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i.MX fixes for 5.6:

Browse Source 
- Build v7_cpu_resume() unconditionally to fix system hang in case that
    suspend is disabled but cpuidle support is enabled.
  - Drop unexisting Ethernet PHY device from imx8qxp-mek board.
  - Fix SRAM compatible strings on imx6dl-colibri-eval-v3 board.
  - Fix imx-scu driver to make sure that all messages words are written
    sequentially.
  - A series from Leonard Crestez to fix i.MX SC API users, having all
    messages aligned on 4 bytes.
  - Fix eMMC supply for phycore-som board.
  - Drop bogus frequency setting from imx7-colibri SD/MMC device, so that
    HS200 mode starts working and delivers better performance.
  - Fix opp-supported-hw for i.MX7D to get consumer and industrial parts
    work with correct frequency settings.
  - Restore MDIO compatible to the correct one for LS1021A SoC.
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Merge tag 'imx-fixes-5.6' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/fixes

i.MX fixes for 5.6:

 - Build v7_cpu_resume() unconditionally to fix system hang in case that
   suspend is disabled but cpuidle support is enabled.
 - Drop unexisting Ethernet PHY device from imx8qxp-mek board.
 - Fix SRAM compatible strings on imx6dl-colibri-eval-v3 board.
 - Fix imx-scu driver to make sure that all messages words are written
   sequentially.
 - A series from Leonard Crestez to fix i.MX SC API users, having all
   messages aligned on 4 bytes.
 - Fix eMMC supply for phycore-som board.
 - Drop bogus frequency setting from imx7-colibri SD/MMC device, so that
   HS200 mode starts working and delivers better performance.
 - Fix opp-supported-hw for i.MX7D to get consumer and industrial parts
   work with correct frequency settings.
 - Restore MDIO compatible to the correct one for LS1021A SoC.

* tag 'imx-fixes-5.6' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  soc: imx-scu: Align imx sc msg structs to 4
  firmware: imx: Align imx_sc_msg_req_cpu_start to 4
  firmware: imx: scu-pd: Align imx sc msg structs to 4
  firmware: imx: misc: Align imx sc msg structs to 4
  firmware: imx: scu: Ensure sequential TX
  ARM: dts: imx7-colibri: Fix frequency for sd/mmc
  arm64: dts: imx8qxp-mek: Remove unexisting Ethernet PHY
  ARM: dts: imx6dl-colibri-eval-v3: fix sram compatible properties
  ARM: dts: ls1021a: Restore MDIO compatible to gianfar
  ARM: dts: imx7d: fix opp-supported-hw
  ARM: imx: build v7_cpu_resume() unconditionally
  ARM: dts: imx6: phycore-som: fix emmc supply

Link: https://lore.kernel.org/r/20200224120334.GH27688@dragon
Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2020-02-24 09:57:04 -08:00
commit f1e4920fe3
14 changed files with 68 additions and 36 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts
View File

@ -275,7 +275,7 @@
/* SRAM on Colibri nEXT_CS0 */
sram@0,0 {
compatible = "cypress,cy7c1019dv33-10zsxi, mtd-ram";
compatible = "cypress,cy7c1019dv33-10zsxi", "mtd-ram";
reg = <0 0 0x00010000>;
#address-cells = <1>;
#size-cells = <1>;
@ -286,7 +286,7 @@
/* SRAM on Colibri nEXT_CS1 */
sram@1,0 {
compatible = "cypress,cy7c1019dv33-10zsxi, mtd-ram";
compatible = "cypress,cy7c1019dv33-10zsxi", "mtd-ram";
reg = <1 0 0x00010000>;
#address-cells = <1>;
#size-cells = <1>;

1
arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi
View File

@ -192,7 +192,6 @@
pinctrl-0 = <&pinctrl_usdhc4>;
bus-width = <8>;
non-removable;
vmmc-supply = <&vdd_emmc_1p8>;
status = "disabled";
};

1
arch/arm/boot/dts/imx7-colibri.dtsi
View File

@ -336,7 +336,6 @@
assigned-clock-rates = <400000000>;
bus-width = <8>;
fsl,tuning-step = <2>;
max-frequency = <100000000>;
vmmc-supply = <&reg_module_3v3>;
vqmmc-supply = <&reg_DCDC3>;
non-removable;

6
arch/arm/boot/dts/imx7d.dtsi
View File

@ -44,7 +44,7 @@
opp-hz = /bits/ 64 <792000000>;
opp-microvolt = <1000000>;
clock-latency-ns = <150000>;
opp-supported-hw = <0xd>, <0xf>;
opp-supported-hw = <0xd>, <0x7>;
opp-suspend;
};
@ -52,7 +52,7 @@
opp-hz = /bits/ 64 <996000000>;
opp-microvolt = <1100000>;
clock-latency-ns = <150000>;
opp-supported-hw = <0xc>, <0xf>;
opp-supported-hw = <0xc>, <0x7>;
opp-suspend;
};
@ -60,7 +60,7 @@
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <1225000>;
clock-latency-ns = <150000>;
opp-supported-hw = <0x8>, <0xf>;
opp-supported-hw = <0x8>, <0x3>;
opp-suspend;
};
};

4
arch/arm/boot/dts/ls1021a.dtsi
View File

@ -747,7 +747,7 @@
};
mdio0: mdio@2d24000 {
compatible = "fsl,etsec2-mdio";
compatible = "gianfar";
device_type = "mdio";
#address-cells = <1>;
#size-cells = <0>;
@ -756,7 +756,7 @@
};
mdio1: mdio@2d64000 {
compatible = "fsl,etsec2-mdio";
compatible = "gianfar";
device_type = "mdio";
#address-cells = <1>;
#size-cells = <0>;

2
arch/arm/mach-imx/Makefile
View File

@ -91,6 +91,8 @@ AFLAGS_suspend-imx6.o :=-Wa,-march=armv7-a
obj-$(CONFIG_SOC_IMX6) += suspend-imx6.o
obj-$(CONFIG_SOC_IMX53) += suspend-imx53.o
endif
AFLAGS_resume-imx6.o :=-Wa,-march=armv7-a
obj-$(CONFIG_SOC_IMX6) += resume-imx6.o
obj-$(CONFIG_SOC_IMX6) += pm-imx6.o
obj-$(CONFIG_SOC_IMX1) += mach-imx1.o

4
arch/arm/mach-imx/common.h
View File

@ -109,17 +109,17 @@ void imx_cpu_die(unsigned int cpu);
int imx_cpu_kill(unsigned int cpu);
#ifdef CONFIG_SUSPEND
void v7_cpu_resume(void);
void imx53_suspend(void __iomem *ocram_vbase);
extern const u32 imx53_suspend_sz;
void imx6_suspend(void __iomem *ocram_vbase);
#else
static inline void v7_cpu_resume(void) {}
static inline void imx53_suspend(void __iomem *ocram_vbase) {}
static const u32 imx53_suspend_sz;
static inline void imx6_suspend(void __iomem *ocram_vbase) {}
#endif
void v7_cpu_resume(void);
void imx6_pm_ccm_init(const char *ccm_compat);
void imx6q_pm_init(void);
void imx6dl_pm_init(void);

24
arch/arm/mach-imx/resume-imx6.S Normal file
View File

@ -0,0 +1,24 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright 2014 Freescale Semiconductor, Inc.
*/
#include <linux/linkage.h>
#include <asm/assembler.h>
#include <asm/asm-offsets.h>
#include <asm/hardware/cache-l2x0.h>
#include "hardware.h"
/*
* The following code must assume it is running from physical address
* where absolute virtual addresses to the data section have to be
* turned into relative ones.
*/
ENTRY(v7_cpu_resume)
bl v7_invalidate_l1
#ifdef CONFIG_CACHE_L2X0
bl l2c310_early_resume
#endif
b cpu_resume
ENDPROC(v7_cpu_resume)

14
arch/arm/mach-imx/suspend-imx6.S
View File

@ -327,17 +327,3 @@ resume:
ret lr
ENDPROC(imx6_suspend)
/*
* The following code must assume it is running from physical address
* where absolute virtual addresses to the data section have to be
* turned into relative ones.
*/
ENTRY(v7_cpu_resume)
bl v7_invalidate_l1
#ifdef CONFIG_CACHE_L2X0
bl l2c310_early_resume
#endif
b cpu_resume
ENDPROC(v7_cpu_resume)

5
arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
View File

@ -52,11 +52,6 @@
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
};
ethphy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
};
};

27
drivers/firmware/imx/imx-scu.c
View File

@ -29,6 +29,7 @@ struct imx_sc_chan {
struct mbox_client cl;
struct mbox_chan *ch;
int idx;
struct completion tx_done;
};
struct imx_sc_ipc {
@ -100,6 +101,14 @@ int imx_scu_get_handle(struct imx_sc_ipc **ipc)
}
EXPORT_SYMBOL(imx_scu_get_handle);
/* Callback called when the word of a message is ack-ed, eg read by SCU */
static void imx_scu_tx_done(struct mbox_client *cl, void *mssg, int r)
{
struct imx_sc_chan *sc_chan = container_of(cl, struct imx_sc_chan, cl);
complete(&sc_chan->tx_done);
}
static void imx_scu_rx_callback(struct mbox_client *c, void *msg)
{
struct imx_sc_chan *sc_chan = container_of(c, struct imx_sc_chan, cl);
@ -149,6 +158,19 @@ static int imx_scu_ipc_write(struct imx_sc_ipc *sc_ipc, void *msg)
for (i = 0; i < hdr->size; i++) {
sc_chan = &sc_ipc->chans[i % 4];
/*
* SCU requires that all messages words are written
* sequentially but linux MU driver implements multiple
* independent channels for each register so ordering between
* different channels must be ensured by SCU API interface.
*
* Wait for tx_done before every send to ensure that no
* queueing happens at the mailbox channel level.
*/
wait_for_completion(&sc_chan->tx_done);
reinit_completion(&sc_chan->tx_done);
ret = mbox_send_message(sc_chan->ch, &data[i]);
if (ret < 0)
return ret;
@ -247,6 +269,11 @@ static int imx_scu_probe(struct platform_device *pdev)
cl->knows_txdone = true;
cl->rx_callback = imx_scu_rx_callback;
/* Initial tx_done completion as "done" */
cl->tx_done = imx_scu_tx_done;
init_completion(&sc_chan->tx_done);
complete(&sc_chan->tx_done);
sc_chan->sc_ipc = sc_ipc;
sc_chan->idx = i % 4;
sc_chan->ch = mbox_request_channel_byname(cl, chan_name);

8
drivers/firmware/imx/misc.c
View File

@ -16,7 +16,7 @@ struct imx_sc_msg_req_misc_set_ctrl {
u32 ctrl;
u32 val;
u16 resource;
} __packed;
} __packed __aligned(4);
struct imx_sc_msg_req_cpu_start {
struct imx_sc_rpc_msg hdr;
@ -24,18 +24,18 @@ struct imx_sc_msg_req_cpu_start {
u32 address_lo;
u16 resource;
u8 enable;
} __packed;
} __packed __aligned(4);
struct imx_sc_msg_req_misc_get_ctrl {
struct imx_sc_rpc_msg hdr;
u32 ctrl;
u16 resource;
} __packed;
} __packed __aligned(4);
struct imx_sc_msg_resp_misc_get_ctrl {
struct imx_sc_rpc_msg hdr;
u32 val;
} __packed;
} __packed __aligned(4);
/*
* This function sets a miscellaneous control value.

2
drivers/firmware/imx/scu-pd.c
View File

@ -61,7 +61,7 @@ struct imx_sc_msg_req_set_resource_power_mode {
struct imx_sc_rpc_msg hdr;
u16 resource;
u8 mode;
} __packed;
} __packed __aligned(4);
#define IMX_SCU_PD_NAME_SIZE 20
struct imx_sc_pm_domain {

2
drivers/soc/imx/soc-imx-scu.c
View File

@ -25,7 +25,7 @@ struct imx_sc_msg_misc_get_soc_id {
u32 id;
} resp;
} data;
} __packed;
} __packed __aligned(4);
struct imx_sc_msg_misc_get_soc_uid {
struct imx_sc_rpc_msg hdr;