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UniCore32 bug fixes for 3.16-rc1
-----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.10 (GNU/Linux) iQIcBAABAgAGBQJTo9f6AAoJENFylnOm3dTb9C0P/2WzzkWssoDN+Fe5I1Fx2mU6 b2Ejqgv1ygygXWUDhXScdcG7jFFIa86Bpo2iGhc+egNmMW+ePad1Pq2o186V4TSu wq3SFmJb/0yjoG1+7Tea69AhEk+NB5cLGunAc+4vP53yvjFlM3bR0IZQ3RKbc72o cpEjZ7V2sXB3LxdkPIqqc3nOrettrLXFioRLGim4pNXdABPPvfFsNuJPbJxrNqgW nZbWJ949iTGigAldyJemMHNVC93nZmR+NkZxKOI0L0yLKnkW9/HaQzLOc7G+bMe7 I0uRdGDN/n+2vw/fhLJ2H+Qkks4GmRvgX3cvERT4euE9ZfUSmA0NQJX7R+oVjFr5 hX8/Et9YSPMlXSGcGyZiOnAtrdsiTV+xW+DN9h7/kbC4f9n3VuAVgaaQtmJ9V43L 7zQXeVagXxusbPvNE9b6i3bTD6Ow03mTG4OmEFpXknNFIhfAKKSXzFpFywQ7j4yZ YfLRhT5Ch3hr51ChmAiApDie/in5ZAkCpbkvzRAQvppMNRpbBVbfU3e/Rc/C8WM3 IZeL/VG+HvMwcPOnNyOFcDCVCWQAMqnyjJtXoFLqxN0KfWCY/B3FVzMiyB5z3W6i RNmU57CBe6HWQfWFLR7zzVOlPNS3xRand6VYLP1LV4LQstBGsVPNqPxvlzF3O+bK KCGeMkMPMhQsRewRAt+y =Lb1U -----END PGP SIGNATURE----- Merge tag 'for-linus' of git://github.com/gxt/linux Pull UniCore32 bug fixes from Guan Xuetao: "This includes bugfixes to make unicore32 successfully build under defconfig, and some changes for allmodconfig (though not finished)" * tag 'for-linus' of git://github.com/gxt/linux: unicore32: Remove ARCH_HAS_CPUFREQ config option UniCore32: Change git tree location information in MAINTAINERS arch: unicore32: ksyms: export '__cpuc_coherent_kern_range' to avoid compiling failure arch: unicore32: ksyms: export 'pm_power_off' to avoid compiling failure. arch: unicore32: ksyms: export additional find_first_*() to avoid compiling failure arch:unicore32:mm: add devmem_is_allowed() to support STRICT_DEVMEM unicore32: include: asm: add missing ')' for PAGE_* macros in pgtable.h arch/unicore32/kernel/setup.c: add generic 'screen_info' to avoid compiling failure drivers: scsi: mvsas: fix compiling issue by adding 'MVS_' for "enum pci_interrupt_cause" arch: unicore32: kernel: ksyms: remove 'bswapsi2' and 'muldi3' to avoid compiling failure arch/unicore32/kernel/ksyms.c: remove 2 export symbols to avoid compiling failure drivers/rtc/rtc-puv3.c: remove "&dev->" for typo issue MIME-Version: 1.0 drivers/rtc/rtc-puv3.c: use dev_dbg() instead of dev_debug() for typo issue arch/unicore32/include/asm/io.h: add readl_relaxed() generic definition arch/unicore32/include/asm/ptrace.h: add generic definition for profile_pc() arch/unicore32/mm/alignment.c: include "asm/pgtable.h" to avoid compiling error arch/unicore32/kernel/clock.c: add readl() and writel() for 'PM_' macros arch/unicore32/kernel/module.c: use __vmalloc_node_range() instead of __vmalloc_area() arch/unicore32/kernel/ksyms.c: remove several undefined exported symbols
This commit is contained in:
commit
f1b35b8305
@ -6960,7 +6960,7 @@ PKUNITY SOC DRIVERS
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M: Guan Xuetao <gxt@mprc.pku.edu.cn>
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W: http://mprc.pku.edu.cn/~guanxuetao/linux
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S: Maintained
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T: git git://git.kernel.org/pub/scm/linux/kernel/git/epip/linux-2.6-unicore32.git
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T: git git://github.com/gxt/linux.git
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F: drivers/input/serio/i8042-unicore32io.h
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F: drivers/i2c/busses/i2c-puv3.c
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F: drivers/video/fb-puv3.c
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@ -9277,7 +9277,7 @@ UNICORE32 ARCHITECTURE:
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M: Guan Xuetao <gxt@mprc.pku.edu.cn>
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W: http://mprc.pku.edu.cn/~guanxuetao/linux
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S: Maintained
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T: git git://git.kernel.org/pub/scm/linux/kernel/git/epip/linux-2.6-unicore32.git
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T: git git://github.com/gxt/linux.git
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F: arch/unicore32/
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UNIFDEF
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@ -51,9 +51,6 @@ config ARCH_HAS_ILOG2_U32
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config ARCH_HAS_ILOG2_U64
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bool
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config ARCH_HAS_CPUFREQ
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bool
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config GENERIC_HWEIGHT
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def_bool y
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@ -87,7 +84,6 @@ config ARCH_PUV3
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select GENERIC_CLOCKEVENTS
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select HAVE_CLK
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select ARCH_REQUIRE_GPIOLIB
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select ARCH_HAS_CPUFREQ
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# CONFIGs for ARCH_PUV3
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@ -198,9 +194,7 @@ menu "Power management options"
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source "kernel/power/Kconfig"
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if ARCH_HAS_CPUFREQ
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source "drivers/cpufreq/Kconfig"
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endif
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config ARCH_SUSPEND_POSSIBLE
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def_bool y if !ARCH_FPGA
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@ -39,10 +39,37 @@ extern void __uc32_iounmap(volatile void __iomem *addr);
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#define ioremap_nocache(cookie, size) __uc32_ioremap(cookie, size)
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#define iounmap(cookie) __uc32_iounmap(cookie)
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#define readb_relaxed readb
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#define readw_relaxed readw
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#define readl_relaxed readl
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#define HAVE_ARCH_PIO_SIZE
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#define PIO_OFFSET (unsigned int)(PCI_IOBASE)
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#define PIO_MASK (unsigned int)(IO_SPACE_LIMIT)
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#define PIO_RESERVED (PIO_OFFSET + PIO_MASK + 1)
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#ifdef CONFIG_STRICT_DEVMEM
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#include <linux/ioport.h>
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#include <linux/mm.h>
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/*
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* devmem_is_allowed() checks to see if /dev/mem access to a certain
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* address is valid. The argument is a physical page number.
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* We mimic x86 here by disallowing access to system RAM as well as
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* device-exclusive MMIO regions. This effectively disable read()/write()
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* on /dev/mem.
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*/
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static inline int devmem_is_allowed(unsigned long pfn)
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{
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if (iomem_is_exclusive(pfn << PAGE_SHIFT))
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return 0;
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if (!page_is_ram(pfn))
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return 1;
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return 0;
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}
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#endif /* CONFIG_STRICT_DEVMEM */
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#endif /* __KERNEL__ */
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#endif /* __UNICORE_IO_H__ */
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@ -87,16 +87,16 @@ extern pgprot_t pgprot_kernel;
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#define PAGE_NONE pgprot_user
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#define PAGE_SHARED __pgprot(pgprot_val(pgprot_user | PTE_READ \
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| PTE_WRITE)
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| PTE_WRITE))
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#define PAGE_SHARED_EXEC __pgprot(pgprot_val(pgprot_user | PTE_READ \
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| PTE_WRITE \
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| PTE_EXEC)
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| PTE_EXEC))
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#define PAGE_COPY __pgprot(pgprot_val(pgprot_user | PTE_READ)
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#define PAGE_COPY_EXEC __pgprot(pgprot_val(pgprot_user | PTE_READ \
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| PTE_EXEC)
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#define PAGE_READONLY __pgprot(pgprot_val(pgprot_user | PTE_READ)
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| PTE_EXEC))
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#define PAGE_READONLY __pgprot(pgprot_val(pgprot_user | PTE_READ))
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#define PAGE_READONLY_EXEC __pgprot(pgprot_val(pgprot_user | PTE_READ \
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| PTE_EXEC)
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| PTE_EXEC))
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#define PAGE_KERNEL pgprot_kernel
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#define PAGE_KERNEL_EXEC __pgprot(pgprot_val(pgprot_kernel | PTE_EXEC))
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@ -55,6 +55,7 @@ static inline int valid_user_regs(struct pt_regs *regs)
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#define instruction_pointer(regs) ((regs)->UCreg_pc)
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#define user_stack_pointer(regs) ((regs)->UCreg_sp)
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#define profile_pc(regs) instruction_pointer(regs)
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#endif /* __ASSEMBLY__ */
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#endif
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|
@ -179,7 +179,7 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
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}
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#ifdef CONFIG_CPU_FREQ
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if (clk == &clk_mclk_clk) {
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u32 pll_rate, divstatus = PM_DIVSTATUS;
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u32 pll_rate, divstatus = readl(PM_DIVSTATUS);
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int ret, i;
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/* lookup mclk_clk_table */
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@ -201,10 +201,10 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
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/ (((divstatus & 0x0000f000) >> 12) + 1);
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/* set pll sys cfg reg. */
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PM_PLLSYSCFG = pll_rate;
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writel(pll_rate, PM_PLLSYSCFG);
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PM_PMCR = PM_PMCR_CFBSYS;
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while ((PM_PLLDFCDONE & PM_PLLDFCDONE_SYSDFC)
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writel(PM_PMCR_CFBSYS, PM_PMCR);
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while ((readl(PM_PLLDFCDONE) & PM_PLLDFCDONE_SYSDFC)
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!= PM_PLLDFCDONE_SYSDFC)
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udelay(100);
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/* about 1ms */
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@ -23,41 +23,15 @@
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#include "ksyms.h"
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EXPORT_SYMBOL(find_first_bit);
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EXPORT_SYMBOL(find_first_zero_bit);
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EXPORT_SYMBOL(find_next_zero_bit);
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EXPORT_SYMBOL(find_next_bit);
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EXPORT_SYMBOL(__backtrace);
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/* platform dependent support */
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EXPORT_SYMBOL(__udelay);
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EXPORT_SYMBOL(__const_udelay);
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/* networking */
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EXPORT_SYMBOL(csum_partial);
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EXPORT_SYMBOL(csum_partial_copy_from_user);
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EXPORT_SYMBOL(csum_partial_copy_nocheck);
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EXPORT_SYMBOL(__csum_ipv6_magic);
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/* io */
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#ifndef __raw_readsb
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EXPORT_SYMBOL(__raw_readsb);
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#endif
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#ifndef __raw_readsw
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EXPORT_SYMBOL(__raw_readsw);
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#endif
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#ifndef __raw_readsl
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EXPORT_SYMBOL(__raw_readsl);
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#endif
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#ifndef __raw_writesb
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EXPORT_SYMBOL(__raw_writesb);
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#endif
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#ifndef __raw_writesw
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EXPORT_SYMBOL(__raw_writesw);
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#endif
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#ifndef __raw_writesl
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EXPORT_SYMBOL(__raw_writesl);
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#endif
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/* string / mem functions */
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EXPORT_SYMBOL(strchr);
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EXPORT_SYMBOL(strrchr);
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@ -76,23 +50,12 @@ EXPORT_SYMBOL(__copy_from_user);
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EXPORT_SYMBOL(__copy_to_user);
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EXPORT_SYMBOL(__clear_user);
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EXPORT_SYMBOL(__get_user_1);
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EXPORT_SYMBOL(__get_user_2);
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EXPORT_SYMBOL(__get_user_4);
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EXPORT_SYMBOL(__put_user_1);
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EXPORT_SYMBOL(__put_user_2);
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EXPORT_SYMBOL(__put_user_4);
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EXPORT_SYMBOL(__put_user_8);
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EXPORT_SYMBOL(__ashldi3);
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EXPORT_SYMBOL(__ashrdi3);
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EXPORT_SYMBOL(__divsi3);
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EXPORT_SYMBOL(__lshrdi3);
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EXPORT_SYMBOL(__modsi3);
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EXPORT_SYMBOL(__muldi3);
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EXPORT_SYMBOL(__ucmpdi2);
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EXPORT_SYMBOL(__udivsi3);
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EXPORT_SYMBOL(__umodsi3);
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EXPORT_SYMBOL(__bswapsi2);
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@ -8,8 +8,6 @@ extern void __ashrdi3(void);
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extern void __divsi3(void);
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extern void __lshrdi3(void);
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extern void __modsi3(void);
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extern void __muldi3(void);
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extern void __ucmpdi2(void);
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extern void __udivsi3(void);
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extern void __umodsi3(void);
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extern void __bswapsi2(void);
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@ -24,14 +24,9 @@
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void *module_alloc(unsigned long size)
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{
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struct vm_struct *area;
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size = PAGE_ALIGN(size);
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area = __get_vm_area(size, VM_ALLOC, MODULES_VADDR, MODULES_END);
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if (!area)
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return NULL;
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return __vmalloc_area(area, GFP_KERNEL, PAGE_KERNEL_EXEC);
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return __vmalloc_node_range(size, 1, MODULES_VADDR, MODULES_END,
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GFP_KERNEL, PAGE_KERNEL_EXEC, NUMA_NO_NODE,
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__builtin_return_address(0));
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}
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int
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@ -60,6 +60,7 @@ void machine_halt(void)
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* Function pointers to optional machine specific functions
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*/
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void (*pm_power_off)(void) = NULL;
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EXPORT_SYMBOL(pm_power_off);
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void machine_power_off(void)
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{
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@ -53,6 +53,10 @@ struct stack {
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static struct stack stacks[NR_CPUS];
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#ifdef CONFIG_VGA_CONSOLE
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struct screen_info screen_info;
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#endif
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char elf_platform[ELF_PLATFORM_SIZE];
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EXPORT_SYMBOL(elf_platform);
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@ -21,6 +21,7 @@
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#include <linux/sched.h>
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#include <linux/uaccess.h>
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#include <asm/pgtable.h>
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#include <asm/tlbflush.h>
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#include <asm/unaligned.h>
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@ -19,5 +19,7 @@
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EXPORT_SYMBOL(cpu_dcache_clean_area);
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EXPORT_SYMBOL(cpu_set_pte);
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EXPORT_SYMBOL(__cpuc_coherent_kern_range);
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EXPORT_SYMBOL(__cpuc_dma_flush_range);
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EXPORT_SYMBOL(__cpuc_dma_clean_range);
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|
@ -71,7 +71,7 @@ static int puv3_rtc_setpie(struct device *dev, int enabled)
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{
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unsigned int tmp;
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dev_debug(dev, "%s: pie=%d\n", __func__, enabled);
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dev_dbg(dev, "%s: pie=%d\n", __func__, enabled);
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spin_lock_irq(&puv3_rtc_pie_lock);
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tmp = readl(RTC_RTSR) & ~RTC_RTSR_HZE;
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@ -140,7 +140,7 @@ static int puv3_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
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rtc_tm_to_time(tm, &rtcalarm_count);
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writel(rtcalarm_count, RTC_RTAR);
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puv3_rtc_setaie(&dev->dev, alrm->enabled);
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puv3_rtc_setaie(dev, alrm->enabled);
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if (alrm->enabled)
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enable_irq_wake(puv3_rtc_alarmno);
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|
@ -564,7 +564,7 @@ static void mvs_94xx_interrupt_enable(struct mvs_info *mvi)
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u32 tmp;
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tmp = mr32(MVS_GBL_CTL);
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tmp |= (IRQ_SAS_A | IRQ_SAS_B);
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tmp |= (MVS_IRQ_SAS_A | MVS_IRQ_SAS_B);
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mw32(MVS_GBL_INT_STAT, tmp);
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writel(tmp, regs + 0x0C);
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writel(tmp, regs + 0x10);
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@ -580,7 +580,7 @@ static void mvs_94xx_interrupt_disable(struct mvs_info *mvi)
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tmp = mr32(MVS_GBL_CTL);
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tmp &= ~(IRQ_SAS_A | IRQ_SAS_B);
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tmp &= ~(MVS_IRQ_SAS_A | MVS_IRQ_SAS_B);
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mw32(MVS_GBL_INT_STAT, tmp);
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writel(tmp, regs + 0x0C);
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writel(tmp, regs + 0x10);
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@ -596,7 +596,7 @@ static u32 mvs_94xx_isr_status(struct mvs_info *mvi, int irq)
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if (!(mvi->flags & MVF_FLAG_SOC)) {
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stat = mr32(MVS_GBL_INT_STAT);
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if (!(stat & (IRQ_SAS_A | IRQ_SAS_B)))
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if (!(stat & (MVS_IRQ_SAS_A | MVS_IRQ_SAS_B)))
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return 0;
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}
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return stat;
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@ -606,8 +606,8 @@ static irqreturn_t mvs_94xx_isr(struct mvs_info *mvi, int irq, u32 stat)
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{
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void __iomem *regs = mvi->regs;
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if (((stat & IRQ_SAS_A) && mvi->id == 0) ||
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((stat & IRQ_SAS_B) && mvi->id == 1)) {
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if (((stat & MVS_IRQ_SAS_A) && mvi->id == 0) ||
|
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((stat & MVS_IRQ_SAS_B) && mvi->id == 1)) {
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mw32_f(MVS_INT_STAT, CINT_DONE);
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|
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spin_lock(&mvi->lock);
|
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|
@ -150,35 +150,35 @@ enum chip_register_bits {
|
||||
|
||||
enum pci_interrupt_cause {
|
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/* MAIN_IRQ_CAUSE (R10200) Bits*/
|
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IRQ_COM_IN_I2O_IOP0 = (1 << 0),
|
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IRQ_COM_IN_I2O_IOP1 = (1 << 1),
|
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IRQ_COM_IN_I2O_IOP2 = (1 << 2),
|
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IRQ_COM_IN_I2O_IOP3 = (1 << 3),
|
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IRQ_COM_OUT_I2O_HOS0 = (1 << 4),
|
||||
IRQ_COM_OUT_I2O_HOS1 = (1 << 5),
|
||||
IRQ_COM_OUT_I2O_HOS2 = (1 << 6),
|
||||
IRQ_COM_OUT_I2O_HOS3 = (1 << 7),
|
||||
IRQ_PCIF_TO_CPU_DRBL0 = (1 << 8),
|
||||
IRQ_PCIF_TO_CPU_DRBL1 = (1 << 9),
|
||||
IRQ_PCIF_TO_CPU_DRBL2 = (1 << 10),
|
||||
IRQ_PCIF_TO_CPU_DRBL3 = (1 << 11),
|
||||
IRQ_PCIF_DRBL0 = (1 << 12),
|
||||
IRQ_PCIF_DRBL1 = (1 << 13),
|
||||
IRQ_PCIF_DRBL2 = (1 << 14),
|
||||
IRQ_PCIF_DRBL3 = (1 << 15),
|
||||
IRQ_XOR_A = (1 << 16),
|
||||
IRQ_XOR_B = (1 << 17),
|
||||
IRQ_SAS_A = (1 << 18),
|
||||
IRQ_SAS_B = (1 << 19),
|
||||
IRQ_CPU_CNTRL = (1 << 20),
|
||||
IRQ_GPIO = (1 << 21),
|
||||
IRQ_UART = (1 << 22),
|
||||
IRQ_SPI = (1 << 23),
|
||||
IRQ_I2C = (1 << 24),
|
||||
IRQ_SGPIO = (1 << 25),
|
||||
IRQ_COM_ERR = (1 << 29),
|
||||
IRQ_I2O_ERR = (1 << 30),
|
||||
IRQ_PCIE_ERR = (1 << 31),
|
||||
MVS_IRQ_COM_IN_I2O_IOP0 = (1 << 0),
|
||||
MVS_IRQ_COM_IN_I2O_IOP1 = (1 << 1),
|
||||
MVS_IRQ_COM_IN_I2O_IOP2 = (1 << 2),
|
||||
MVS_IRQ_COM_IN_I2O_IOP3 = (1 << 3),
|
||||
MVS_IRQ_COM_OUT_I2O_HOS0 = (1 << 4),
|
||||
MVS_IRQ_COM_OUT_I2O_HOS1 = (1 << 5),
|
||||
MVS_IRQ_COM_OUT_I2O_HOS2 = (1 << 6),
|
||||
MVS_IRQ_COM_OUT_I2O_HOS3 = (1 << 7),
|
||||
MVS_IRQ_PCIF_TO_CPU_DRBL0 = (1 << 8),
|
||||
MVS_IRQ_PCIF_TO_CPU_DRBL1 = (1 << 9),
|
||||
MVS_IRQ_PCIF_TO_CPU_DRBL2 = (1 << 10),
|
||||
MVS_IRQ_PCIF_TO_CPU_DRBL3 = (1 << 11),
|
||||
MVS_IRQ_PCIF_DRBL0 = (1 << 12),
|
||||
MVS_IRQ_PCIF_DRBL1 = (1 << 13),
|
||||
MVS_IRQ_PCIF_DRBL2 = (1 << 14),
|
||||
MVS_IRQ_PCIF_DRBL3 = (1 << 15),
|
||||
MVS_IRQ_XOR_A = (1 << 16),
|
||||
MVS_IRQ_XOR_B = (1 << 17),
|
||||
MVS_IRQ_SAS_A = (1 << 18),
|
||||
MVS_IRQ_SAS_B = (1 << 19),
|
||||
MVS_IRQ_CPU_CNTRL = (1 << 20),
|
||||
MVS_IRQ_GPIO = (1 << 21),
|
||||
MVS_IRQ_UART = (1 << 22),
|
||||
MVS_IRQ_SPI = (1 << 23),
|
||||
MVS_IRQ_I2C = (1 << 24),
|
||||
MVS_IRQ_SGPIO = (1 << 25),
|
||||
MVS_IRQ_COM_ERR = (1 << 29),
|
||||
MVS_IRQ_I2O_ERR = (1 << 30),
|
||||
MVS_IRQ_PCIE_ERR = (1 << 31),
|
||||
};
|
||||
|
||||
union reg_phy_cfg {
|
||||
|
Loading…
Reference in New Issue
Block a user