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clk: samsung: exynos5433: Drop RO registers from the save/restore lists
Restoring read-only registers is of not much effect, drop them from the respective lists. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This commit is contained in:
Sylwester Nawrocki
parent
f190a87e27
commit
f0abd93125
@ -142,17 +142,6 @@ static unsigned long top_clk_regs[] __initdata = {
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MUX_ENABLE_TOP_FSYS1,
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MUX_ENABLE_TOP_PERIC0,
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MUX_ENABLE_TOP_PERIC1,
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MUX_STAT_TOP0,
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MUX_STAT_TOP1,
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MUX_STAT_TOP2,
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MUX_STAT_TOP3,
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MUX_STAT_TOP4,
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MUX_STAT_TOP_MSCL,
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MUX_STAT_TOP_CAM1,
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MUX_STAT_TOP_FSYS0,
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MUX_STAT_TOP_FSYS1,
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MUX_STAT_TOP_PERIC0,
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MUX_STAT_TOP_PERIC1,
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DIV_TOP0,
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DIV_TOP1,
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DIV_TOP2,
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@ -170,22 +159,6 @@ static unsigned long top_clk_regs[] __initdata = {
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DIV_TOP_PERIC3,
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DIV_TOP_PERIC4,
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DIV_TOP_PLL_FREQ_DET,
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DIV_STAT_TOP0,
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DIV_STAT_TOP1,
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DIV_STAT_TOP2,
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DIV_STAT_TOP3,
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DIV_STAT_TOP4,
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DIV_STAT_TOP_MSCL,
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DIV_STAT_TOP_CAM10,
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DIV_STAT_TOP_CAM11,
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DIV_STAT_TOP_FSYS0,
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DIV_STAT_TOP_FSYS1,
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DIV_STAT_TOP_FSYS2,
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DIV_STAT_TOP_PERIC0,
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DIV_STAT_TOP_PERIC1,
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DIV_STAT_TOP_PERIC2,
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DIV_STAT_TOP_PERIC3,
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DIV_STAT_TOP_PLL_FREQ_DET,
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ENABLE_ACLK_TOP,
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ENABLE_SCLK_TOP,
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ENABLE_SCLK_TOP_MSCL,
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@ -999,26 +972,12 @@ static unsigned long mif_clk_regs[] __initdata = {
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MUX_ENABLE_MIF5,
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MUX_ENABLE_MIF6,
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MUX_ENABLE_MIF7,
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MUX_STAT_MIF0,
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MUX_STAT_MIF1,
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MUX_STAT_MIF2,
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MUX_STAT_MIF3,
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MUX_STAT_MIF4,
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MUX_STAT_MIF5,
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MUX_STAT_MIF6,
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MUX_STAT_MIF7,
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DIV_MIF1,
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DIV_MIF2,
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DIV_MIF3,
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DIV_MIF4,
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DIV_MIF5,
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DIV_MIF_PLL_FREQ_DET,
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DIV_STAT_MIF1,
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DIV_STAT_MIF2,
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DIV_STAT_MIF3,
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DIV_STAT_MIF4,
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DIV_STAT_MIF5,
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DIV_STAT_MIF_PLL_FREQ_DET,
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ENABLE_ACLK_MIF0,
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ENABLE_ACLK_MIF1,
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ENABLE_ACLK_MIF2,
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@ -1565,7 +1524,6 @@ CLK_OF_DECLARE(exynos5433_cmu_mif, "samsung,exynos5433-cmu-mif",
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static unsigned long peric_clk_regs[] __initdata = {
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DIV_PERIC,
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DIV_STAT_PERIC,
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ENABLE_ACLK_PERIC,
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ENABLE_PCLK_PERIC0,
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ENABLE_PCLK_PERIC1,
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@ -2012,11 +1970,6 @@ static unsigned long fsys_clk_regs[] __initdata = {
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MUX_ENABLE_FSYS2,
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MUX_ENABLE_FSYS3,
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MUX_ENABLE_FSYS4,
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MUX_STAT_FSYS0,
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MUX_STAT_FSYS1,
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MUX_STAT_FSYS2,
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MUX_STAT_FSYS3,
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MUX_STAT_FSYS4,
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MUX_IGNORE_FSYS2,
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MUX_IGNORE_FSYS3,
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ENABLE_ACLK_FSYS0,
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@ -2362,9 +2315,7 @@ CLK_OF_DECLARE(exynos5433_cmu_fsys, "samsung,exynos5433-cmu-fsys",
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static unsigned long g2d_clk_regs[] __initdata = {
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MUX_SEL_G2D0,
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MUX_SEL_ENABLE_G2D0,
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MUX_SEL_STAT_G2D0,
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DIV_G2D,
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DIV_STAT_G2D,
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DIV_ENABLE_ACLK_G2D,
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DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D,
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DIV_ENABLE_PCLK_G2D,
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@ -2520,16 +2471,9 @@ static unsigned long disp_clk_regs[] __initdata = {
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MUX_ENABLE_DISP2,
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MUX_ENABLE_DISP3,
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MUX_ENABLE_DISP4,
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MUX_STAT_DISP0,
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MUX_STAT_DISP1,
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MUX_STAT_DISP2,
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MUX_STAT_DISP3,
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MUX_STAT_DISP4,
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MUX_IGNORE_DISP2,
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DIV_DISP,
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DIV_DISP_PLL_FREQ_DET,
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DIV_STAT_DISP,
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DIV_STAT_DISP_PLL_FREQ_DET,
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ENABLE_ACLK_DISP0,
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ENABLE_ACLK_DISP1,
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ENABLE_PCLK_DISP,
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@ -2923,11 +2867,8 @@ static unsigned long aud_clk_regs[] __initdata = {
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MUX_SEL_AUD1,
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MUX_ENABLE_AUD0,
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MUX_ENABLE_AUD1,
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MUX_STAT_AUD0,
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DIV_AUD0,
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DIV_AUD1,
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DIV_STAT_AUD0,
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DIV_STAT_AUD1,
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ENABLE_ACLK_AUD,
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ENABLE_PCLK_AUD,
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ENABLE_SCLK_AUD0,
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@ -3091,7 +3032,6 @@ PNAME(mout_aclk_bus2_400_p) = { "oscclk", "aclk_bus2_400", };
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#define CMU_BUS_COMMON_CLK_REGS \
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DIV_BUS, \
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DIV_STAT_BUS, \
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ENABLE_ACLK_BUS, \
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ENABLE_PCLK_BUS, \
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ENABLE_IP_BUS0, \
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@ -3104,7 +3044,6 @@ static unsigned long bus01_clk_regs[] __initdata = {
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static unsigned long bus2_clk_regs[] __initdata = {
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MUX_SEL_BUS2,
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MUX_ENABLE_BUS2,
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MUX_STAT_BUS2,
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CMU_BUS_COMMON_CLK_REGS,
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};
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@ -3263,11 +3202,8 @@ static unsigned long g3d_clk_regs[] __initdata = {
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G3D_PLL_FREQ_DET,
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MUX_SEL_G3D,
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MUX_ENABLE_G3D,
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MUX_STAT_G3D,
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DIV_G3D,
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DIV_G3D_PLL_FREQ_DET,
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DIV_STAT_G3D,
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DIV_STAT_G3D_PLL_FREQ_DET,
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ENABLE_ACLK_G3D,
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ENABLE_PCLK_G3D,
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ENABLE_SCLK_G3D,
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@ -3383,7 +3319,6 @@ CLK_OF_DECLARE(exynos5433_cmu_g3d, "samsung,exynos5433-cmu-g3d",
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static unsigned long gscl_clk_regs[] __initdata = {
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MUX_SEL_GSCL,
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MUX_ENABLE_GSCL,
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MUX_STAT_GSCL,
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ENABLE_ACLK_GSCL,
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ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0,
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ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1,
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@ -3547,15 +3482,9 @@ static unsigned long apollo_clk_regs[] __initdata = {
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MUX_ENABLE_APOLLO0,
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MUX_ENABLE_APOLLO1,
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MUX_ENABLE_APOLLO2,
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MUX_STAT_APOLLO0,
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MUX_STAT_APOLLO1,
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MUX_STAT_APOLLO2,
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DIV_APOLLO0,
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DIV_APOLLO1,
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DIV_APOLLO_PLL_FREQ_DET,
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DIV_STAT_APOLLO0,
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DIV_STAT_APOLLO1,
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DIV_STAT_APOLLO_PLL_FREQ_DET,
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ENABLE_ACLK_APOLLO,
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ENABLE_PCLK_APOLLO,
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ENABLE_SCLK_APOLLO,
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@ -3739,15 +3668,9 @@ static unsigned long atlas_clk_regs[] __initdata = {
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MUX_ENABLE_ATLAS0,
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MUX_ENABLE_ATLAS1,
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MUX_ENABLE_ATLAS2,
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MUX_STAT_ATLAS0,
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MUX_STAT_ATLAS1,
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MUX_STAT_ATLAS2,
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DIV_ATLAS0,
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DIV_ATLAS1,
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DIV_ATLAS_PLL_FREQ_DET,
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DIV_STAT_ATLAS0,
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DIV_STAT_ATLAS1,
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DIV_STAT_ATLAS_PLL_FREQ_DET,
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ENABLE_ACLK_ATLAS,
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ENABLE_PCLK_ATLAS,
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ENABLE_SCLK_ATLAS,
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@ -3941,10 +3864,7 @@ static unsigned long mscl_clk_regs[] __initdata = {
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MUX_SEL_MSCL1,
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MUX_ENABLE_MSCL0,
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MUX_ENABLE_MSCL1,
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MUX_STAT_MSCL0,
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MUX_STAT_MSCL1,
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DIV_MSCL,
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DIV_STAT_MSCL,
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ENABLE_ACLK_MSCL,
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ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0,
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ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1,
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@ -4101,9 +4021,7 @@ CLK_OF_DECLARE(exynos5433_cmu_mscl, "samsung,exynos5433-cmu-mscl",
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static unsigned long mfc_clk_regs[] __initdata = {
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MUX_SEL_MFC,
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MUX_ENABLE_MFC,
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MUX_STAT_MFC,
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DIV_MFC,
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DIV_STAT_MFC,
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ENABLE_ACLK_MFC,
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ENABLE_ACLK_MFC_SECURE_SMMU_MFC,
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ENABLE_PCLK_MFC,
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@ -4211,9 +4129,7 @@ CLK_OF_DECLARE(exynos5433_cmu_mfc, "samsung,exynos5433-cmu-mfc",
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static unsigned long hevc_clk_regs[] __initdata = {
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MUX_SEL_HEVC,
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MUX_ENABLE_HEVC,
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MUX_STAT_HEVC,
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DIV_HEVC,
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DIV_STAT_HEVC,
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ENABLE_ACLK_HEVC,
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ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC,
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ENABLE_PCLK_HEVC,
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@ -4325,9 +4241,7 @@ CLK_OF_DECLARE(exynos5433_cmu_hevc, "samsung,exynos5433-cmu-hevc",
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static unsigned long isp_clk_regs[] __initdata = {
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MUX_SEL_ISP,
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MUX_ENABLE_ISP,
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MUX_STAT_ISP,
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DIV_ISP,
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DIV_STAT_ISP,
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ENABLE_ACLK_ISP0,
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ENABLE_ACLK_ISP1,
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ENABLE_ACLK_ISP2,
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@ -4607,20 +4521,11 @@ static unsigned long cam0_clk_regs[] __initdata = {
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MUX_ENABLE_CAM02,
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MUX_ENABLE_CAM03,
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MUX_ENABLE_CAM04,
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MUX_STAT_CAM00,
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MUX_STAT_CAM01,
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MUX_STAT_CAM02,
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MUX_STAT_CAM03,
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MUX_STAT_CAM04,
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MUX_IGNORE_CAM01,
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DIV_CAM00,
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DIV_CAM01,
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DIV_CAM02,
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DIV_CAM03,
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DIV_STAT_CAM00,
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DIV_STAT_CAM01,
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DIV_STAT_CAM02,
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DIV_STAT_CAM03,
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ENABLE_ACLK_CAM00,
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ENABLE_ACLK_CAM01,
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ENABLE_ACLK_CAM02,
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@ -5078,14 +4983,9 @@ static unsigned long cam1_clk_regs[] __initdata = {
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MUX_ENABLE_CAM10,
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MUX_ENABLE_CAM11,
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MUX_ENABLE_CAM12,
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MUX_STAT_CAM10,
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MUX_STAT_CAM11,
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MUX_STAT_CAM12,
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MUX_IGNORE_CAM11,
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DIV_CAM10,
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DIV_CAM11,
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DIV_STAT_CAM10,
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DIV_STAT_CAM11,
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ENABLE_ACLK_CAM10,
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ENABLE_ACLK_CAM11,
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ENABLE_ACLK_CAM12,
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