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ARC: ARCv2: jump label: implement jump label patching
Implement jump label patching for ARC. Jump labels provide an interface to generate dynamic branches using self-modifying code. This allows us to implement conditional branches where changing branch direction is expensive but branch selection is basically 'free' This implementation uses 32-bit NOP and BRANCH instructions which forced to be aligned by 4 to guarantee that they don't cross L1 cache line boundary and can be update atomically. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
This commit is contained in:
Eugeniy Paltsev
Vineet Gupta
parent
2f4ecf68a0
commit
f091d5a426
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@ -46,6 +46,7 @@ config ARC
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select OF_EARLY_FLATTREE
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select PCI_SYSCALL if PCI
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select PERF_USE_VMALLOC if ARC_CACHE_VIPT_ALIASING
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select HAVE_ARCH_JUMP_LABEL if ISA_ARCV2 && !CPU_ENDIAN_BE32
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config ARCH_HAS_CACHE_LINE_SIZE
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def_bool y
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@ -525,6 +526,13 @@ config ARC_DW2_UNWIND
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config ARC_DBG_TLB_PARANOIA
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bool "Paranoia Checks in Low Level TLB Handlers"
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config ARC_DBG_JUMP_LABEL
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bool "Paranoid checks in Static Keys (jump labels) code"
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depends on JUMP_LABEL
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default y if STATIC_KEYS_SELFTEST
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help
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Enable paranoid checks and self-test of both ARC-specific and generic
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part of static keys (jump labels) related code.
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endif
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config ARC_BUILTIN_DTB_NAME
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@ -25,6 +25,8 @@
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#ifndef __ASSEMBLY__
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#include <linux/build_bug.h>
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/* Uncached access macros */
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#define arc_read_uncached_32(ptr) \
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({ \
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72
arch/arc/include/asm/jump_label.h
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72
arch/arc/include/asm/jump_label.h
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@ -0,0 +1,72 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_ARC_JUMP_LABEL_H
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#define _ASM_ARC_JUMP_LABEL_H
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#ifndef __ASSEMBLY__
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#include <linux/stringify.h>
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#include <linux/types.h>
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#define JUMP_LABEL_NOP_SIZE 4
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/*
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* NOTE about '.balign 4':
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*
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* To make atomic update of patched instruction available we need to guarantee
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* that this instruction doesn't cross L1 cache line boundary.
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*
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* As of today we simply align instruction which can be patched by 4 byte using
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* ".balign 4" directive. In that case patched instruction is aligned with one
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* 16-bit NOP_S if this is required.
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* However 'align by 4' directive is much stricter than it actually required.
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* It's enough that our 32-bit instruction don't cross L1 cache line boundary /
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* L1 I$ fetch block boundary which can be achieved by using
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* ".bundle_align_mode" assembler directive. That will save us from adding
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* useless NOP_S padding in most of the cases.
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*
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* TODO: switch to ".bundle_align_mode" directive using whin it will be
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* supported by ARC toolchain.
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*/
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static __always_inline bool arch_static_branch(struct static_key *key,
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bool branch)
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{
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asm_volatile_goto(".balign "__stringify(JUMP_LABEL_NOP_SIZE)" \n"
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"1: \n"
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"nop \n"
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".pushsection __jump_table, \"aw\" \n"
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".word 1b, %l[l_yes], %c0 \n"
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".popsection \n"
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: : "i" (&((char *)key)[branch]) : : l_yes);
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return false;
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l_yes:
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return true;
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}
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static __always_inline bool arch_static_branch_jump(struct static_key *key,
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bool branch)
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{
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asm_volatile_goto(".balign "__stringify(JUMP_LABEL_NOP_SIZE)" \n"
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"1: \n"
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"b %l[l_yes] \n"
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".pushsection __jump_table, \"aw\" \n"
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".word 1b, %l[l_yes], %c0 \n"
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".popsection \n"
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: : "i" (&((char *)key)[branch]) : : l_yes);
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return false;
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l_yes:
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return true;
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}
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typedef u32 jump_label_t;
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struct jump_entry {
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jump_label_t code;
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jump_label_t target;
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jump_label_t key;
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};
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#endif /* __ASSEMBLY__ */
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#endif
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@ -20,6 +20,7 @@ obj-$(CONFIG_ARC_EMUL_UNALIGNED) += unaligned.o
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obj-$(CONFIG_KGDB) += kgdb.o
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obj-$(CONFIG_ARC_METAWARE_HLINK) += arc_hostlink.o
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obj-$(CONFIG_PERF_EVENTS) += perf_event.o
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obj-$(CONFIG_JUMP_LABEL) += jump_label.o
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obj-$(CONFIG_ARC_FPU_SAVE_RESTORE) += fpu.o
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CFLAGS_fpu.o += -mdpfp
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170
arch/arc/kernel/jump_label.c
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170
arch/arc/kernel/jump_label.c
Normal file
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@ -0,0 +1,170 @@
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// SPDX-License-Identifier: GPL-2.0
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#include <linux/kernel.h>
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#include <linux/jump_label.h>
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#include "asm/cacheflush.h"
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#define JUMPLABEL_ERR "ARC: jump_label: ERROR: "
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/* Halt system on fatal error to make debug easier */
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#define arc_jl_fatal(format...) \
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({ \
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pr_err(JUMPLABEL_ERR format); \
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BUG(); \
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})
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static inline u32 arc_gen_nop(void)
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{
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/* 1x 32bit NOP in middle endian */
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return 0x7000264a;
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}
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/*
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* Atomic update of patched instruction is only available if this
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* instruction doesn't cross L1 cache line boundary. You can read about
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* the way we achieve this in arc/include/asm/jump_label.h
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*/
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static inline void instruction_align_assert(void *addr, int len)
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{
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unsigned long a = (unsigned long)addr;
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if ((a >> L1_CACHE_SHIFT) != ((a + len - 1) >> L1_CACHE_SHIFT))
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arc_jl_fatal("instruction (addr %px) cross L1 cache line border",
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addr);
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}
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/*
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* ARCv2 'Branch unconditionally' instruction:
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* 00000ssssssssss1SSSSSSSSSSNRtttt
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* s S[n:0] lower bits signed immediate (number is bitfield size)
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* S S[m:n+1] upper bits signed immediate (number is bitfield size)
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* t S[24:21] upper bits signed immediate (branch unconditionally far)
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* N N <.d> delay slot mode
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* R R Reserved
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*/
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static inline u32 arc_gen_branch(jump_label_t pc, jump_label_t target)
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{
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u32 instruction_l, instruction_r;
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u32 pcl = pc & GENMASK(31, 2);
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u32 u_offset = target - pcl;
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u32 s, S, t;
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/*
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* Offset in 32-bit branch instruction must to fit into s25.
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* Something is terribly broken if we get such huge offset within one
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* function.
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*/
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if ((s32)u_offset < -16777216 || (s32)u_offset > 16777214)
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arc_jl_fatal("gen branch with offset (%d) not fit in s25",
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(s32)u_offset);
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/*
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* All instructions are aligned by 2 bytes so we should never get offset
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* here which is not 2 bytes aligned.
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*/
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if (u_offset & 0x1)
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arc_jl_fatal("gen branch with offset (%d) unaligned to 2 bytes",
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(s32)u_offset);
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s = (u_offset >> 1) & GENMASK(9, 0);
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S = (u_offset >> 11) & GENMASK(9, 0);
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t = (u_offset >> 21) & GENMASK(3, 0);
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/* 00000ssssssssss1 */
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instruction_l = (s << 1) | 0x1;
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/* SSSSSSSSSSNRtttt */
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instruction_r = (S << 6) | t;
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return (instruction_r << 16) | (instruction_l & GENMASK(15, 0));
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}
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void arch_jump_label_transform(struct jump_entry *entry,
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enum jump_label_type type)
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{
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jump_label_t *instr_addr = (jump_label_t *)entry->code;
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u32 instr;
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instruction_align_assert(instr_addr, JUMP_LABEL_NOP_SIZE);
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if (type == JUMP_LABEL_JMP)
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instr = arc_gen_branch(entry->code, entry->target);
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else
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instr = arc_gen_nop();
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WRITE_ONCE(*instr_addr, instr);
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flush_icache_range(entry->code, entry->code + JUMP_LABEL_NOP_SIZE);
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}
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void arch_jump_label_transform_static(struct jump_entry *entry,
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enum jump_label_type type)
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{
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/*
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* We use only one NOP type (1x, 4 byte) in arch_static_branch, so
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* there's no need to patch an identical NOP over the top of it here.
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* The generic code calls 'arch_jump_label_transform' if the NOP needs
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* to be replaced by a branch, so 'arch_jump_label_transform_static' is
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* never called with type other than JUMP_LABEL_NOP.
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*/
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BUG_ON(type != JUMP_LABEL_NOP);
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}
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#ifdef CONFIG_ARC_DBG_JUMP_LABEL
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#define SELFTEST_MSG "ARC: instruction generation self-test: "
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struct arc_gen_branch_testdata {
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jump_label_t pc;
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jump_label_t target_address;
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u32 expected_instr;
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};
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static __init int branch_gen_test(const struct arc_gen_branch_testdata *test)
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{
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u32 instr_got;
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instr_got = arc_gen_branch(test->pc, test->target_address);
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if (instr_got == test->expected_instr)
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return 0;
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pr_err(SELFTEST_MSG "FAIL:\n arc_gen_branch(0x%08x, 0x%08x) != 0x%08x, got 0x%08x\n",
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test->pc, test->target_address,
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test->expected_instr, instr_got);
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return -EFAULT;
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}
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/*
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* Offset field in branch instruction is not continuous. Test all
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* available offset field and sign combinations. Test data is generated
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* from real working code.
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*/
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static const struct arc_gen_branch_testdata arcgenbr_test_data[] __initconst = {
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{0x90007548, 0x90007514, 0xffcf07cd}, /* tiny (-52) offs */
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{0x9000c9c0, 0x9000c782, 0xffcf05c3}, /* tiny (-574) offs */
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{0x9000cc1c, 0x9000c782, 0xffcf0367}, /* tiny (-1178) offs */
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{0x9009dce0, 0x9009d106, 0xff8f0427}, /* small (-3034) offs */
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{0x9000f5de, 0x90007d30, 0xfc0f0755}, /* big (-30892) offs */
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{0x900a2444, 0x90035f64, 0xc9cf0321}, /* huge (-443616) offs */
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{0x90007514, 0x9000752c, 0x00000019}, /* tiny (+24) offs */
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{0x9001a578, 0x9001a77a, 0x00000203}, /* tiny (+514) offs */
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{0x90031ed8, 0x90032634, 0x0000075d}, /* tiny (+1884) offs */
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{0x9008c7f2, 0x9008d3f0, 0x00400401}, /* small (+3072) offs */
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{0x9000bb38, 0x9003b340, 0x17c00009}, /* big (+194568) offs */
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{0x90008f44, 0x90578d80, 0xb7c2063d} /* huge (+5701180) offs */
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};
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static __init int instr_gen_test(void)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(arcgenbr_test_data); i++)
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if (branch_gen_test(&arcgenbr_test_data[i]))
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return -EFAULT;
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pr_info(SELFTEST_MSG "OK\n");
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return 0;
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}
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early_initcall(instr_gen_test);
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#endif /* CONFIG_ARC_DBG_JUMP_LABEL */
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