Minki/linux
1
0
Fork 1
mirror of https://github.com/torvalds/linux.git synced 2024-12-27 05:11:48 +00:00
Code Issues Packages Projects Releases Wiki Activity

crypto: hisilicon - add sgl_sge_nr module param for zip

Browse Source 
Add a module parameter for zip driver to set the number of SGE in one SGL.

Signed-off-by: Shukun Tan <tanshukun1@huawei.com>
Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
Shukun Tan 2019-09-30 15:08:53 +08:00 committed by Herbert Xu
parent 48c1cd40fa
commit f081fda293
3 changed files with 28 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/crypto/hisilicon/qm.h
View File

@ -75,6 +75,8 @@
#define QM_Q_DEPTH 1024
#define HISI_ACC_SGL_SGE_NR_MAX 255
enum qp_state {
QP_STOP,
};

2
drivers/crypto/hisilicon/sgl.c
View File

@ -3,9 +3,9 @@
#include <linux/dma-mapping.h>
#include <linux/module.h>
#include <linux/slab.h>
#include "qm.h"
#define HISI_ACC_SGL_SGE_NR_MIN 1
#define HISI_ACC_SGL_SGE_NR_MAX 255
#define HISI_ACC_SGL_NR_MAX 256
#define HISI_ACC_SGL_ALIGN_SIZE 64

26
drivers/crypto/hisilicon/zip/zip_crypto.c
View File

@ -79,6 +79,30 @@ struct hisi_zip_ctx {
struct hisi_zip_qp_ctx qp_ctx[HZIP_CTX_Q_NUM];
};
static int sgl_sge_nr_set(const char *val, const struct kernel_param *kp)
{
int ret;
u16 n;
if (!val)
return -EINVAL;
ret = kstrtou16(val, 10, &n);
if (ret || n == 0 || n > HISI_ACC_SGL_SGE_NR_MAX)
return -EINVAL;
return param_set_int(val, kp);
}
static const struct kernel_param_ops sgl_sge_nr_ops = {
.set = sgl_sge_nr_set,
.get = param_get_int,
};
static u16 sgl_sge_nr = HZIP_SGL_SGE_NR;
module_param_cb(sgl_sge_nr, &sgl_sge_nr_ops, &sgl_sge_nr, 0444);
MODULE_PARM_DESC(sgl_sge_nr, "Number of sge in sgl(1-255)");
static void hisi_zip_config_buf_type(struct hisi_zip_sqe *sqe, u8 buf_type)
{
u32 val;
@ -273,7 +297,7 @@ static int hisi_zip_create_sgl_pool(struct hisi_zip_ctx *ctx)
tmp = &ctx->qp_ctx[i];
dev = &tmp->qp->qm->pdev->dev;
tmp->sgl_pool = hisi_acc_create_sgl_pool(dev, QM_Q_DEPTH << 1,
HZIP_SGL_SGE_NR);
sgl_sge_nr);
if (IS_ERR(tmp->sgl_pool)) {
if (i == 1)
goto err_free_sgl_pool0;