Minki/linux
1
0
Fork 1
mirror of https://github.com/torvalds/linux.git synced 2024-11-15 00:21:59 +00:00
Code Issues Packages Projects Releases Wiki Activity

phy: qcom-qmp-pcie: consolidate lane config

Browse Source 
For legacy reasons, there are two configuration parameters that describe
the number of lanes a PHY has.

Replace them both with a new field simply named "lanes".

Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20220920073826.20811-13-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Johan Hovold 2022-09-20 09:38:21 +02:00 committed by Vinod Koul
parent b4e9da4d96
commit f02543fa5b
1 changed files with 16 additions and 23 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

39
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
View File

@ -1302,8 +1302,7 @@ static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = {
/* struct qmp_phy_cfg - per-PHY initialization config */
struct qmp_phy_cfg {
/* number of lanes provided by phy */
int nlanes;
int lanes;
/* Init sequence for PHY blocks - serdes, tx, rx, pcs */
const struct qmp_phy_init_tbl *serdes_tbl;
@ -1351,9 +1350,6 @@ struct qmp_phy_cfg {
int pwrdn_delay_min;
int pwrdn_delay_max;
/* true, if PHY has secondary tx/rx lanes to be configured */
bool is_dual_lane_phy;
/* QMP PHY pipe clock interface rate */
unsigned long pipe_clock_rate;
};
@ -1461,7 +1457,7 @@ static const char * const sdm845_pciephy_reset_l[] = {
};
static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
.nlanes = 1,
.lanes = 1,
.serdes_tbl = ipq8074_pcie_serdes_tbl,
.serdes_tbl_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl),
@ -1489,7 +1485,7 @@ static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
};
static const struct qmp_phy_cfg ipq8074_pciephy_gen3_cfg = {
.nlanes = 1,
.lanes = 1,
.serdes_tbl = ipq8074_pcie_gen3_serdes_tbl,
.serdes_tbl_num = ARRAY_SIZE(ipq8074_pcie_gen3_serdes_tbl),
@ -1518,7 +1514,7 @@ static const struct qmp_phy_cfg ipq8074_pciephy_gen3_cfg = {
};
static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
.nlanes = 1,
.lanes = 1,
.serdes_tbl = ipq6018_pcie_serdes_tbl,
.serdes_tbl_num = ARRAY_SIZE(ipq6018_pcie_serdes_tbl),
@ -1547,7 +1543,7 @@ static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
};
static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
.nlanes = 1,
.lanes = 1,
.serdes_tbl = sdm845_qmp_pcie_serdes_tbl,
.serdes_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl),
@ -1577,7 +1573,7 @@ static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
};
static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {
.nlanes = 1,
.lanes = 1,
.serdes_tbl = sdm845_qhp_pcie_serdes_tbl,
.serdes_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl),
@ -1605,7 +1601,7 @@ static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {
};
static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {
.nlanes = 1,
.lanes = 1,
.serdes_tbl = sm8250_qmp_pcie_serdes_tbl,
.serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
@ -1643,7 +1639,7 @@ static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {
};
static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = {
.nlanes = 2,
.lanes = 2,
.serdes_tbl = sm8250_qmp_pcie_serdes_tbl,
.serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
@ -1675,14 +1671,13 @@ static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = {
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
.phy_status = PHYSTATUS,
.is_dual_lane_phy = true,
.has_pwrdn_delay = true,
.pwrdn_delay_min = 995, /* us */
.pwrdn_delay_max = 1005, /* us */
};
static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
.nlanes = 1,
.lanes = 1,
.serdes_tbl = msm8998_pcie_serdes_tbl,
.serdes_tbl_num = ARRAY_SIZE(msm8998_pcie_serdes_tbl),
@ -1706,7 +1701,7 @@ static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
};
static const struct qmp_phy_cfg sc8180x_pciephy_cfg = {
.nlanes = 1,
.lanes = 1,
.serdes_tbl = sc8180x_qmp_pcie_serdes_tbl,
.serdes_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl),
@ -1735,7 +1730,7 @@ static const struct qmp_phy_cfg sc8180x_pciephy_cfg = {
};
static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = {
.nlanes = 2,
.lanes = 2,
.serdes_tbl = sdx55_qmp_pcie_serdes_tbl,
.serdes_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl),
@ -1759,14 +1754,13 @@ static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = {
.pwrdn_ctrl = SW_PWRDN,
.phy_status = PHYSTATUS_4_20,
.is_dual_lane_phy = true,
.has_pwrdn_delay = true,
.pwrdn_delay_min = 995, /* us */
.pwrdn_delay_max = 1005, /* us */
};
static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = {
.nlanes = 1,
.lanes = 1,
.serdes_tbl = sm8450_qmp_gen3x1_pcie_serdes_tbl,
.serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_serdes_tbl),
@ -1796,7 +1790,7 @@ static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = {
};
static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = {
.nlanes = 2,
.lanes = 2,
.serdes_tbl = sm8450_qmp_gen4x2_pcie_serdes_tbl,
.serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl),
@ -1820,7 +1814,6 @@ static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = {
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
.phy_status = PHYSTATUS_4_20,
.is_dual_lane_phy = true,
.has_pwrdn_delay = true,
.pwrdn_delay_min = 995, /* us */
.pwrdn_delay_max = 1005, /* us */
@ -1959,7 +1952,7 @@ static int qmp_pcie_power_on(struct phy *phy)
qmp_pcie_configure_lane(tx, cfg->regs, cfg->tx_tbl, cfg->tx_tbl_num, 1);
qmp_pcie_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec, cfg->tx_tbl_num_sec, 1);
if (cfg->is_dual_lane_phy) {
if (cfg->lanes >= 2) {
qmp_pcie_configure_lane(qphy->tx2, cfg->regs, cfg->tx_tbl,
cfg->tx_tbl_num, 2);
qmp_pcie_configure_lane(qphy->tx2, cfg->regs, cfg->tx_tbl_sec,
@ -1969,7 +1962,7 @@ static int qmp_pcie_power_on(struct phy *phy)
qmp_pcie_configure_lane(rx, cfg->regs, cfg->rx_tbl, cfg->rx_tbl_num, 1);
qmp_pcie_configure_lane(rx, cfg->regs, cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1);
if (cfg->is_dual_lane_phy) {
if (cfg->lanes >= 2) {
qmp_pcie_configure_lane(qphy->rx2, cfg->regs, cfg->rx_tbl,
cfg->rx_tbl_num, 2);
qmp_pcie_configure_lane(qphy->rx2, cfg->regs, cfg->rx_tbl_sec,
@ -2225,7 +2218,7 @@ static int qmp_pcie_create(struct device *dev, struct device_node *np, int id,
if (IS_ERR(qphy->pcs))
return PTR_ERR(qphy->pcs);
if (cfg->is_dual_lane_phy) {
if (cfg->lanes >= 2) {
qphy->tx2 = devm_of_iomap(dev, np, 3, NULL);
if (IS_ERR(qphy->tx2))
return PTR_ERR(qphy->tx2);