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Merge branch 'thunderbolt/fixes' into thunderbolt/next
We need Thunderbolt/USB4 fixes here as well. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
This commit is contained in:
commit
ef65afa074
@ -192,9 +192,9 @@ static int dma_test_start_rings(struct dma_test *dt)
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}
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ret = tb_xdomain_enable_paths(dt->xd, dt->tx_hopid,
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dt->tx_ring ? dt->tx_ring->hop : 0,
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dt->tx_ring ? dt->tx_ring->hop : -1,
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dt->rx_hopid,
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dt->rx_ring ? dt->rx_ring->hop : 0);
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dt->rx_ring ? dt->rx_ring->hop : -1);
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if (ret) {
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dma_test_free_rings(dt);
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return ret;
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@ -218,9 +218,9 @@ static void dma_test_stop_rings(struct dma_test *dt)
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tb_ring_stop(dt->tx_ring);
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ret = tb_xdomain_disable_paths(dt->xd, dt->tx_hopid,
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dt->tx_ring ? dt->tx_ring->hop : 0,
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dt->tx_ring ? dt->tx_ring->hop : -1,
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dt->rx_hopid,
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dt->rx_ring ? dt->rx_ring->hop : 0);
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dt->rx_ring ? dt->rx_ring->hop : -1);
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if (ret)
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dev_warn(&dt->svc->dev, "failed to disable DMA paths\n");
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@ -56,9 +56,14 @@ static int ring_interrupt_index(const struct tb_ring *ring)
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static void nhi_mask_interrupt(struct tb_nhi *nhi, int mask, int ring)
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{
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if (nhi->quirks & QUIRK_AUTO_CLEAR_INT)
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return;
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if (nhi->quirks & QUIRK_AUTO_CLEAR_INT) {
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u32 val;
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val = ioread32(nhi->iobase + REG_RING_INTERRUPT_BASE + ring);
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iowrite32(val & ~mask, nhi->iobase + REG_RING_INTERRUPT_BASE + ring);
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} else {
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iowrite32(mask, nhi->iobase + REG_RING_INTERRUPT_MASK_CLEAR_BASE + ring);
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}
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}
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static void nhi_clear_interrupt(struct tb_nhi *nhi, int ring)
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@ -737,6 +737,7 @@ static void tb_scan_port(struct tb_port *port)
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{
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struct tb_cm *tcm = tb_priv(port->sw->tb);
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struct tb_port *upstream_port;
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bool discovery = false;
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struct tb_switch *sw;
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int ret;
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@ -804,8 +805,10 @@ static void tb_scan_port(struct tb_port *port)
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* tunnels and know which switches were authorized already by
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* the boot firmware.
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*/
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if (!tcm->hotplug_active)
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if (!tcm->hotplug_active) {
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dev_set_uevent_suppress(&sw->dev, true);
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discovery = true;
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}
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/*
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* At the moment Thunderbolt 2 and beyond (devices with LC) we
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@ -835,10 +838,14 @@ static void tb_scan_port(struct tb_port *port)
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* CL0s and CL1 are enabled and supported together.
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* Silently ignore CLx enabling in case CLx is not supported.
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*/
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if (discovery) {
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tb_sw_dbg(sw, "discovery, not touching CL states\n");
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} else {
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ret = tb_switch_enable_clx(sw, TB_CL1);
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if (ret && ret != -EOPNOTSUPP)
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tb_sw_warn(sw, "failed to enable %s on upstream port\n",
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tb_switch_clx_name(TB_CL1));
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}
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if (tb_switch_is_clx_enabled(sw, TB_CL1))
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/*
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@ -531,7 +531,7 @@ static int tb_dp_xchg_caps(struct tb_tunnel *tunnel)
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* Perform connection manager handshake between IN and OUT ports
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* before capabilities exchange can take place.
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*/
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ret = tb_dp_cm_handshake(in, out, 1500);
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ret = tb_dp_cm_handshake(in, out, 3000);
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if (ret)
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return ret;
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