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mtd: rawnand: gpmi: Implement exec_op

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The gpmi driver performance suffers from NAND operations being split
in multiple small DMA transfers. This has been forced by the NAND layer
in the former days, but now with exec_op we can use the controller as
intended.

With this patch gpmi_nfc_exec_op becomes the main entry point to NAND
operations. Here all instructions are collected and chained as separate
DMA transfers. In the end whole chain is fired and waited to be
finished. gpmi_nfc_exec_op only does the hardware operations, bad block
marker swapping and buffer scrambling is done by the callers. It's worth
noting that the nand_*_op functions always take the buffer lengths for
the data that the NAND chip actually transfers. When doing BCH we have
to calculate the net data size from the raw data size in some places.

This patch has been tested with 2048/64 and 2048/128 byte NAND on
i.MX6q. mtd_oobtest, mtd_subpagetest and mtd_speedtest run without
errors. nandbiterrs, nandpagetest and nandsubpagetest userspace tests
from mtdutils run without errors and UBIFS can successfully be mounted.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
This commit is contained in:
Sascha Hauer 2019-05-21 09:06:43 +02:00 committed by Miquel Raynal
parent ceeeb99cd8
commit ef347c0cfd
4 changed files with 444 additions and 690 deletions
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3
drivers/dma/mxs-dma.c
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@ -78,6 +78,7 @@
#define BM_CCW_COMMAND (3 << 0) #define BM_CCW_COMMAND (3 << 0)
#define CCW_CHAIN (1 << 2) #define CCW_CHAIN (1 << 2)
#define CCW_IRQ (1 << 3) #define CCW_IRQ (1 << 3)
#define CCW_WAIT4RDY (1 << 5)
#define CCW_DEC_SEM (1 << 6) #define CCW_DEC_SEM (1 << 6)
#define CCW_WAIT4END (1 << 7) #define CCW_WAIT4END (1 << 7)
#define CCW_HALT_ON_TERM (1 << 8) #define CCW_HALT_ON_TERM (1 << 8)
@ -547,6 +548,8 @@ static struct dma_async_tx_descriptor *mxs_dma_prep_slave_sg(
ccw->bits |= CCW_TERM_FLUSH; ccw->bits |= CCW_TERM_FLUSH;
ccw->bits |= BF_CCW(sg_len, PIO_NUM); ccw->bits |= BF_CCW(sg_len, PIO_NUM);
ccw->bits |= BF_CCW(MXS_DMA_CMD_NO_XFER, COMMAND); ccw->bits |= BF_CCW(MXS_DMA_CMD_NO_XFER, COMMAND);
if (flags & MXS_DMA_CTRL_WAIT4RDY)
ccw->bits |= CCW_WAIT4RDY;
} else { } else {
for_each_sg(sgl, sg, sg_len, i) { for_each_sg(sgl, sg, sg_len, i) {
if (sg_dma_len(sg) > MAX_XFER_BYTES) { if (sg_dma_len(sg) > MAX_XFER_BYTES) {

1105
drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c
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File diff suppressed because it is too large Load Diff

25
drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.h
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@ -103,6 +103,14 @@ struct gpmi_nfc_hardware_timing {
u32 ctrl1n; u32 ctrl1n;
}; };
#define GPMI_MAX_TRANSFERS 8
struct gpmi_transfer {
u8 cmdbuf[8];
struct scatterlist sgl;
enum dma_data_direction direction;
};
struct gpmi_nand_data { struct gpmi_nand_data {
/* Devdata */ /* Devdata */
const struct gpmi_devdata *devdata; const struct gpmi_devdata *devdata;
@ -126,23 +134,18 @@ struct gpmi_nand_data {
struct boot_rom_geometry rom_geometry; struct boot_rom_geometry rom_geometry;
/* MTD / NAND */ /* MTD / NAND */
struct nand_controller base;
struct nand_chip nand; struct nand_chip nand;
/* General-use Variables */ struct gpmi_transfer transfers[GPMI_MAX_TRANSFERS];
int current_chip; int ntransfers;
unsigned int command_length;
struct scatterlist cmd_sgl; bool bch;
char *cmd_buffer; uint32_t bch_flashlayout0;
uint32_t bch_flashlayout1;
struct scatterlist data_sgl;
char *data_buffer_dma; char *data_buffer_dma;
unsigned int page_buffer_size;
void *payload_virt;
dma_addr_t payload_phys;
void *auxiliary_virt; void *auxiliary_virt;
dma_addr_t auxiliary_phys; dma_addr_t auxiliary_phys;

1
include/linux/dma/mxs-dma.h
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@ -5,6 +5,7 @@
#include <linux/dmaengine.h> #include <linux/dmaengine.h>
#define MXS_DMA_CTRL_WAIT4END BIT(31) #define MXS_DMA_CTRL_WAIT4END BIT(31)
#define MXS_DMA_CTRL_WAIT4RDY BIT(30)
/* /*
* The mxs dmaengine can do PIO transfers. We pass a pointer to the PIO words * The mxs dmaengine can do PIO transfers. We pass a pointer to the PIO words