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Merge branch 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip
* 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: x86, cacheinfo: Turn off L3 cache index disable feature in virtualized environments x86, k8: Fix build error when K8_NB is disabled x86, amd: Check X86_FEATURE_OSVW bit before accessing OSVW MSRs x86: Fix fake apicid to node mapping for numa emulation
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ef0e9180d3
@ -16,11 +16,16 @@ extern int k8_numa_init(unsigned long start_pfn, unsigned long end_pfn);
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extern int k8_scan_nodes(void);
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#ifdef CONFIG_K8_NB
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extern int num_k8_northbridges;
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static inline struct pci_dev *node_to_k8_nb_misc(int node)
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{
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return (node < num_k8_northbridges) ? k8_northbridges[node] : NULL;
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}
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#else
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#define num_k8_northbridges 0
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static inline struct pci_dev *node_to_k8_nb_misc(int node)
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{
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return NULL;
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@ -340,6 +340,10 @@ amd_check_l3_disable(int index, struct _cpuid4_info_regs *this_leaf)
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(boot_cpu_data.x86_mask < 0x1)))
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return;
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/* not in virtualized environments */
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if (num_k8_northbridges == 0)
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return;
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this_leaf->can_disable = true;
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this_leaf->l3_indices = amd_calc_l3_indices();
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}
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@ -546,11 +546,13 @@ static int __cpuinit check_c1e_idle(const struct cpuinfo_x86 *c)
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* check OSVW bit for CPUs that are not affected
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* by erratum #400
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*/
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rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, val);
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if (val >= 2) {
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rdmsrl(MSR_AMD64_OSVW_STATUS, val);
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if (!(val & BIT(1)))
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goto no_c1e_idle;
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if (cpu_has(c, X86_FEATURE_OSVW)) {
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rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, val);
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if (val >= 2) {
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rdmsrl(MSR_AMD64_OSVW_STATUS, val);
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if (!(val & BIT(1)))
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goto no_c1e_idle;
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}
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}
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return 1;
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}
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@ -461,7 +461,8 @@ void __init acpi_fake_nodes(const struct bootnode *fake_nodes, int num_nodes)
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* node, it must now point to the fake node ID.
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*/
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for (j = 0; j < MAX_LOCAL_APIC; j++)
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if (apicid_to_node[j] == nid)
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if (apicid_to_node[j] == nid &&
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fake_apicid_to_node[j] == NUMA_NO_NODE)
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fake_apicid_to_node[j] = i;
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}
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for (i = 0; i < num_nodes; i++)
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