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staging: ccree: remove custom bitfield macros

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With all users removed or re-factored to use the standard
kernel bit fields ops we can now drop the custom
bit field macros.

Signed-off-by: Gilad Ben-Yossef <gilad@benyossef.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Gilad Ben-Yossef 2017-06-04 11:02:30 +03:00 committed by Greg Kroah-Hartman
parent 37a99c9831
commit ed7443911e
5 changed files with 7 additions and 108 deletions
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39
drivers/staging/ccree/cc_bitops.h
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@ -1,39 +0,0 @@
/*
* Copyright (C) 2012-2017 ARM Limited or its affiliates.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, see <http://www.gnu.org/licenses/>.
*/
/*!
* \file cc_bitops.h
* Bit fields operations macros.
*/
#ifndef _CC_BITOPS_H_
#define _CC_BITOPS_H_
#include <linux/bitops.h>
#include <linux/bitfield.h>
#define BITMASK(mask_size) (((mask_size) < 32) ? \
((1UL << (mask_size)) - 1) : 0xFFFFFFFFUL)
#define BITMASK_AT(mask_size, mask_offset) (BITMASK(mask_size) << (mask_offset))
#define BITFIELD_GET(word, bit_offset, bit_size) \
(((word) >> (bit_offset)) & BITMASK(bit_size))
#define BITFIELD_SET(word, bit_offset, bit_size, new_val) do { \
word = ((word) & ~BITMASK_AT(bit_size, bit_offset)) | \
(((new_val) & BITMASK(bit_size)) << (bit_offset)); \
} while (0)
#endif /*_CC_BITOPS_H_*/

2
drivers/staging/ccree/cc_hw_queue_defs.h
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@ -19,8 +19,8 @@
#include <linux/types.h>
#include "cc_regs.h"
#include "dx_crys_kernel.h"
#include <linux/bitfield.h>
/******************************************************************************
* DEFINITIONS

2
drivers/staging/ccree/cc_lli_defs.h
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@ -19,8 +19,6 @@
#include <linux/types.h>
#include "cc_bitops.h"
/* Max DLLI size
* AKA DX_DSCRPTR_QUEUE_WORD1_DIN_SIZE_BIT_SIZE
*/

71
drivers/staging/ccree/cc_regs.h
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@ -24,7 +24,12 @@
#ifndef _CC_REGS_H_
#define _CC_REGS_H_
#include "cc_bitops.h"
#include <linux/bitfield.h>
#define AXIM_MON_BASE_OFFSET CC_REG_OFFSET(CRY_KERNEL, AXIM_MON_COMP)
#define AXIM_MON_COMP_VALUE GENMASK(DX_AXIM_MON_COMP_VALUE_BIT_SIZE + \
DX_AXIM_MON_COMP_VALUE_BIT_SHIFT, \
DX_AXIM_MON_COMP_VALUE_BIT_SHIFT)
#define AXIM_MON_BASE_OFFSET CC_REG_OFFSET(CRY_KERNEL, AXIM_MON_COMP)
#define AXIM_MON_COMP_VALUE GENMASK(DX_AXIM_MON_COMP_VALUE_BIT_SIZE + \
@ -35,68 +40,4 @@
#define CC_REG_OFFSET(unit_name, reg_name) \
(DX_BASE_ ## unit_name + DX_ ## reg_name ## _REG_OFFSET)
#define CC_REG_BIT_SHIFT(reg_name, field_name) \
(DX_ ## reg_name ## _ ## field_name ## _BIT_SHIFT)
/* Read-Modify-Write a field of a register */
#define MODIFY_REGISTER_FLD(unitName, regName, fldName, fldVal) \
do { \
u32 regVal; \
regVal = READ_REGISTER(CC_REG_ADDR(unitName, regName)); \
CC_REG_FLD_SET(unitName, regName, fldName, regVal, fldVal); \
WRITE_REGISTER(CC_REG_ADDR(unitName, regName), regVal); \
} while (0)
/*! Bit fields get */
#define CC_REG_FLD_GET(unit_name, reg_name, fld_name, reg_val) \
(DX_ ## reg_name ## _ ## fld_name ## _BIT_SIZE == 0x20 ? \
reg_val /*!< \internal Optimization for 32b fields */ : \
BITFIELD_GET(reg_val, DX_ ## reg_name ## _ ## fld_name ## _BIT_SHIFT, \
DX_ ## reg_name ## _ ## fld_name ## _BIT_SIZE))
/*! Bit fields access */
#define CC_REG_FLD_GET2(unit_name, reg_name, fld_name, reg_val) \
(CC_ ## reg_name ## _ ## fld_name ## _BIT_SIZE == 0x20 ? \
reg_val /*!< \internal Optimization for 32b fields */ : \
BITFIELD_GET(reg_val, CC_ ## reg_name ## _ ## fld_name ## _BIT_SHIFT, \
CC_ ## reg_name ## _ ## fld_name ## _BIT_SIZE))
/* yael TBD !!!
* all HW includes should start with CC_ and not DX_ !!
*/
/*! Bit fields set */
#define CC_REG_FLD_SET( \
unit_name, reg_name, fld_name, reg_shadow_var, new_fld_val) \
do { \
if (DX_ ## reg_name ## _ ## fld_name ## _BIT_SIZE == 0x20) \
reg_shadow_var = new_fld_val; /*!< \internal Optimization for 32b fields */\
else \
BITFIELD_SET(reg_shadow_var, \
DX_ ## reg_name ## _ ## fld_name ## _BIT_SHIFT, \
DX_ ## reg_name ## _ ## fld_name ## _BIT_SIZE, \
new_fld_val); \
} while (0)
/*! Bit fields set */
#define CC_REG_FLD_SET2( \
unit_name, reg_name, fld_name, reg_shadow_var, new_fld_val) \
do { \
if (CC_ ## reg_name ## _ ## fld_name ## _BIT_SIZE == 0x20) \
reg_shadow_var = new_fld_val; /*!< \internal Optimization for 32b fields */\
else \
BITFIELD_SET(reg_shadow_var, \
CC_ ## reg_name ## _ ## fld_name ## _BIT_SHIFT, \
CC_ ## reg_name ## _ ## fld_name ## _BIT_SIZE, \
new_fld_val); \
} while (0)
/* Usage example:
* u32 reg_shadow = READ_REGISTER(CC_REG_ADDR(CRY_KERNEL,AES_CONTROL));
* CC_REG_FLD_SET(CRY_KERNEL,AES_CONTROL,NK_KEY0,reg_shadow, 3);
* CC_REG_FLD_SET(CRY_KERNEL,AES_CONTROL,NK_KEY1,reg_shadow, 1);
* WRITE_REGISTER(CC_REG_ADDR(CRY_KERNEL,AES_CONTROL), reg_shadow);
*/
#endif /*_CC_REGS_H_*/

1
drivers/staging/ccree/ssi_driver.h
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@ -40,7 +40,6 @@
/* Registers definitions from shared/hw/ree_include */
#include "dx_reg_base_host.h"
#include "dx_host.h"
#define DX_CC_HOST_VIRT /* must be defined before including dx_cc_regs.h */
#include "cc_regs.h"
#include "dx_reg_common.h"
#include "cc_hal.h"