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arm64: entry: convert el1_sync to C
This patch converts the EL1 sync entry assembly logic to C code. Doing this will allow us to make changes in a slightly more readable way. A case in point is supporting kernel-first RAS. do_sea() should be called on the CPU that took the fault. Largely the assembly code is converted to C in a relatively straightforward manner. Since all sync sites share a common asm entry point, the ASM_BUG() instances are no longer required for effective backtraces back to assembly, and we don't need similar BUG() entries. The ESR_ELx.EC codes for all (supported) debug exceptions are now checked in the el1_sync_handler's switch statement, which renders the check in el1_dbg redundant. This both simplifies the el1_dbg handler, and makes the EL1 exception handling more robust to currently-unallocated ESR_ELx.EC encodings. Signed-off-by: Mark Rutland <mark.rutland@arm.com> [split out of a bigger series, added nokprobes, moved prototypes] Signed-off-by: James Morse <james.morse@arm.com> Reviewed-by: Mark Rutland <mark.rutland@arm.com> Cc: Julien Thierry <julien.thierry.kdev@gmail.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
This commit is contained in:
Mark Rutland
Catalin Marinas
parent
51077e03b8
commit
ed3768db58
@ -13,9 +13,9 @@ CFLAGS_REMOVE_return_address.o = $(CC_FLAGS_FTRACE)
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# Object file lists.
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obj-y := debug-monitors.o entry.o irq.o fpsimd.o \
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entry-fpsimd.o process.o ptrace.o setup.o signal.o \
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sys.o stacktrace.o time.o traps.o io.o vdso.o \
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hyp-stub.o psci.o cpu_ops.o insn.o \
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entry-common.o entry-fpsimd.o process.o ptrace.o \
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setup.o signal.o sys.o stacktrace.o time.o traps.o \
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io.o vdso.o hyp-stub.o psci.o cpu_ops.o insn.o \
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return_address.o cpuinfo.o cpu_errata.o \
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cpufeature.o alternative.o cacheinfo.o \
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smp.o smp_spin_table.o topology.o smccc-call.o \
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98
arch/arm64/kernel/entry-common.c
Normal file
98
arch/arm64/kernel/entry-common.c
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@ -0,0 +1,98 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Exception handling code
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*
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* Copyright (C) 2019 ARM Ltd.
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*/
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#include <linux/context_tracking.h>
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#include <linux/ptrace.h>
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#include <linux/thread_info.h>
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#include <asm/cpufeature.h>
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#include <asm/daifflags.h>
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#include <asm/esr.h>
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#include <asm/exception.h>
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#include <asm/kprobes.h>
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#include <asm/sysreg.h>
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static void notrace el1_abort(struct pt_regs *regs, unsigned long esr)
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{
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unsigned long far = read_sysreg(far_el1);
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local_daif_inherit(regs);
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far = untagged_addr(far);
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do_mem_abort(far, esr, regs);
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}
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NOKPROBE_SYMBOL(el1_abort);
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static void notrace el1_pc(struct pt_regs *regs, unsigned long esr)
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{
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unsigned long far = read_sysreg(far_el1);
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local_daif_inherit(regs);
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do_sp_pc_abort(far, esr, regs);
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}
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NOKPROBE_SYMBOL(el1_pc);
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static void el1_undef(struct pt_regs *regs)
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{
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local_daif_inherit(regs);
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do_undefinstr(regs);
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}
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NOKPROBE_SYMBOL(el1_undef);
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static void el1_inv(struct pt_regs *regs, unsigned long esr)
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{
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local_daif_inherit(regs);
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bad_mode(regs, 0, esr);
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}
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NOKPROBE_SYMBOL(el1_inv);
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static void notrace el1_dbg(struct pt_regs *regs, unsigned long esr)
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{
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unsigned long far = read_sysreg(far_el1);
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/*
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* The CPU masked interrupts, and we are leaving them masked during
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* do_debug_exception(). Update PMR as if we had called
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* local_mask_daif().
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*/
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if (system_uses_irq_prio_masking())
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gic_write_pmr(GIC_PRIO_IRQON | GIC_PRIO_PSR_I_SET);
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do_debug_exception(far, esr, regs);
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}
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NOKPROBE_SYMBOL(el1_dbg);
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asmlinkage void notrace el1_sync_handler(struct pt_regs *regs)
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{
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unsigned long esr = read_sysreg(esr_el1);
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switch (ESR_ELx_EC(esr)) {
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case ESR_ELx_EC_DABT_CUR:
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case ESR_ELx_EC_IABT_CUR:
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el1_abort(regs, esr);
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break;
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/*
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* We don't handle ESR_ELx_EC_SP_ALIGN, since we will have hit a
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* recursive exception when trying to push the initial pt_regs.
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*/
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case ESR_ELx_EC_PC_ALIGN:
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el1_pc(regs, esr);
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break;
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case ESR_ELx_EC_SYS64:
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case ESR_ELx_EC_UNKNOWN:
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el1_undef(regs);
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break;
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case ESR_ELx_EC_BREAKPT_CUR:
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case ESR_ELx_EC_SOFTSTP_CUR:
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case ESR_ELx_EC_WATCHPT_CUR:
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case ESR_ELx_EC_BRK64:
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el1_dbg(regs, esr);
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break;
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default:
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el1_inv(regs, esr);
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};
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}
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NOKPROBE_SYMBOL(el1_sync_handler);
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@ -578,76 +578,9 @@ ENDPROC(el1_error_invalid)
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.align 6
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el1_sync:
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kernel_entry 1
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mrs x1, esr_el1 // read the syndrome register
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lsr x24, x1, #ESR_ELx_EC_SHIFT // exception class
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cmp x24, #ESR_ELx_EC_DABT_CUR // data abort in EL1
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b.eq el1_da
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cmp x24, #ESR_ELx_EC_IABT_CUR // instruction abort in EL1
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b.eq el1_ia
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cmp x24, #ESR_ELx_EC_SYS64 // configurable trap
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b.eq el1_undef
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cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception
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b.eq el1_pc
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cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL1
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b.eq el1_undef
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cmp x24, #ESR_ELx_EC_BREAKPT_CUR // debug exception in EL1
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b.ge el1_dbg
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b el1_inv
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el1_ia:
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/*
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* Fall through to the Data abort case
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*/
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el1_da:
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/*
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* Data abort handling
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*/
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mrs x3, far_el1
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inherit_daif pstate=x23, tmp=x2
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clear_address_tag x0, x3
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mov x2, sp // struct pt_regs
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bl do_mem_abort
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kernel_exit 1
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el1_pc:
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/*
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* PC alignment exception handling. We don't handle SP alignment faults,
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* since we will have hit a recursive exception when trying to push the
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* initial pt_regs.
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*/
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mrs x0, far_el1
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inherit_daif pstate=x23, tmp=x2
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mov x2, sp
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bl do_sp_pc_abort
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ASM_BUG()
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el1_undef:
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/*
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* Undefined instruction
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*/
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inherit_daif pstate=x23, tmp=x2
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mov x0, sp
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bl do_undefinstr
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bl el1_sync_handler
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kernel_exit 1
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el1_dbg:
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/*
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* Debug exception handling
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*/
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cmp x24, #ESR_ELx_EC_BRK64 // if BRK64
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cinc x24, x24, eq // set bit '0'
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tbz x24, #0, el1_inv // EL1 only
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gic_prio_kentry_setup tmp=x3
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mrs x0, far_el1
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mov x2, sp // struct pt_regs
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bl do_debug_exception
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kernel_exit 1
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el1_inv:
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// TODO: add support for undefined instructions in kernel mode
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inherit_daif pstate=x23, tmp=x2
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mov x0, sp
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mov x2, x1
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mov x1, #BAD_SYNC
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bl bad_mode
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ASM_BUG()
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ENDPROC(el1_sync)
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.align 6
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