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ARM: S5P64X0: Add HSMMC setup for host Controller
Adds support for HSMMC for S5P64X0 platform, performs setup for host controller and related GPIO. Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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ebc433c289
@ -41,6 +41,11 @@ config S5P64X0_SETUP_SPI
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help
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Common setup code for SPI GPIO configurations
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config S5P64X0_SETUP_SDHCI_GPIO
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bool
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help
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Common setup code for SDHCI gpio.
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# machine support
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config MACH_SMDK6440
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@ -50,12 +55,16 @@ config MACH_SMDK6440
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select S3C_DEV_I2C1
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select S3C_DEV_RTC
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select S3C_DEV_WDT
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select S3C_DEV_HSMMC
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select S3C_DEV_HSMMC1
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select S3C_DEV_HSMMC2
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select SAMSUNG_DEV_ADC
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select SAMSUNG_DEV_BACKLIGHT
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select SAMSUNG_DEV_PWM
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select SAMSUNG_DEV_TS
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select S5P64X0_SETUP_FB_24BPP
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select S5P64X0_SETUP_I2C1
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select S5P64X0_SETUP_SDHCI_GPIO
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help
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Machine support for the Samsung SMDK6440
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@ -66,13 +75,28 @@ config MACH_SMDK6450
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select S3C_DEV_I2C1
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select S3C_DEV_RTC
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select S3C_DEV_WDT
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select S3C_DEV_HSMMC
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select S3C_DEV_HSMMC1
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select S3C_DEV_HSMMC2
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select SAMSUNG_DEV_ADC
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select SAMSUNG_DEV_BACKLIGHT
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select SAMSUNG_DEV_PWM
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select SAMSUNG_DEV_TS
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select S5P64X0_SETUP_FB_24BPP
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select S5P64X0_SETUP_I2C1
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select S5P64X0_SETUP_SDHCI_GPIO
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help
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Machine support for the Samsung SMDK6450
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menu "Use 8-bit SDHCI bus width"
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config S5P64X0_SD_CH1_8BIT
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bool "SDHCI Channel 1 (Slot 1)"
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depends on MACH_SMDK6450 || MACH_SMDK6440
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help
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Support SDHCI Channel 1 8-bit bus.
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If selected, Channel 2 is disabled.
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endmenu
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endif
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@ -30,3 +30,4 @@ obj-y += dev-audio.o
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obj-$(CONFIG_S5P64X0_SETUP_I2C1) += setup-i2c1.o
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obj-$(CONFIG_S5P64X0_SETUP_FB_24BPP) += setup-fb-24bpp.o
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obj-$(CONFIG_S5P64X0_SETUP_SPI) += setup-spi.o
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obj-$(CONFIG_S5P64X0_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
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@ -40,6 +40,7 @@
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#include <plat/s5p6450.h>
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#include <plat/adc-core.h>
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#include <plat/fb-core.h>
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#include <plat/sdhci.h>
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/* Initial IO mappings */
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@ -112,6 +113,10 @@ void __init s5p6440_map_io(void)
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s3c_adc_setname("s3c64xx-adc");
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s3c_fb_setname("s5p64x0-fb");
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s5p64x0_default_sdhci0();
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s5p64x0_default_sdhci1();
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s5p6440_default_sdhci2();
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iotable_init(s5p64x0_iodesc, ARRAY_SIZE(s5p64x0_iodesc));
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iotable_init(s5p6440_iodesc, ARRAY_SIZE(s5p6440_iodesc));
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init_consistent_dma_size(SZ_8M);
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@ -123,6 +128,10 @@ void __init s5p6450_map_io(void)
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s3c_adc_setname("s3c64xx-adc");
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s3c_fb_setname("s5p64x0-fb");
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s5p64x0_default_sdhci0();
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s5p64x0_default_sdhci1();
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s5p6450_default_sdhci2();
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iotable_init(s5p64x0_iodesc, ARRAY_SIZE(s5p64x0_iodesc));
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iotable_init(s5p6450_iodesc, ARRAY_SIZE(s5p6450_iodesc));
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init_consistent_dma_size(SZ_8M);
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104
arch/arm/mach-s5p64x0/setup-sdhci-gpio.c
Normal file
104
arch/arm/mach-s5p64x0/setup-sdhci-gpio.c
Normal file
@ -0,0 +1,104 @@
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/* linux/arch/arm/mach-s5p64x0/setup-sdhci-gpio.c
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*
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* Copyright (c) 2011 Samsung Electronics Co., Ltd.
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* http://www.samsung.com/
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*
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* S5P64X0 - Helper functions for setting up SDHCI device(s) GPIO (HSMMC)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <linux/gpio.h>
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#include <mach/regs-gpio.h>
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#include <mach/regs-clock.h>
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#include <plat/gpio-cfg.h>
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#include <plat/sdhci.h>
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#include <plat/cpu.h>
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void s5p64x0_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
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{
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struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
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/* Set all the necessary GPG pins to special-function 2 */
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if (soc_is_s5p6450())
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s3c_gpio_cfgrange_nopull(S5P6450_GPG(0), 2 + width,
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S3C_GPIO_SFN(2));
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else
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s3c_gpio_cfgrange_nopull(S5P6440_GPG(0), 2 + width,
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S3C_GPIO_SFN(2));
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/* Set GPG[6] pin to special-function 2 - MMC0 CDn */
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if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
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if (soc_is_s5p6450()) {
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s3c_gpio_setpull(S5P6450_GPG(6), S3C_GPIO_PULL_UP);
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s3c_gpio_cfgpin(S5P6450_GPG(6), S3C_GPIO_SFN(2));
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} else {
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s3c_gpio_setpull(S5P6440_GPG(6), S3C_GPIO_PULL_UP);
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s3c_gpio_cfgpin(S5P6440_GPG(6), S3C_GPIO_SFN(2));
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}
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}
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}
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void s5p64x0_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
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{
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struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
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/* Set GPH[0:1] pins to special-function 2 - CLK and CMD */
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if (soc_is_s5p6450())
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s3c_gpio_cfgrange_nopull(S5P6450_GPH(0), 2, S3C_GPIO_SFN(2));
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else
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s3c_gpio_cfgrange_nopull(S5P6440_GPH(0), 2 , S3C_GPIO_SFN(2));
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switch (width) {
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case 8:
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/* Set data pins GPH[6:9] special-function 2 */
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if (soc_is_s5p6450())
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s3c_gpio_cfgrange_nopull(S5P6450_GPH(6), 4,
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S3C_GPIO_SFN(2));
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else
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s3c_gpio_cfgrange_nopull(S5P6440_GPH(6), 4,
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S3C_GPIO_SFN(2));
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case 4:
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/* set data pins GPH[2:5] special-function 2 */
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if (soc_is_s5p6450())
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s3c_gpio_cfgrange_nopull(S5P6450_GPH(2), 4,
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S3C_GPIO_SFN(2));
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else
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s3c_gpio_cfgrange_nopull(S5P6440_GPH(2), 4,
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S3C_GPIO_SFN(2));
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default:
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break;
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}
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/* Set GPG[6] pin to special-funtion 3 : MMC1 CDn */
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if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
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if (soc_is_s5p6450()) {
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s3c_gpio_setpull(S5P6450_GPG(6), S3C_GPIO_PULL_UP);
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s3c_gpio_cfgpin(S5P6450_GPG(6), S3C_GPIO_SFN(3));
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} else {
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s3c_gpio_setpull(S5P6440_GPG(6), S3C_GPIO_PULL_UP);
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s3c_gpio_cfgpin(S5P6440_GPG(6), S3C_GPIO_SFN(3));
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}
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}
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}
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void s5p6440_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
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{
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/* Set GPC[4:5] pins to special-function 3 - CLK and CMD */
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s3c_gpio_cfgrange_nopull(S5P6440_GPC(4), 2, S3C_GPIO_SFN(3));
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/* Set data pins GPH[6:9] pins to special-function 3 */
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s3c_gpio_cfgrange_nopull(S5P6440_GPH(6), 4, S3C_GPIO_SFN(3));
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}
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void s5p6450_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
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{
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/* Set all the necessary GPG pins to special-function 3 */
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s3c_gpio_cfgrange_nopull(S5P6450_GPG(7), 2 + width, S3C_GPIO_SFN(3));
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}
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@ -123,6 +123,10 @@ extern void exynos4_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
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extern void exynos4_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
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extern void exynos4_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
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extern void exynos4_setup_sdhci3_cfg_gpio(struct platform_device *, int w);
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extern void s5p64x0_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
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extern void s5p64x0_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
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extern void s5p6440_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
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extern void s5p6450_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
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/* S3C2416 SDHCI setup */
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@ -146,6 +150,7 @@ static inline void s3c2416_default_sdhci0(void) { }
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static inline void s3c2416_default_sdhci1(void) { }
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#endif /* CONFIG_S3C2416_SETUP_SDHCI */
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/* S3C64XX SDHCI setup */
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#ifdef CONFIG_S3C64XX_SETUP_SDHCI
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@ -201,6 +206,45 @@ static inline void s3c6400_default_sdhci2(void) { }
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#endif /* CONFIG_S3C64XX_SETUP_SDHCI */
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/* S5P64X0 SDHCI setup */
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#ifdef CONFIG_S5P64X0_SETUP_SDHCI
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static inline void s5p64x0_default_sdhci0(void)
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{
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#ifdef CONFIG_S3C_DEV_HSMMC
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s3c_hsmmc0_def_platdata.cfg_gpio = s5p64x0_setup_sdhci0_cfg_gpio;
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#endif
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}
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static inline void s5p64x0_default_sdhci1(void)
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{
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#ifdef CONFIG_S3C_DEV_HSMMC1
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s3c_hsmmc1_def_platdata.cfg_gpio = s5p64x0_setup_sdhci1_cfg_gpio;
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#endif
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}
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static inline void s5p6440_default_sdhci2(void)
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{
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#ifdef CONFIG_S3C_DEV_HSMMC2
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s3c_hsmmc2_def_platdata.cfg_gpio = s5p6440_setup_sdhci2_cfg_gpio;
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#endif
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}
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static inline void s5p6450_default_sdhci2(void)
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{
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#ifdef CONFIG_S3C_DEV_HSMMC2
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s3c_hsmmc2_def_platdata.cfg_gpio = s5p6450_setup_sdhci2_cfg_gpio;
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#endif
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}
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#else
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static inline void s5p64x0_default_sdhci0(void) { }
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static inline void s5p64x0_default_sdhci1(void) { }
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static inline void s5p6440_default_sdhci2(void) { }
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static inline void s5p6450_default_sdhci2(void) { }
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#endif /* CONFIG_S5P64X0_SETUP_SDHCI */
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/* S5PC100 SDHCI setup */
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#ifdef CONFIG_S5PC100_SETUP_SDHCI
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