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media: i2c: ar0521: fix spellos
Fix spelling mistakes as reported by codespell. Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Cc: Krzysztof Hałasa <khalasa@piap.pl> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
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@ -314,7 +314,7 @@ static void ar0521_calc_pll(struct ar0521_dev *sensor)
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* In the clock tree:
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* MIPI_CLK = PIXEL_CLOCK * bpp / 2 / 2
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*
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* Generic pixel_rate to bus clock frequencey equation:
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* Generic pixel_rate to bus clock frequency equation:
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* MIPI_CLK = V4L2_CID_PIXEL_RATE * bpp / lanes / 2
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*
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* From which we derive the PIXEL_CLOCK to use in the clock tree:
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@ -327,7 +327,7 @@ static void ar0521_calc_pll(struct ar0521_dev *sensor)
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*
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* TODO: in case we have less data lanes we have to reduce the desired
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* VCO not to exceed the limits specified by the datasheet and
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* consequentially reduce the obtained pixel clock.
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* consequently reduce the obtained pixel clock.
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*/
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pixel_clock = AR0521_PIXEL_CLOCK_RATE * 2 / sensor->lane_count;
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bpp = ar0521_code_to_bpp(sensor);
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@ -806,7 +806,7 @@ static const struct initial_reg {
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REGS(be(0x3F00),
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be(0x0017), /* 3F00: BM_T0 */
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be(0x02DD), /* 3F02: BM_T1 */
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/* 3F04: if Ana_gain less than 2, use noise_floor0, multipl */
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/* 3F04: if Ana_gain less than 2, use noise_floor0, multiply */
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be(0x0020),
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/* 3F06: if Ana_gain between 4 and 7, use noise_floor2 and */
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be(0x0040),
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