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staging: pi433: Remove unused driver
Marcus started a project in 2016 to bring the pi433 alive. One project was funded successfully but the second not. So only a few pi433 got sold to early adaptors during this time that ended late 2017. There is a simple user space program available for a demo with the pi433 but that does not use this driver. The driver is unused since 2018. No description or user space application to use it can be found. To bring it alive the device tree needs to be adjusted manually. The last patch reviewed by Marcus was in June 2018, last patch tested was in July 2017. No response since 27. March 2024 regarding the removal of the driver. Remove unused driver because of the above named reasons. Link: https://lore.kernel.org/linux-staging/c4c5ab38-8c67-4c21-86bc-f4f3c06be358@gmail.com/ Link: https://www.kickstarter.com/projects/1292669042/pi433-a-radio-module-funkmodul-for-raspberry-pi Link: https://www.kickstarter.com/projects/1292669042/smarthome-pi/comments Link: https://www.pi433.de/en.html Signed-off-by: Philipp Hortmann <philipp.g.hortmann@gmail.com> Cc: Marcus Wolf <marcus.wolf@wolf-entwicklungen.de> Link: https://lore.kernel.org/r/20240421195717.GA10943@matrix-ESPRIMO-P710 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Philipp Hortmann
Greg Kroah-Hartman
parent
cf707f77a1
commit
eb563dc752
@ -60,8 +60,6 @@ source "drivers/staging/greybus/Kconfig"
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source "drivers/staging/vc04_services/Kconfig"
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source "drivers/staging/pi433/Kconfig"
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source "drivers/staging/axis-fifo/Kconfig"
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source "drivers/staging/fieldbus/Kconfig"
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@ -20,6 +20,5 @@ obj-$(CONFIG_MOST) += most/
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obj-$(CONFIG_KS7010) += ks7010/
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obj-$(CONFIG_GREYBUS) += greybus/
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obj-$(CONFIG_BCM2835_VCHIQ) += vc04_services/
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obj-$(CONFIG_PI433) += pi433/
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obj-$(CONFIG_XIL_AXIS_FIFO) += axis-fifo/
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obj-$(CONFIG_FIELDBUS_DEV) += fieldbus/
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@ -1,48 +0,0 @@
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// Definitions for Pi433
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/dts-v1/;
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/plugin/;
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/ {
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compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709";
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};
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&spi0 {
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#address-cells = <1>;
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#size-cells = <0>;
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status = "okay";
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spidev@0{
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reg = <0>;
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status = "disabled";
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};
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spidev@1{
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reg = <1>;
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status = "disabled";
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};
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};
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&gpio {
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pi433_pins: pi433_pins {
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brcm,pins = <7 25 24>;
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brcm,function = <0 0 0>; // in in in
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};
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};
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&spi0 {
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#address-cells = <1>;
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#size-cells = <0>;
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status = "okay";
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pi433: pi433@0 {
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compatible = "Smarthome-Wolf,pi433";
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reg = <0>;
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spi-max-frequency = <10000000>;
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status = "okay";
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pinctrl-0 = <&pi433_pins>;
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DIO0-gpio = <&gpio 24 0>;
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DIO1-gpio = <&gpio 25 0>;
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DIO2-gpio = <&gpio 7 0>;
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};
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};
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@ -1,62 +0,0 @@
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* Smarthome-Wolf Pi433 - a 433MHz radio module/shield for Raspberry Pi (see www.pi433.de)
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Required properties:
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- compatible: must be "Smarthome-Wolf,pi433"
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- reg: chip select of SPI Interface
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- DIOx-gpio must be dedicated to the GPIO, connected with DIOx of the RFM69 module
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Example:
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With the following lines in gpio-section, the gpio pins, connected with pi433 are
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reserved/declared.
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&gpio{
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[...]
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pi433_pins: pi433_pins {
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brcm,pins = <7 25 24>;
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brcm,function = <0 0 0>; // in in in
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};
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[...]
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}
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With the following lines in spi section, the device pi433 is declared.
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It consists of the three gpio pins and an spi interface (here chip select 0)
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&spi0{
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[...]
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pi433: pi433@0 {
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compatible = "Smarthome-Wolf,pi433";
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reg = <0>; /* CE 0 */
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#address-cells = <1>;
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#size-cells = <0>;
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spi-max-frequency = <10000000>;
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pinctrl-0 = <&pi433_pins>;
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DIO0-gpio = <&gpio 24 0>;
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DIO1-gpio = <&gpio 25 0>;
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DIO2-gpio = <&gpio 7 0>;
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};
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}
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For Raspbian users only
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=======================
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Since Raspbian supports device tree overlays, you may use an overlay instead
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of editing your boards device tree.
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To use the overlay, you need to compile the file pi433-overlay.dtso which can
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be found alongside this documentation.
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The file needs to be compiled - either manually or by integration in your kernel
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source tree. For a manual compile, you may use a command line like the following:
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'linux/scripts/dtc/dtc -@ -I dts -O dtb -o pi433.dtbo pi433-overlay.dtso'
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For compiling inside of the kernel tree, you need to copy pi433-overlay.dtso to
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arch/arm/boot/dts/overlays and you need to add the file to the list of files
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in the Makefile over there. Execute 'make dtbs' in kernel tree root to make the
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kernel make files compile the device tree overlay for you.
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@ -1,274 +0,0 @@
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=====
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Pi433
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=====
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Introduction
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============
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This driver is for controlling pi433, a radio module for the Raspberry Pi
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(www.pi433.de). It supports transmission and reception. It can be opened
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by multiple applications for transmission and reception. While transmit
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jobs are queued and processed automatically in the background, the first
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application asking for reception will block out all other applications
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until something gets received terminates the read request.
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The driver supports on the fly reloading of the hardware fifo of the rf
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chip, thus enabling for much longer telegrams than the hardware fifo size.
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Description of driver operation
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===============================
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a) transmission
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Each transmission can take place with a different configuration of the rf
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module. Therefore each application can set its own set of parameters. The driver
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takes care, that each transmission takes place with the parameterset of the
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application, that requests the transmission. To allow the transmission to take
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place in the background, a tx thread is introduced.
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The transfer of data from the main thread to the tx thread is realised by a
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kfifo. With each write request of an application, the passed in data and the
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corresponding parameter set gets written to the kfifo.
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On the other "side" of the kfifo, the tx thread continuously checks, whether the
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kfifo is empty. If not, it gets one set of config and data from the kfifo. If
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there is no receive request or the receiver is still waiting for something in
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the air, the rf module is set to standby, the parameters for transmission gets
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set, the hardware fifo of the rf chip gets preloaded and the transmission gets
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started. Upon hardware fifo threshold interrupt it gets reloaded, thus enabling
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much longer telegrams than the hardware fifo size. If the telegram is sent and there
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is more data available in the kfifo, the procedure is repeated. If not the
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transmission cycle ends.
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b) reception
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Since there is only one application allowed to receive data at a time, for
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reception there is only one configuration set.
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As soon as an application sets a request for receiving a telegram, the reception
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configuration set is written to the rf module and it gets set into receiving mode.
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Now the driver is waiting, that a predefined RSSI level (signal strength at the
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receiver) is reached. Until this hasn't happened, the reception can be
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interrupted by the transmission thread at any time to insert a transmission cycle.
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As soon as the predefined RSSI level is met, a receiving cycle starts. Similar
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as described for the transmission cycle the read out of the hardware fifo is done
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dynamically. Upon each hardware fifo threshold interrupt, a portion of data gets
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read. So also for reception it is possible to receive more data than the hardware
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fifo can hold.
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Driver API
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==========
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The driver is currently implemented as a character device. Therefore it supports
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the calls open, ioctl, read, write and close.
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params for ioctl
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----------------
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There are four options:
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PI433_IOC_RD_TX_CFG - get the transmission parameters from the driver
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PI433_IOC_WR_TX_CFG - set the transmission parameters
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PI433_IOC_RD_RX_CFG - get the receiving parameters from the driver
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PI433_IOC_WR_RX_CFG - set the receiving parameters
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The tx configuration is transferred via struct pi433_tx_cfg, the parameterset for transmission.
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It is divided into two sections: rf parameters and packet format.
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rf params:
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frequency
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frequency used for transmission.
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Allowed values: 433050000...434790000
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bit_rate
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bit rate used for transmission.
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Allowed values: #####
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dev_frequency
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frequency deviation in case of FSK.
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Allowed values: 600...500000
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modulation
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FSK - frequency shift key
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OOK - On-Off-key
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modShaping
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shapingOff - no shaping
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shaping1_0 - gauss filter with BT 1 (FSK only)
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shaping0_5 - gauss filter with BT 0.5 (FSK only)
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shaping0_3 - gauss filter with BT 0.3 (FSK only)
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shapingBR - filter cut off at BR (OOK only)
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shaping2BR - filter cut off at 2*BR (OOK only)
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pa_ramp (FSK only)
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ramp3400 - amp ramps up in 3.4ms
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ramp2000 - amp ramps up in 2.0ms
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ramp1000 - amp ramps up in 1ms
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ramp500 - amp ramps up in 500us
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ramp250 - amp ramps up in 250us
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ramp125 - amp ramps up in 125us
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ramp100 - amp ramps up in 100us
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ramp62 - amp ramps up in 62us
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ramp50 - amp ramps up in 50us
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ramp40 - amp ramps up in 40us
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ramp31 - amp ramps up in 31us
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ramp25 - amp ramps up in 25us
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ramp20 - amp ramps up in 20us
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ramp15 - amp ramps up in 15us
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ramp12 - amp ramps up in 12us
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ramp10 - amp ramps up in 10us
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tx_start_condition
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fifo_level - transmission starts, if fifo is filled to
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threshold level
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fifo_not_empty - transmission starts, as soon as there is one
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byte in internal fifo
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repetitions
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This gives the option, to send a telegram multiple times. Default: 1
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packet format:
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enable_preamble
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optionOn - a preamble will be automatically generated
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optionOff - no preamble will be generated
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enable_sync
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optionOn - a sync word will be automatically added to
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the telegram after the preamble
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optionOff - no sync word will be added
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Attention: While possible to generate sync without preamble, the
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receiver won't be able to detect the sync without preamble.
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enable_length_byte
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optionOn - the length of the telegram will be automatically
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added to the telegram. It's part of the payload
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optionOff - no length information will be automatically added
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to the telegram.
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Attention: For telegram length over 255 bytes, this option can't be used
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Attention: should be used in combination with sync, only
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enable_address_byte
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optionOn - the address byte will be automatically added to the
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telegram. It's part of the payload
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optionOff - the address byte will not be added to the telegram.
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The address byte can be used for address filtering, so the receiver
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will only receive telegrams with a given address byte.
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Attention: should be used in combination with sync, only
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enable_crc
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optionOn - an crc will be automatically calculated over the
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payload of the telegram and added to the telegram
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after payload.
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optionOff - no crc will be calculated
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preamble_length
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length of the preamble. Allowed values: 0...65536
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sync_length
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length of the sync word. Allowed values: 0...8
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fixed_message_length
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length of the payload of the telegram. Will override the length
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given by the buffer, passed in with the write command. Will be
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ignored if set to zero.
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sync_pattern[8]
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contains up to eight values, that are used as the sync pattern
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on sync option
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address_byte
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one byte, used as address byte on address byte option.
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The rx configuration is transferred via struct pi433_rx_cfg, the parameterset for receiving. It is divided into two sections: rf parameters and packet format.
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rf params:
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frequency
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frequency used for transmission.
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Allowed values: 433050000...434790000
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bit_rate
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bit rate used for transmission.
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Allowed values: #####
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dev_frequency
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frequency deviation in case of FSK.
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Allowed values: 600...500000
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modulation
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FSK - frequency shift key
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OOK - on off key
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rssi_threshold
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threshold value for the signal strength on the receiver input.
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If this value is exceeded, a reception cycle starts
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Allowed values: 0...255
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threshold_decrement
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in order to adapt to different levels of singnal strength, over
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time the receiver gets more and more sensitive. This value
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determs, how fast the sensitivity increases.
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step_0_5db - increase in 0,5dB steps
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step_1_0db - increase in 1 db steps
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step_1_5db - increase in 1,5dB steps
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step_2_0db - increase in 2 db steps
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step_3_0db - increase in 3 db steps
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step_4_0db - increase in 4 db steps
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step_5_0db - increase in 5 db steps
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step_6_0db - increase in 6 db steps
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antenna_impedance
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sets the electrical adoption of the antenna
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fifty_ohm - for antennas with an impedance of 50Ohm
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two_hundred_ohm - for antennas with an impedance of 200Ohm
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lna_gain
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sets the gain of the low noise amp
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automatic - lna gain is determined by an agc
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max - lna gain is set to maximum
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max_minus_6 - lna gain is set to 6db below max
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max_minus_12 - lna gain is set to 12db below max
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max_minus_24 - lna gain is set to 24db below max
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max_minus_36 - lna gain is set to 36db below max
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max_minus_48 - lna gain is set to 48db below max
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bw_mantisse
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sets the bandwidth of the channel filter - part one: mantisse.
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mantisse16 - mantisse is set to 16
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mantisse20 - mantisse is set to 20
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mantisse24 - mantisse is set to 24
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bw_exponent
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sets the bandwidth of the channel filter - part two: exponent.
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Allowd values: 0...7
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dagc;
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operation mode of the digital automatic gain control
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normal_mode
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improve
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improve_for_low_modulation_index
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packet format:
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enable_sync
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optionOn - sync detection is enabled. If configured sync pattern
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isn't found, telegram will be internally discarded
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optionOff - sync detection is disabled.
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enable_length_byte
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optionOn - First byte of payload will be used as a length byte,
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regardless of the amount of bytes that were requested
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by the read request.
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optionOff - Number of bytes to be read will be set according to
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amount of bytes that were requested by the read request.
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Attention: should be used in combination with sync, only
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enable_address_filtering;
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filtering_off - no address filtering will take place
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node_address - all telegrams, not matching the node
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address will be internally discarded
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node_or_broadcast_address - all telegrams, neither matching the
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node, nor the broadcast address will
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be internally discarded
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Attention: Sync option must be enabled in order to use this feature
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enable_crc
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optionOn - a crc will be calculated over the payload of
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the telegram, that was received. If the
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calculated crc doesn't match to two bytes,
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that follow the payload, the telegram will be
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internally discarded.
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Attention: This option is only operational if sync on and fixed length
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or length byte is used
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sync_length
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Gives the length of the payload.
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Attention: This setting must meet the setting of the transmitter,
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if sync option is used.
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fixed_message_length
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Overrides the telegram length either given by the first byte of
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payload or by the read request.
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bytes_to_drop
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gives the number of bytes, that will be dropped before transferring
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data to the read buffer
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This option is only useful if all packet helper are switched
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off and the rf chip is used in raw receiving mode. This may be
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needed, if a telegram of a third party device should be received,
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using a protocol not compatible with the packet engine of the rf69 chip.
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sync_pattern[8]
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contains up to eight values, that are used as the sync pattern
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on sync option.
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This setting must meet the configuration of the transmitting device,
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if sync option is enabled.
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node_address
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one byte, used as node address byte on address byte option.
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broadcast_address
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one byte, used as broadcast address byte on address byte option.
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@ -1,17 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0
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config PI433
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tristate "Pi433 - a 433MHz radio module for Raspberry Pi"
|
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depends on SPI
|
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help
|
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This option allows you to enable support for the radio module Pi433.
|
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|
||||
Pi433 is a shield that fits onto the GPIO header of a Raspberry Pi
|
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or compatible. It extends the Raspberry Pi with the option, to
|
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send and receive data in the 433MHz ISM band - for example to
|
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communicate between two systems without using ethernet or bluetooth
|
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or for control or read sockets, actors, sensors, widely available
|
||||
for low price.
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||||
|
||||
For details or the option to buy, please visit https://pi433.de/en.html
|
||||
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If in doubt, say N here, but saying yes most probably won't hurt
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@ -1,4 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0
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obj-$(CONFIG_PI433) += pi433.o
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pi433-objs := pi433_if.o rf69.o
|
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@ -1,8 +0,0 @@
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* currently the code introduces new IOCTLs. I'm afraid this is a bad idea.
|
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-> Replace this with another interface, hints are welcome!
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* Some missing data (marked with ###) needs to be added in the documentation
|
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* Change (struct pi433_tx_cfg)->bit_rate to be a u32 so that we can support
|
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bit rates up to 300kbps per the spec.
|
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-> This configuration needs to be moved to sysfs instead of being done through
|
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IOCTL. Going forward, we need to port userspace tools to use sysfs instead
|
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of IOCTL and then we would delete IOCTL.
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File diff suppressed because it is too large
Load Diff
@ -1,148 +0,0 @@
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||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* userspace interface for pi433 radio module
|
||||
*
|
||||
* Pi433 is a 433MHz radio module for the Raspberry Pi.
|
||||
* It is based on the HopeRf Module RFM69CW. Therefore, inside of this
|
||||
* driver you'll find an abstraction of the rf69 chip.
|
||||
*
|
||||
* If needed this driver could also be extended to support other
|
||||
* devices based on HopeRf rf69 as well as HopeRf modules with a similar
|
||||
* interface such as RFM69HCW, RFM12, RFM95 and so on.
|
||||
*
|
||||
* Copyright (C) 2016 Wolf-Entwicklungen
|
||||
* Marcus Wolf <linux@wolf-entwicklungen.de>
|
||||
*/
|
||||
|
||||
#ifndef PI433_H
|
||||
#define PI433_H
|
||||
|
||||
#include <linux/types.h>
|
||||
#include "rf69_enum.h"
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
|
||||
enum option_on_off {
|
||||
OPTION_OFF,
|
||||
OPTION_ON
|
||||
};
|
||||
|
||||
/* IOCTL structs and commands */
|
||||
|
||||
/**
|
||||
* struct pi433_tx_cfg
|
||||
* describes the configuration of the radio module for sending data
|
||||
* @frequency:
|
||||
* @bit_rate:
|
||||
* @modulation:
|
||||
* @data_mode:
|
||||
* @preamble_length:
|
||||
* @sync_pattern:
|
||||
* @tx_start_condition:
|
||||
* @payload_length:
|
||||
* @repetitions:
|
||||
*
|
||||
* ATTENTION:
|
||||
* If the contents of 'pi433_tx_cfg' ever change
|
||||
* incompatibly, then the ioctl number (see define below) must change.
|
||||
*
|
||||
* NOTE: struct layout is the same in 64bit and 32bit userspace.
|
||||
*/
|
||||
#define PI433_TX_CFG_IOCTL_NR 0
|
||||
struct pi433_tx_cfg {
|
||||
__u32 frequency;
|
||||
__u16 bit_rate;
|
||||
__u32 dev_frequency;
|
||||
enum modulation modulation;
|
||||
enum mod_shaping mod_shaping;
|
||||
|
||||
enum pa_ramp pa_ramp;
|
||||
|
||||
enum tx_start_condition tx_start_condition;
|
||||
|
||||
__u16 repetitions;
|
||||
|
||||
/* packet format */
|
||||
enum option_on_off enable_preamble;
|
||||
enum option_on_off enable_sync;
|
||||
enum option_on_off enable_length_byte;
|
||||
enum option_on_off enable_address_byte;
|
||||
enum option_on_off enable_crc;
|
||||
|
||||
__u16 preamble_length;
|
||||
__u8 sync_length;
|
||||
__u8 fixed_message_length;
|
||||
|
||||
__u8 sync_pattern[8];
|
||||
__u8 address_byte;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct pi433_rx_cfg
|
||||
* describes the configuration of the radio module for receiving data
|
||||
* @frequency:
|
||||
* @bit_rate:
|
||||
* @modulation:
|
||||
* @data_mode:
|
||||
* @preamble_length:
|
||||
* @sync_pattern:
|
||||
* @tx_start_condition:
|
||||
* @payload_length:
|
||||
* @repetitions:
|
||||
*
|
||||
* ATTENTION:
|
||||
* If the contents of 'pi433_rx_cfg' ever change
|
||||
* incompatibly, then the ioctl number (see define below) must change
|
||||
*
|
||||
* NOTE: struct layout is the same in 64bit and 32bit userspace.
|
||||
*/
|
||||
#define PI433_RX_CFG_IOCTL_NR 1
|
||||
struct pi433_rx_cfg {
|
||||
__u32 frequency;
|
||||
__u16 bit_rate;
|
||||
__u32 dev_frequency;
|
||||
|
||||
enum modulation modulation;
|
||||
|
||||
__u8 rssi_threshold;
|
||||
enum threshold_decrement threshold_decrement;
|
||||
enum antenna_impedance antenna_impedance;
|
||||
enum lna_gain lna_gain;
|
||||
enum mantisse bw_mantisse; /* normal: 0x50 */
|
||||
__u8 bw_exponent; /* during AFC: 0x8b */
|
||||
enum dagc dagc;
|
||||
|
||||
/* packet format */
|
||||
enum option_on_off enable_sync;
|
||||
|
||||
/* should be used in combination with sync, only */
|
||||
enum option_on_off enable_length_byte;
|
||||
|
||||
/* operational with sync, only */
|
||||
enum address_filtering enable_address_filtering;
|
||||
|
||||
/* only operational, if sync on and fixed length or length byte is used */
|
||||
enum option_on_off enable_crc;
|
||||
|
||||
__u8 sync_length;
|
||||
__u8 fixed_message_length;
|
||||
__u32 bytes_to_drop;
|
||||
|
||||
__u8 sync_pattern[8];
|
||||
__u8 node_address;
|
||||
__u8 broadcast_address;
|
||||
};
|
||||
|
||||
#define PI433_IOC_MAGIC 'r'
|
||||
|
||||
#define PI433_IOC_RD_TX_CFG \
|
||||
_IOR(PI433_IOC_MAGIC, PI433_TX_CFG_IOCTL_NR, char[sizeof(struct pi433_tx_cfg)])
|
||||
#define PI433_IOC_WR_TX_CFG \
|
||||
_IOW(PI433_IOC_MAGIC, PI433_TX_CFG_IOCTL_NR, char[sizeof(struct pi433_tx_cfg)])
|
||||
|
||||
#define PI433_IOC_RD_RX_CFG \
|
||||
_IOR(PI433_IOC_MAGIC, PI433_RX_CFG_IOCTL_NR, char[sizeof(struct pi433_rx_cfg)])
|
||||
#define PI433_IOC_WR_RX_CFG \
|
||||
_IOW(PI433_IOC_MAGIC, PI433_RX_CFG_IOCTL_NR, char[sizeof(struct pi433_rx_cfg)])
|
||||
|
||||
#endif /* PI433_H */
|
||||
@ -1,832 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* abstraction of the spi interface of HopeRf rf69 radio module
|
||||
*
|
||||
* Copyright (C) 2016 Wolf-Entwicklungen
|
||||
* Marcus Wolf <linux@wolf-entwicklungen.de>
|
||||
*/
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/spi/spi.h>
|
||||
#include <linux/units.h>
|
||||
|
||||
#include "rf69.h"
|
||||
#include "rf69_registers.h"
|
||||
|
||||
#define F_OSC (32 * HZ_PER_MHZ)
|
||||
|
||||
/*-------------------------------------------------------------------------*/
|
||||
|
||||
u8 rf69_read_reg(struct spi_device *spi, u8 addr)
|
||||
{
|
||||
return spi_w8r8(spi, addr);
|
||||
}
|
||||
|
||||
static int rf69_write_reg(struct spi_device *spi, u8 addr, u8 value)
|
||||
{
|
||||
char buffer[2];
|
||||
|
||||
buffer[0] = addr | WRITE_BIT;
|
||||
buffer[1] = value;
|
||||
|
||||
return spi_write(spi, &buffer, ARRAY_SIZE(buffer));
|
||||
}
|
||||
|
||||
/*-------------------------------------------------------------------------*/
|
||||
|
||||
static int rf69_set_bit(struct spi_device *spi, u8 reg, u8 mask)
|
||||
{
|
||||
u8 tmp;
|
||||
|
||||
tmp = rf69_read_reg(spi, reg);
|
||||
tmp = tmp | mask;
|
||||
return rf69_write_reg(spi, reg, tmp);
|
||||
}
|
||||
|
||||
static int rf69_clear_bit(struct spi_device *spi, u8 reg, u8 mask)
|
||||
{
|
||||
u8 tmp;
|
||||
|
||||
tmp = rf69_read_reg(spi, reg);
|
||||
tmp = tmp & ~mask;
|
||||
return rf69_write_reg(spi, reg, tmp);
|
||||
}
|
||||
|
||||
static inline int rf69_read_mod_write(struct spi_device *spi, u8 reg,
|
||||
u8 mask, u8 value)
|
||||
{
|
||||
u8 tmp;
|
||||
|
||||
tmp = rf69_read_reg(spi, reg);
|
||||
tmp = (tmp & ~mask) | value;
|
||||
return rf69_write_reg(spi, reg, tmp);
|
||||
}
|
||||
|
||||
/*-------------------------------------------------------------------------*/
|
||||
|
||||
int rf69_get_version(struct spi_device *spi)
|
||||
{
|
||||
return rf69_read_reg(spi, REG_VERSION);
|
||||
}
|
||||
|
||||
int rf69_set_mode(struct spi_device *spi, enum mode mode)
|
||||
{
|
||||
static const u8 mode_map[] = {
|
||||
[transmit] = OPMODE_MODE_TRANSMIT,
|
||||
[receive] = OPMODE_MODE_RECEIVE,
|
||||
[synthesizer] = OPMODE_MODE_SYNTHESIZER,
|
||||
[standby] = OPMODE_MODE_STANDBY,
|
||||
[mode_sleep] = OPMODE_MODE_SLEEP,
|
||||
};
|
||||
|
||||
if (unlikely(mode >= ARRAY_SIZE(mode_map))) {
|
||||
dev_dbg(&spi->dev, "set: illegal mode %u\n", mode);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return rf69_read_mod_write(spi, REG_OPMODE, MASK_OPMODE_MODE,
|
||||
mode_map[mode]);
|
||||
|
||||
/*
|
||||
* we are using packet mode, so this check is not really needed
|
||||
* but waiting for mode ready is necessary when going from sleep
|
||||
* because the FIFO may not be immediately available from previous mode
|
||||
* while (_mode == RF69_MODE_SLEEP && (READ_REG(REG_IRQFLAGS1) &
|
||||
RF_IRQFLAGS1_MODEREADY) == 0x00); // Wait for ModeReady
|
||||
*/
|
||||
}
|
||||
|
||||
int rf69_set_data_mode(struct spi_device *spi, u8 data_mode)
|
||||
{
|
||||
return rf69_read_mod_write(spi, REG_DATAMODUL, MASK_DATAMODUL_MODE,
|
||||
data_mode);
|
||||
}
|
||||
|
||||
int rf69_set_modulation(struct spi_device *spi, enum modulation modulation)
|
||||
{
|
||||
static const u8 modulation_map[] = {
|
||||
[OOK] = DATAMODUL_MODULATION_TYPE_OOK,
|
||||
[FSK] = DATAMODUL_MODULATION_TYPE_FSK,
|
||||
};
|
||||
|
||||
if (unlikely(modulation >= ARRAY_SIZE(modulation_map))) {
|
||||
dev_dbg(&spi->dev, "set: illegal modulation %u\n", modulation);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return rf69_read_mod_write(spi, REG_DATAMODUL,
|
||||
MASK_DATAMODUL_MODULATION_TYPE,
|
||||
modulation_map[modulation]);
|
||||
}
|
||||
|
||||
static enum modulation rf69_get_modulation(struct spi_device *spi)
|
||||
{
|
||||
u8 modulation_reg;
|
||||
|
||||
modulation_reg = rf69_read_reg(spi, REG_DATAMODUL);
|
||||
|
||||
switch (modulation_reg & MASK_DATAMODUL_MODULATION_TYPE) {
|
||||
case DATAMODUL_MODULATION_TYPE_OOK:
|
||||
return OOK;
|
||||
case DATAMODUL_MODULATION_TYPE_FSK:
|
||||
return FSK;
|
||||
default:
|
||||
return UNDEF;
|
||||
}
|
||||
}
|
||||
|
||||
int rf69_set_modulation_shaping(struct spi_device *spi,
|
||||
enum mod_shaping mod_shaping)
|
||||
{
|
||||
switch (rf69_get_modulation(spi)) {
|
||||
case FSK:
|
||||
switch (mod_shaping) {
|
||||
case SHAPING_OFF:
|
||||
return rf69_read_mod_write(spi, REG_DATAMODUL,
|
||||
MASK_DATAMODUL_MODULATION_SHAPE,
|
||||
DATAMODUL_MODULATION_SHAPE_NONE);
|
||||
case SHAPING_1_0:
|
||||
return rf69_read_mod_write(spi, REG_DATAMODUL,
|
||||
MASK_DATAMODUL_MODULATION_SHAPE,
|
||||
DATAMODUL_MODULATION_SHAPE_1_0);
|
||||
case SHAPING_0_5:
|
||||
return rf69_read_mod_write(spi, REG_DATAMODUL,
|
||||
MASK_DATAMODUL_MODULATION_SHAPE,
|
||||
DATAMODUL_MODULATION_SHAPE_0_5);
|
||||
case SHAPING_0_3:
|
||||
return rf69_read_mod_write(spi, REG_DATAMODUL,
|
||||
MASK_DATAMODUL_MODULATION_SHAPE,
|
||||
DATAMODUL_MODULATION_SHAPE_0_3);
|
||||
default:
|
||||
dev_dbg(&spi->dev, "set: illegal mod shaping for FSK %u\n", mod_shaping);
|
||||
return -EINVAL;
|
||||
}
|
||||
case OOK:
|
||||
switch (mod_shaping) {
|
||||
case SHAPING_OFF:
|
||||
return rf69_read_mod_write(spi, REG_DATAMODUL,
|
||||
MASK_DATAMODUL_MODULATION_SHAPE,
|
||||
DATAMODUL_MODULATION_SHAPE_NONE);
|
||||
case SHAPING_BR:
|
||||
return rf69_read_mod_write(spi, REG_DATAMODUL,
|
||||
MASK_DATAMODUL_MODULATION_SHAPE,
|
||||
DATAMODUL_MODULATION_SHAPE_BR);
|
||||
case SHAPING_2BR:
|
||||
return rf69_read_mod_write(spi, REG_DATAMODUL,
|
||||
MASK_DATAMODUL_MODULATION_SHAPE,
|
||||
DATAMODUL_MODULATION_SHAPE_2BR);
|
||||
default:
|
||||
dev_dbg(&spi->dev, "set: illegal mod shaping for OOK %u\n", mod_shaping);
|
||||
return -EINVAL;
|
||||
}
|
||||
default:
|
||||
dev_dbg(&spi->dev, "set: modulation undefined\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
int rf69_set_bit_rate(struct spi_device *spi, u16 bit_rate)
|
||||
{
|
||||
int retval;
|
||||
u32 bit_rate_reg;
|
||||
u8 msb;
|
||||
u8 lsb;
|
||||
enum modulation mod;
|
||||
|
||||
// check if modulation is configured
|
||||
mod = rf69_get_modulation(spi);
|
||||
if (mod == UNDEF) {
|
||||
dev_dbg(&spi->dev, "setBitRate: modulation is undefined\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
// check input value
|
||||
if (bit_rate < 1200 || (mod == OOK && bit_rate > 32768)) {
|
||||
dev_dbg(&spi->dev, "setBitRate: illegal input param\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
// calculate reg settings
|
||||
bit_rate_reg = (F_OSC / bit_rate);
|
||||
|
||||
msb = (bit_rate_reg & 0xff00) >> 8;
|
||||
lsb = (bit_rate_reg & 0xff);
|
||||
|
||||
// transmit to RF 69
|
||||
retval = rf69_write_reg(spi, REG_BITRATE_MSB, msb);
|
||||
if (retval)
|
||||
return retval;
|
||||
retval = rf69_write_reg(spi, REG_BITRATE_LSB, lsb);
|
||||
if (retval)
|
||||
return retval;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int rf69_set_deviation(struct spi_device *spi, u32 deviation)
|
||||
{
|
||||
int retval;
|
||||
u64 f_reg;
|
||||
u64 f_step;
|
||||
u32 bit_rate_reg;
|
||||
u32 bit_rate;
|
||||
u8 msb;
|
||||
u8 lsb;
|
||||
u64 factor = 1000000; // to improve precision of calculation
|
||||
|
||||
// calculate bit rate
|
||||
bit_rate_reg = rf69_read_reg(spi, REG_BITRATE_MSB) << 8;
|
||||
bit_rate_reg |= rf69_read_reg(spi, REG_BITRATE_LSB);
|
||||
bit_rate = F_OSC / bit_rate_reg;
|
||||
|
||||
/*
|
||||
* frequency deviation must exceed 600 Hz but not exceed
|
||||
* 500kHz when taking bitrate dependency into consideration
|
||||
* to ensure proper modulation
|
||||
*/
|
||||
if (deviation < 600 || (deviation + (bit_rate / 2)) > 500000) {
|
||||
dev_dbg(&spi->dev,
|
||||
"set_deviation: illegal input param: %u\n", deviation);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
// calculat f step
|
||||
f_step = F_OSC * factor;
|
||||
do_div(f_step, 524288); // 524288 = 2^19
|
||||
|
||||
// calculate register settings
|
||||
f_reg = deviation * factor;
|
||||
do_div(f_reg, f_step);
|
||||
|
||||
msb = (f_reg & 0xff00) >> 8;
|
||||
lsb = (f_reg & 0xff);
|
||||
|
||||
// check msb
|
||||
if (msb & ~FDEVMASB_MASK) {
|
||||
dev_dbg(&spi->dev, "set_deviation: err in calc of msb\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
// write to chip
|
||||
retval = rf69_write_reg(spi, REG_FDEV_MSB, msb);
|
||||
if (retval)
|
||||
return retval;
|
||||
retval = rf69_write_reg(spi, REG_FDEV_LSB, lsb);
|
||||
if (retval)
|
||||
return retval;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int rf69_set_frequency(struct spi_device *spi, u32 frequency)
|
||||
{
|
||||
int retval;
|
||||
u32 f_max;
|
||||
u64 f_reg;
|
||||
u64 f_step;
|
||||
u8 msb;
|
||||
u8 mid;
|
||||
u8 lsb;
|
||||
u64 factor = 1000000; // to improve precision of calculation
|
||||
|
||||
// calculat f step
|
||||
f_step = F_OSC * factor;
|
||||
do_div(f_step, 524288); // 524288 = 2^19
|
||||
|
||||
// check input value
|
||||
f_max = div_u64(f_step * 8388608, factor);
|
||||
if (frequency > f_max) {
|
||||
dev_dbg(&spi->dev, "setFrequency: illegal input param\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
// calculate reg settings
|
||||
f_reg = frequency * factor;
|
||||
do_div(f_reg, f_step);
|
||||
|
||||
msb = (f_reg & 0xff0000) >> 16;
|
||||
mid = (f_reg & 0xff00) >> 8;
|
||||
lsb = (f_reg & 0xff);
|
||||
|
||||
// write to chip
|
||||
retval = rf69_write_reg(spi, REG_FRF_MSB, msb);
|
||||
if (retval)
|
||||
return retval;
|
||||
retval = rf69_write_reg(spi, REG_FRF_MID, mid);
|
||||
if (retval)
|
||||
return retval;
|
||||
retval = rf69_write_reg(spi, REG_FRF_LSB, lsb);
|
||||
if (retval)
|
||||
return retval;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int rf69_enable_amplifier(struct spi_device *spi, u8 amplifier_mask)
|
||||
{
|
||||
return rf69_set_bit(spi, REG_PALEVEL, amplifier_mask);
|
||||
}
|
||||
|
||||
int rf69_disable_amplifier(struct spi_device *spi, u8 amplifier_mask)
|
||||
{
|
||||
return rf69_clear_bit(spi, REG_PALEVEL, amplifier_mask);
|
||||
}
|
||||
|
||||
int rf69_set_output_power_level(struct spi_device *spi, u8 power_level)
|
||||
{
|
||||
u8 pa_level, ocp, test_pa1, test_pa2;
|
||||
bool pa0, pa1, pa2, high_power;
|
||||
u8 min_power_level;
|
||||
|
||||
// check register pa_level
|
||||
pa_level = rf69_read_reg(spi, REG_PALEVEL);
|
||||
pa0 = pa_level & MASK_PALEVEL_PA0;
|
||||
pa1 = pa_level & MASK_PALEVEL_PA1;
|
||||
pa2 = pa_level & MASK_PALEVEL_PA2;
|
||||
|
||||
// check high power mode
|
||||
ocp = rf69_read_reg(spi, REG_OCP);
|
||||
test_pa1 = rf69_read_reg(spi, REG_TESTPA1);
|
||||
test_pa2 = rf69_read_reg(spi, REG_TESTPA2);
|
||||
high_power = (ocp == 0x0f) && (test_pa1 == 0x5d) && (test_pa2 == 0x7c);
|
||||
|
||||
if (pa0 && !pa1 && !pa2) {
|
||||
power_level += 18;
|
||||
min_power_level = 0;
|
||||
} else if (!pa0 && pa1 && !pa2) {
|
||||
power_level += 18;
|
||||
min_power_level = 16;
|
||||
} else if (!pa0 && pa1 && pa2) {
|
||||
if (high_power)
|
||||
power_level += 11;
|
||||
else
|
||||
power_level += 14;
|
||||
min_power_level = 16;
|
||||
} else {
|
||||
goto failed;
|
||||
}
|
||||
|
||||
// check input value
|
||||
if (power_level > 0x1f)
|
||||
goto failed;
|
||||
|
||||
if (power_level < min_power_level)
|
||||
goto failed;
|
||||
|
||||
// write value
|
||||
return rf69_read_mod_write(spi, REG_PALEVEL, MASK_PALEVEL_OUTPUT_POWER,
|
||||
power_level);
|
||||
failed:
|
||||
dev_dbg(&spi->dev, "set: illegal power level %u\n", power_level);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
int rf69_set_pa_ramp(struct spi_device *spi, enum pa_ramp pa_ramp)
|
||||
{
|
||||
static const u8 pa_ramp_map[] = {
|
||||
[ramp3400] = PARAMP_3400,
|
||||
[ramp2000] = PARAMP_2000,
|
||||
[ramp1000] = PARAMP_1000,
|
||||
[ramp500] = PARAMP_500,
|
||||
[ramp250] = PARAMP_250,
|
||||
[ramp125] = PARAMP_125,
|
||||
[ramp100] = PARAMP_100,
|
||||
[ramp62] = PARAMP_62,
|
||||
[ramp50] = PARAMP_50,
|
||||
[ramp40] = PARAMP_40,
|
||||
[ramp31] = PARAMP_31,
|
||||
[ramp25] = PARAMP_25,
|
||||
[ramp20] = PARAMP_20,
|
||||
[ramp15] = PARAMP_15,
|
||||
[ramp10] = PARAMP_10,
|
||||
};
|
||||
|
||||
if (unlikely(pa_ramp >= ARRAY_SIZE(pa_ramp_map))) {
|
||||
dev_dbg(&spi->dev, "set: illegal pa_ramp %u\n", pa_ramp);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return rf69_write_reg(spi, REG_PARAMP, pa_ramp_map[pa_ramp]);
|
||||
}
|
||||
|
||||
int rf69_set_antenna_impedance(struct spi_device *spi,
|
||||
enum antenna_impedance antenna_impedance)
|
||||
{
|
||||
switch (antenna_impedance) {
|
||||
case fifty_ohm:
|
||||
return rf69_clear_bit(spi, REG_LNA, MASK_LNA_ZIN);
|
||||
case two_hundred_ohm:
|
||||
return rf69_set_bit(spi, REG_LNA, MASK_LNA_ZIN);
|
||||
default:
|
||||
dev_dbg(&spi->dev, "set: illegal antenna impedance %u\n", antenna_impedance);
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
int rf69_set_lna_gain(struct spi_device *spi, enum lna_gain lna_gain)
|
||||
{
|
||||
static const u8 lna_gain_map[] = {
|
||||
[automatic] = LNA_GAIN_AUTO,
|
||||
[max] = LNA_GAIN_MAX,
|
||||
[max_minus_6] = LNA_GAIN_MAX_MINUS_6,
|
||||
[max_minus_12] = LNA_GAIN_MAX_MINUS_12,
|
||||
[max_minus_24] = LNA_GAIN_MAX_MINUS_24,
|
||||
[max_minus_36] = LNA_GAIN_MAX_MINUS_36,
|
||||
[max_minus_48] = LNA_GAIN_MAX_MINUS_48,
|
||||
};
|
||||
|
||||
if (unlikely(lna_gain >= ARRAY_SIZE(lna_gain_map))) {
|
||||
dev_dbg(&spi->dev, "set: illegal lna gain %u\n", lna_gain);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return rf69_read_mod_write(spi, REG_LNA, MASK_LNA_GAIN,
|
||||
lna_gain_map[lna_gain]);
|
||||
}
|
||||
|
||||
static int rf69_set_bandwidth_intern(struct spi_device *spi, u8 reg,
|
||||
enum mantisse mantisse, u8 exponent)
|
||||
{
|
||||
u8 bandwidth;
|
||||
|
||||
// check value for mantisse and exponent
|
||||
if (exponent > 7) {
|
||||
dev_dbg(&spi->dev, "set: illegal bandwidth exponent %u\n", exponent);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (mantisse != mantisse16 &&
|
||||
mantisse != mantisse20 &&
|
||||
mantisse != mantisse24) {
|
||||
dev_dbg(&spi->dev, "set: illegal bandwidth mantisse %u\n", mantisse);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
// read old value
|
||||
bandwidth = rf69_read_reg(spi, reg);
|
||||
|
||||
// "delete" mantisse and exponent = just keep the DCC setting
|
||||
bandwidth = bandwidth & MASK_BW_DCC_FREQ;
|
||||
|
||||
// add new mantisse
|
||||
switch (mantisse) {
|
||||
case mantisse16:
|
||||
bandwidth = bandwidth | BW_MANT_16;
|
||||
break;
|
||||
case mantisse20:
|
||||
bandwidth = bandwidth | BW_MANT_20;
|
||||
break;
|
||||
case mantisse24:
|
||||
bandwidth = bandwidth | BW_MANT_24;
|
||||
break;
|
||||
}
|
||||
|
||||
// add new exponent
|
||||
bandwidth = bandwidth | exponent;
|
||||
|
||||
// write back
|
||||
return rf69_write_reg(spi, reg, bandwidth);
|
||||
}
|
||||
|
||||
int rf69_set_bandwidth(struct spi_device *spi, enum mantisse mantisse,
|
||||
u8 exponent)
|
||||
{
|
||||
return rf69_set_bandwidth_intern(spi, REG_RXBW, mantisse, exponent);
|
||||
}
|
||||
|
||||
int rf69_set_bandwidth_during_afc(struct spi_device *spi,
|
||||
enum mantisse mantisse,
|
||||
u8 exponent)
|
||||
{
|
||||
return rf69_set_bandwidth_intern(spi, REG_AFCBW, mantisse, exponent);
|
||||
}
|
||||
|
||||
int rf69_set_ook_threshold_dec(struct spi_device *spi,
|
||||
enum threshold_decrement threshold_decrement)
|
||||
{
|
||||
static const u8 td_map[] = {
|
||||
[dec_every8th] = OOKPEAK_THRESHDEC_EVERY_8TH,
|
||||
[dec_every4th] = OOKPEAK_THRESHDEC_EVERY_4TH,
|
||||
[dec_every2nd] = OOKPEAK_THRESHDEC_EVERY_2ND,
|
||||
[dec_once] = OOKPEAK_THRESHDEC_ONCE,
|
||||
[dec_twice] = OOKPEAK_THRESHDEC_TWICE,
|
||||
[dec_4times] = OOKPEAK_THRESHDEC_4_TIMES,
|
||||
[dec_8times] = OOKPEAK_THRESHDEC_8_TIMES,
|
||||
[dec_16times] = OOKPEAK_THRESHDEC_16_TIMES,
|
||||
};
|
||||
|
||||
if (unlikely(threshold_decrement >= ARRAY_SIZE(td_map))) {
|
||||
dev_dbg(&spi->dev, "set: illegal OOK threshold decrement %u\n",
|
||||
threshold_decrement);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return rf69_read_mod_write(spi, REG_OOKPEAK, MASK_OOKPEAK_THRESDEC,
|
||||
td_map[threshold_decrement]);
|
||||
}
|
||||
|
||||
int rf69_set_dio_mapping(struct spi_device *spi, u8 dio_number, u8 value)
|
||||
{
|
||||
u8 mask;
|
||||
u8 shift;
|
||||
u8 dio_addr;
|
||||
u8 dio_value;
|
||||
|
||||
switch (dio_number) {
|
||||
case 0:
|
||||
mask = MASK_DIO0;
|
||||
shift = SHIFT_DIO0;
|
||||
dio_addr = REG_DIOMAPPING1;
|
||||
break;
|
||||
case 1:
|
||||
mask = MASK_DIO1;
|
||||
shift = SHIFT_DIO1;
|
||||
dio_addr = REG_DIOMAPPING1;
|
||||
break;
|
||||
case 2:
|
||||
mask = MASK_DIO2;
|
||||
shift = SHIFT_DIO2;
|
||||
dio_addr = REG_DIOMAPPING1;
|
||||
break;
|
||||
case 3:
|
||||
mask = MASK_DIO3;
|
||||
shift = SHIFT_DIO3;
|
||||
dio_addr = REG_DIOMAPPING1;
|
||||
break;
|
||||
case 4:
|
||||
mask = MASK_DIO4;
|
||||
shift = SHIFT_DIO4;
|
||||
dio_addr = REG_DIOMAPPING2;
|
||||
break;
|
||||
case 5:
|
||||
mask = MASK_DIO5;
|
||||
shift = SHIFT_DIO5;
|
||||
dio_addr = REG_DIOMAPPING2;
|
||||
break;
|
||||
default:
|
||||
dev_dbg(&spi->dev, "set: illegal dio number %u\n", dio_number);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
// read reg
|
||||
dio_value = rf69_read_reg(spi, dio_addr);
|
||||
// delete old value
|
||||
dio_value = dio_value & ~mask;
|
||||
// add new value
|
||||
dio_value = dio_value | value << shift;
|
||||
// write back
|
||||
return rf69_write_reg(spi, dio_addr, dio_value);
|
||||
}
|
||||
|
||||
int rf69_set_rssi_threshold(struct spi_device *spi, u8 threshold)
|
||||
{
|
||||
/* no value check needed - u8 exactly matches register size */
|
||||
|
||||
return rf69_write_reg(spi, REG_RSSITHRESH, threshold);
|
||||
}
|
||||
|
||||
int rf69_set_preamble_length(struct spi_device *spi, u16 preamble_length)
|
||||
{
|
||||
int retval;
|
||||
u8 msb, lsb;
|
||||
|
||||
/* no value check needed - u16 exactly matches register size */
|
||||
|
||||
/* calculate reg settings */
|
||||
msb = (preamble_length & 0xff00) >> 8;
|
||||
lsb = (preamble_length & 0xff);
|
||||
|
||||
/* transmit to chip */
|
||||
retval = rf69_write_reg(spi, REG_PREAMBLE_MSB, msb);
|
||||
if (retval)
|
||||
return retval;
|
||||
return rf69_write_reg(spi, REG_PREAMBLE_LSB, lsb);
|
||||
}
|
||||
|
||||
int rf69_enable_sync(struct spi_device *spi)
|
||||
{
|
||||
return rf69_set_bit(spi, REG_SYNC_CONFIG, MASK_SYNC_CONFIG_SYNC_ON);
|
||||
}
|
||||
|
||||
int rf69_disable_sync(struct spi_device *spi)
|
||||
{
|
||||
return rf69_clear_bit(spi, REG_SYNC_CONFIG, MASK_SYNC_CONFIG_SYNC_ON);
|
||||
}
|
||||
|
||||
int rf69_set_fifo_fill_condition(struct spi_device *spi,
|
||||
enum fifo_fill_condition fifo_fill_condition)
|
||||
{
|
||||
switch (fifo_fill_condition) {
|
||||
case always:
|
||||
return rf69_set_bit(spi, REG_SYNC_CONFIG,
|
||||
MASK_SYNC_CONFIG_FIFO_FILL_CONDITION);
|
||||
case after_sync_interrupt:
|
||||
return rf69_clear_bit(spi, REG_SYNC_CONFIG,
|
||||
MASK_SYNC_CONFIG_FIFO_FILL_CONDITION);
|
||||
default:
|
||||
dev_dbg(&spi->dev, "set: illegal fifo fill condition %u\n", fifo_fill_condition);
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
int rf69_set_sync_size(struct spi_device *spi, u8 sync_size)
|
||||
{
|
||||
// check input value
|
||||
if (sync_size > 0x07) {
|
||||
dev_dbg(&spi->dev, "set: illegal sync size %u\n", sync_size);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
// write value
|
||||
return rf69_read_mod_write(spi, REG_SYNC_CONFIG,
|
||||
MASK_SYNC_CONFIG_SYNC_SIZE,
|
||||
(sync_size << 3));
|
||||
}
|
||||
|
||||
int rf69_set_sync_values(struct spi_device *spi, u8 sync_values[8])
|
||||
{
|
||||
int retval = 0;
|
||||
|
||||
retval += rf69_write_reg(spi, REG_SYNCVALUE1, sync_values[0]);
|
||||
retval += rf69_write_reg(spi, REG_SYNCVALUE2, sync_values[1]);
|
||||
retval += rf69_write_reg(spi, REG_SYNCVALUE3, sync_values[2]);
|
||||
retval += rf69_write_reg(spi, REG_SYNCVALUE4, sync_values[3]);
|
||||
retval += rf69_write_reg(spi, REG_SYNCVALUE5, sync_values[4]);
|
||||
retval += rf69_write_reg(spi, REG_SYNCVALUE6, sync_values[5]);
|
||||
retval += rf69_write_reg(spi, REG_SYNCVALUE7, sync_values[6]);
|
||||
retval += rf69_write_reg(spi, REG_SYNCVALUE8, sync_values[7]);
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
int rf69_set_packet_format(struct spi_device *spi,
|
||||
enum packet_format packet_format)
|
||||
{
|
||||
switch (packet_format) {
|
||||
case packet_length_var:
|
||||
return rf69_set_bit(spi, REG_PACKETCONFIG1,
|
||||
MASK_PACKETCONFIG1_PACKET_FORMAT_VARIABLE);
|
||||
case packet_length_fix:
|
||||
return rf69_clear_bit(spi, REG_PACKETCONFIG1,
|
||||
MASK_PACKETCONFIG1_PACKET_FORMAT_VARIABLE);
|
||||
default:
|
||||
dev_dbg(&spi->dev, "set: illegal packet format %u\n", packet_format);
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
int rf69_enable_crc(struct spi_device *spi)
|
||||
{
|
||||
return rf69_set_bit(spi, REG_PACKETCONFIG1, MASK_PACKETCONFIG1_CRC_ON);
|
||||
}
|
||||
|
||||
int rf69_disable_crc(struct spi_device *spi)
|
||||
{
|
||||
return rf69_clear_bit(spi, REG_PACKETCONFIG1, MASK_PACKETCONFIG1_CRC_ON);
|
||||
}
|
||||
|
||||
int rf69_set_address_filtering(struct spi_device *spi,
|
||||
enum address_filtering address_filtering)
|
||||
{
|
||||
static const u8 af_map[] = {
|
||||
[filtering_off] = PACKETCONFIG1_ADDRESSFILTERING_OFF,
|
||||
[node_address] = PACKETCONFIG1_ADDRESSFILTERING_NODE,
|
||||
[node_or_broadcast_address] =
|
||||
PACKETCONFIG1_ADDRESSFILTERING_NODEBROADCAST,
|
||||
};
|
||||
|
||||
if (unlikely(address_filtering >= ARRAY_SIZE(af_map))) {
|
||||
dev_dbg(&spi->dev, "set: illegal address filtering %u\n", address_filtering);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return rf69_read_mod_write(spi, REG_PACKETCONFIG1,
|
||||
MASK_PACKETCONFIG1_ADDRESSFILTERING,
|
||||
af_map[address_filtering]);
|
||||
}
|
||||
|
||||
int rf69_set_payload_length(struct spi_device *spi, u8 payload_length)
|
||||
{
|
||||
return rf69_write_reg(spi, REG_PAYLOAD_LENGTH, payload_length);
|
||||
}
|
||||
|
||||
int rf69_set_node_address(struct spi_device *spi, u8 node_address)
|
||||
{
|
||||
return rf69_write_reg(spi, REG_NODEADRS, node_address);
|
||||
}
|
||||
|
||||
int rf69_set_broadcast_address(struct spi_device *spi, u8 broadcast_address)
|
||||
{
|
||||
return rf69_write_reg(spi, REG_BROADCASTADRS, broadcast_address);
|
||||
}
|
||||
|
||||
int rf69_set_tx_start_condition(struct spi_device *spi,
|
||||
enum tx_start_condition tx_start_condition)
|
||||
{
|
||||
switch (tx_start_condition) {
|
||||
case fifo_level:
|
||||
return rf69_clear_bit(spi, REG_FIFO_THRESH,
|
||||
MASK_FIFO_THRESH_TXSTART);
|
||||
case fifo_not_empty:
|
||||
return rf69_set_bit(spi, REG_FIFO_THRESH,
|
||||
MASK_FIFO_THRESH_TXSTART);
|
||||
default:
|
||||
dev_dbg(&spi->dev, "set: illegal tx start condition %u\n", tx_start_condition);
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
int rf69_set_fifo_threshold(struct spi_device *spi, u8 threshold)
|
||||
{
|
||||
int retval;
|
||||
|
||||
/* check input value */
|
||||
if (threshold & ~MASK_FIFO_THRESH_VALUE) {
|
||||
dev_dbg(&spi->dev, "set: illegal fifo threshold %u\n", threshold);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* write value */
|
||||
retval = rf69_read_mod_write(spi, REG_FIFO_THRESH,
|
||||
MASK_FIFO_THRESH_VALUE,
|
||||
threshold);
|
||||
if (retval)
|
||||
return retval;
|
||||
|
||||
/*
|
||||
* access the fifo to activate new threshold
|
||||
* retval (mis-) used as buffer here
|
||||
*/
|
||||
return rf69_read_fifo(spi, (u8 *)&retval, 1);
|
||||
}
|
||||
|
||||
int rf69_set_dagc(struct spi_device *spi, enum dagc dagc)
|
||||
{
|
||||
static const u8 dagc_map[] = {
|
||||
[normal_mode] = DAGC_NORMAL,
|
||||
[improve] = DAGC_IMPROVED_LOWBETA0,
|
||||
[improve_for_low_modulation_index] = DAGC_IMPROVED_LOWBETA1,
|
||||
};
|
||||
|
||||
if (unlikely(dagc >= ARRAY_SIZE(dagc_map))) {
|
||||
dev_dbg(&spi->dev, "set: illegal dagc %u\n", dagc);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return rf69_write_reg(spi, REG_TESTDAGC, dagc_map[dagc]);
|
||||
}
|
||||
|
||||
/*-------------------------------------------------------------------------*/
|
||||
|
||||
int rf69_read_fifo(struct spi_device *spi, u8 *buffer, unsigned int size)
|
||||
{
|
||||
int i;
|
||||
struct spi_transfer transfer;
|
||||
u8 local_buffer[FIFO_SIZE + 1] = {};
|
||||
int retval;
|
||||
|
||||
if (size > FIFO_SIZE) {
|
||||
dev_dbg(&spi->dev,
|
||||
"read fifo: passed in buffer bigger then internal buffer\n");
|
||||
return -EMSGSIZE;
|
||||
}
|
||||
|
||||
/* prepare a bidirectional transfer */
|
||||
local_buffer[0] = REG_FIFO;
|
||||
memset(&transfer, 0, sizeof(transfer));
|
||||
transfer.tx_buf = local_buffer;
|
||||
transfer.rx_buf = local_buffer;
|
||||
transfer.len = size + 1;
|
||||
|
||||
retval = spi_sync_transfer(spi, &transfer, 1);
|
||||
|
||||
/* print content read from fifo for debugging purposes */
|
||||
for (i = 0; i < size; i++)
|
||||
dev_dbg(&spi->dev, "%d - 0x%x\n", i, local_buffer[i + 1]);
|
||||
|
||||
memcpy(buffer, &local_buffer[1], size);
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
int rf69_write_fifo(struct spi_device *spi, u8 *buffer, unsigned int size)
|
||||
{
|
||||
int i;
|
||||
u8 local_buffer[FIFO_SIZE + 1];
|
||||
|
||||
if (size > FIFO_SIZE) {
|
||||
dev_dbg(&spi->dev,
|
||||
"write fifo: passed in buffer bigger then internal buffer\n");
|
||||
return -EMSGSIZE;
|
||||
}
|
||||
|
||||
local_buffer[0] = REG_FIFO | WRITE_BIT;
|
||||
memcpy(&local_buffer[1], buffer, size);
|
||||
|
||||
/* print content written from fifo for debugging purposes */
|
||||
for (i = 0; i < size; i++)
|
||||
dev_dbg(&spi->dev, "%d - 0x%x\n", i, buffer[i]);
|
||||
|
||||
return spi_write(spi, local_buffer, size + 1);
|
||||
}
|
||||
|
||||
@ -1,66 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* hardware abstraction/register access for HopeRf rf69 radio module
|
||||
*
|
||||
* Copyright (C) 2016 Wolf-Entwicklungen
|
||||
* Marcus Wolf <linux@wolf-entwicklungen.de>
|
||||
*/
|
||||
#ifndef RF69_H
|
||||
#define RF69_H
|
||||
|
||||
#include "rf69_enum.h"
|
||||
#include "rf69_registers.h"
|
||||
|
||||
#define FIFO_SIZE 66 /* bytes */
|
||||
|
||||
u8 rf69_read_reg(struct spi_device *spi, u8 addr);
|
||||
int rf69_get_version(struct spi_device *spi);
|
||||
int rf69_set_mode(struct spi_device *spi, enum mode mode);
|
||||
int rf69_set_data_mode(struct spi_device *spi, u8 data_mode);
|
||||
int rf69_set_modulation(struct spi_device *spi, enum modulation modulation);
|
||||
int rf69_set_modulation_shaping(struct spi_device *spi,
|
||||
enum mod_shaping mod_shaping);
|
||||
int rf69_set_bit_rate(struct spi_device *spi, u16 bit_rate);
|
||||
int rf69_set_deviation(struct spi_device *spi, u32 deviation);
|
||||
int rf69_set_frequency(struct spi_device *spi, u32 frequency);
|
||||
int rf69_enable_amplifier(struct spi_device *spi, u8 amplifier_mask);
|
||||
int rf69_disable_amplifier(struct spi_device *spi, u8 amplifier_mask);
|
||||
int rf69_set_output_power_level(struct spi_device *spi, u8 power_level);
|
||||
int rf69_set_pa_ramp(struct spi_device *spi, enum pa_ramp pa_ramp);
|
||||
int rf69_set_antenna_impedance(struct spi_device *spi,
|
||||
enum antenna_impedance antenna_impedance);
|
||||
int rf69_set_lna_gain(struct spi_device *spi, enum lna_gain lna_gain);
|
||||
int rf69_set_bandwidth(struct spi_device *spi, enum mantisse mantisse,
|
||||
u8 exponent);
|
||||
int rf69_set_bandwidth_during_afc(struct spi_device *spi,
|
||||
enum mantisse mantisse,
|
||||
u8 exponent);
|
||||
int rf69_set_ook_threshold_dec(struct spi_device *spi,
|
||||
enum threshold_decrement threshold_decrement);
|
||||
int rf69_set_dio_mapping(struct spi_device *spi, u8 dio_number, u8 value);
|
||||
int rf69_set_rssi_threshold(struct spi_device *spi, u8 threshold);
|
||||
int rf69_set_preamble_length(struct spi_device *spi, u16 preamble_length);
|
||||
int rf69_enable_sync(struct spi_device *spi);
|
||||
int rf69_disable_sync(struct spi_device *spi);
|
||||
int rf69_set_fifo_fill_condition(struct spi_device *spi,
|
||||
enum fifo_fill_condition fifo_fill_condition);
|
||||
int rf69_set_sync_size(struct spi_device *spi, u8 sync_size);
|
||||
int rf69_set_sync_values(struct spi_device *spi, u8 sync_values[8]);
|
||||
int rf69_set_packet_format(struct spi_device *spi,
|
||||
enum packet_format packet_format);
|
||||
int rf69_enable_crc(struct spi_device *spi);
|
||||
int rf69_disable_crc(struct spi_device *spi);
|
||||
int rf69_set_address_filtering(struct spi_device *spi,
|
||||
enum address_filtering address_filtering);
|
||||
int rf69_set_payload_length(struct spi_device *spi, u8 payload_length);
|
||||
int rf69_set_node_address(struct spi_device *spi, u8 node_address);
|
||||
int rf69_set_broadcast_address(struct spi_device *spi, u8 broadcast_address);
|
||||
int rf69_set_tx_start_condition(struct spi_device *spi,
|
||||
enum tx_start_condition tx_start_condition);
|
||||
int rf69_set_fifo_threshold(struct spi_device *spi, u8 threshold);
|
||||
int rf69_set_dagc(struct spi_device *spi, enum dagc dagc);
|
||||
|
||||
int rf69_read_fifo(struct spi_device *spi, u8 *buffer, unsigned int size);
|
||||
int rf69_write_fifo(struct spi_device *spi, u8 *buffer, unsigned int size);
|
||||
|
||||
#endif
|
||||
@ -1,126 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* enumerations for HopeRf rf69 radio module
|
||||
*
|
||||
* Copyright (C) 2016 Wolf-Entwicklungen
|
||||
* Marcus Wolf <linux@wolf-entwicklungen.de>
|
||||
*/
|
||||
|
||||
#ifndef RF69_ENUM_H
|
||||
#define RF69_ENUM_H
|
||||
|
||||
enum mode {
|
||||
mode_sleep,
|
||||
standby,
|
||||
synthesizer,
|
||||
transmit,
|
||||
receive
|
||||
};
|
||||
|
||||
enum modulation {
|
||||
OOK,
|
||||
FSK,
|
||||
UNDEF
|
||||
};
|
||||
|
||||
enum mod_shaping {
|
||||
SHAPING_OFF,
|
||||
SHAPING_1_0,
|
||||
SHAPING_0_5,
|
||||
SHAPING_0_3,
|
||||
SHAPING_BR,
|
||||
SHAPING_2BR
|
||||
};
|
||||
|
||||
enum pa_ramp {
|
||||
ramp3400,
|
||||
ramp2000,
|
||||
ramp1000,
|
||||
ramp500,
|
||||
ramp250,
|
||||
ramp125,
|
||||
ramp100,
|
||||
ramp62,
|
||||
ramp50,
|
||||
ramp40,
|
||||
ramp31,
|
||||
ramp25,
|
||||
ramp20,
|
||||
ramp15,
|
||||
ramp12,
|
||||
ramp10
|
||||
};
|
||||
|
||||
enum antenna_impedance {
|
||||
fifty_ohm,
|
||||
two_hundred_ohm
|
||||
};
|
||||
|
||||
enum lna_gain {
|
||||
automatic,
|
||||
max,
|
||||
max_minus_6,
|
||||
max_minus_12,
|
||||
max_minus_24,
|
||||
max_minus_36,
|
||||
max_minus_48,
|
||||
undefined
|
||||
};
|
||||
|
||||
enum mantisse {
|
||||
mantisse16,
|
||||
mantisse20,
|
||||
mantisse24
|
||||
};
|
||||
|
||||
enum threshold_decrement {
|
||||
dec_every8th,
|
||||
dec_every4th,
|
||||
dec_every2nd,
|
||||
dec_once,
|
||||
dec_twice,
|
||||
dec_4times,
|
||||
dec_8times,
|
||||
dec_16times
|
||||
};
|
||||
|
||||
enum fifo_fill_condition {
|
||||
after_sync_interrupt,
|
||||
always
|
||||
};
|
||||
|
||||
enum packet_format {
|
||||
/*
|
||||
* Used when the size of payload is fixed in advance. This mode of
|
||||
* operation may be of interest to minimize RF overhead by 1 byte as
|
||||
* no length byte field is required
|
||||
*/
|
||||
packet_length_fix,
|
||||
/*
|
||||
* Used when the size of payload isn't known in advance. It requires the
|
||||
* transmitter to send the length byte in each packet so the receiver
|
||||
* would know how to operate properly
|
||||
*/
|
||||
packet_length_var
|
||||
};
|
||||
|
||||
enum tx_start_condition {
|
||||
/* the number of bytes in the FIFO exceeds FIFO_THRESHOLD */
|
||||
fifo_level,
|
||||
/* at least one byte in the FIFO */
|
||||
fifo_not_empty
|
||||
};
|
||||
|
||||
enum address_filtering {
|
||||
filtering_off,
|
||||
node_address,
|
||||
node_or_broadcast_address
|
||||
};
|
||||
|
||||
enum dagc {
|
||||
normal_mode,
|
||||
improve,
|
||||
improve_for_low_modulation_index
|
||||
};
|
||||
|
||||
#endif
|
||||
@ -1,478 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* register description for HopeRf rf69 radio module
|
||||
*
|
||||
* Copyright (C) 2016 Wolf-Entwicklungen
|
||||
* Marcus Wolf <linux@wolf-entwicklungen.de>
|
||||
*/
|
||||
|
||||
/*******************************************/
|
||||
/* RF69 register addresses */
|
||||
/*******************************************/
|
||||
#define REG_FIFO 0x00
|
||||
#define REG_OPMODE 0x01
|
||||
#define REG_DATAMODUL 0x02
|
||||
#define REG_BITRATE_MSB 0x03
|
||||
#define REG_BITRATE_LSB 0x04
|
||||
#define REG_FDEV_MSB 0x05
|
||||
#define REG_FDEV_LSB 0x06
|
||||
#define REG_FRF_MSB 0x07
|
||||
#define REG_FRF_MID 0x08
|
||||
#define REG_FRF_LSB 0x09
|
||||
#define REG_OSC1 0x0A
|
||||
#define REG_AFCCTRL 0x0B
|
||||
#define REG_LOWBAT 0x0C
|
||||
#define REG_LISTEN1 0x0D
|
||||
#define REG_LISTEN2 0x0E
|
||||
#define REG_LISTEN3 0x0F
|
||||
#define REG_VERSION 0x10
|
||||
#define REG_PALEVEL 0x11
|
||||
#define REG_PARAMP 0x12
|
||||
#define REG_OCP 0x13
|
||||
#define REG_AGCREF 0x14 /* not available on RF69 */
|
||||
#define REG_AGCTHRESH1 0x15 /* not available on RF69 */
|
||||
#define REG_AGCTHRESH2 0x16 /* not available on RF69 */
|
||||
#define REG_AGCTHRESH3 0x17 /* not available on RF69 */
|
||||
#define REG_LNA 0x18
|
||||
#define REG_RXBW 0x19
|
||||
#define REG_AFCBW 0x1A
|
||||
#define REG_OOKPEAK 0x1B
|
||||
#define REG_OOKAVG 0x1C
|
||||
#define REG_OOKFIX 0x1D
|
||||
#define REG_AFCFEI 0x1E
|
||||
#define REG_AFCMSB 0x1F
|
||||
#define REG_AFCLSB 0x20
|
||||
#define REG_FEIMSB 0x21
|
||||
#define REG_FEILSB 0x22
|
||||
#define REG_RSSICONFIG 0x23
|
||||
#define REG_RSSIVALUE 0x24
|
||||
#define REG_DIOMAPPING1 0x25
|
||||
#define REG_DIOMAPPING2 0x26
|
||||
#define REG_IRQFLAGS1 0x27
|
||||
#define REG_IRQFLAGS2 0x28
|
||||
#define REG_RSSITHRESH 0x29
|
||||
#define REG_RXTIMEOUT1 0x2A
|
||||
#define REG_RXTIMEOUT2 0x2B
|
||||
#define REG_PREAMBLE_MSB 0x2C
|
||||
#define REG_PREAMBLE_LSB 0x2D
|
||||
#define REG_SYNC_CONFIG 0x2E
|
||||
#define REG_SYNCVALUE1 0x2F
|
||||
#define REG_SYNCVALUE2 0x30
|
||||
#define REG_SYNCVALUE3 0x31
|
||||
#define REG_SYNCVALUE4 0x32
|
||||
#define REG_SYNCVALUE5 0x33
|
||||
#define REG_SYNCVALUE6 0x34
|
||||
#define REG_SYNCVALUE7 0x35
|
||||
#define REG_SYNCVALUE8 0x36
|
||||
#define REG_PACKETCONFIG1 0x37
|
||||
#define REG_PAYLOAD_LENGTH 0x38
|
||||
#define REG_NODEADRS 0x39
|
||||
#define REG_BROADCASTADRS 0x3A
|
||||
#define REG_AUTOMODES 0x3B
|
||||
#define REG_FIFO_THRESH 0x3C
|
||||
#define REG_PACKETCONFIG2 0x3D
|
||||
#define REG_AESKEY1 0x3E
|
||||
#define REG_AESKEY2 0x3F
|
||||
#define REG_AESKEY3 0x40
|
||||
#define REG_AESKEY4 0x41
|
||||
#define REG_AESKEY5 0x42
|
||||
#define REG_AESKEY6 0x43
|
||||
#define REG_AESKEY7 0x44
|
||||
#define REG_AESKEY8 0x45
|
||||
#define REG_AESKEY9 0x46
|
||||
#define REG_AESKEY10 0x47
|
||||
#define REG_AESKEY11 0x48
|
||||
#define REG_AESKEY12 0x49
|
||||
#define REG_AESKEY13 0x4A
|
||||
#define REG_AESKEY14 0x4B
|
||||
#define REG_AESKEY15 0x4C
|
||||
#define REG_AESKEY16 0x4D
|
||||
#define REG_TEMP1 0x4E
|
||||
#define REG_TEMP2 0x4F
|
||||
#define REG_TESTLNA 0x58
|
||||
#define REG_TESTPA1 0x5A /* only present on RFM69HW */
|
||||
#define REG_TESTPA2 0x5C /* only present on RFM69HW */
|
||||
#define REG_TESTDAGC 0x6F
|
||||
#define REG_TESTAFC 0x71
|
||||
|
||||
/******************************************************/
|
||||
/* RF69/SX1231 bit definition */
|
||||
/******************************************************/
|
||||
/* write bit */
|
||||
#define WRITE_BIT 0x80
|
||||
|
||||
/* RegOpMode */
|
||||
#define MASK_OPMODE_SEQUENCER_OFF 0x80
|
||||
#define MASK_OPMODE_LISTEN_ON 0x40
|
||||
#define MASK_OPMODE_LISTEN_ABORT 0x20
|
||||
#define MASK_OPMODE_MODE 0x1C
|
||||
|
||||
#define OPMODE_MODE_SLEEP 0x00
|
||||
#define OPMODE_MODE_STANDBY 0x04 /* default */
|
||||
#define OPMODE_MODE_SYNTHESIZER 0x08
|
||||
#define OPMODE_MODE_TRANSMIT 0x0C
|
||||
#define OPMODE_MODE_RECEIVE 0x10
|
||||
|
||||
/* RegDataModul */
|
||||
#define MASK_DATAMODUL_MODE 0x06
|
||||
#define MASK_DATAMODUL_MODULATION_TYPE 0x18
|
||||
#define MASK_DATAMODUL_MODULATION_SHAPE 0x03
|
||||
|
||||
#define DATAMODUL_MODE_PACKET 0x00 /* default */
|
||||
#define DATAMODUL_MODE_CONTINUOUS 0x40
|
||||
#define DATAMODUL_MODE_CONTINUOUS_NOSYNC 0x60
|
||||
|
||||
#define DATAMODUL_MODULATION_TYPE_FSK 0x00 /* default */
|
||||
#define DATAMODUL_MODULATION_TYPE_OOK 0x08
|
||||
|
||||
#define DATAMODUL_MODULATION_SHAPE_NONE 0x00 /* default */
|
||||
#define DATAMODUL_MODULATION_SHAPE_1_0 0x01
|
||||
#define DATAMODUL_MODULATION_SHAPE_0_5 0x02
|
||||
#define DATAMODUL_MODULATION_SHAPE_0_3 0x03
|
||||
#define DATAMODUL_MODULATION_SHAPE_BR 0x01
|
||||
#define DATAMODUL_MODULATION_SHAPE_2BR 0x02
|
||||
|
||||
/* RegFDevMsb (0x05)*/
|
||||
#define FDEVMASB_MASK 0x3f
|
||||
|
||||
/*
|
||||
* // RegOsc1
|
||||
* #define OSC1_RCCAL_START 0x80
|
||||
* #define OSC1_RCCAL_DONE 0x40
|
||||
*
|
||||
* // RegLowBat
|
||||
* #define LOWBAT_MONITOR 0x10
|
||||
* #define LOWBAT_ON 0x08
|
||||
* #define LOWBAT_OFF 0x00 // Default
|
||||
*
|
||||
* #define LOWBAT_TRIM_1695 0x00
|
||||
* #define LOWBAT_TRIM_1764 0x01
|
||||
* #define LOWBAT_TRIM_1835 0x02 // Default
|
||||
* #define LOWBAT_TRIM_1905 0x03
|
||||
* #define LOWBAT_TRIM_1976 0x04
|
||||
* #define LOWBAT_TRIM_2045 0x05
|
||||
* #define LOWBAT_TRIM_2116 0x06
|
||||
* #define LOWBAT_TRIM_2185 0x07
|
||||
*
|
||||
*
|
||||
* // RegListen1
|
||||
* #define LISTEN1_RESOL_64 0x50
|
||||
* #define LISTEN1_RESOL_4100 0xA0 // Default
|
||||
* #define LISTEN1_RESOL_262000 0xF0
|
||||
*
|
||||
* #define LISTEN1_CRITERIA_RSSI 0x00 // Default
|
||||
* #define LISTEN1_CRITERIA_RSSIANDSYNC 0x08
|
||||
*
|
||||
* #define LISTEN1_END_00 0x00
|
||||
* #define LISTEN1_END_01 0x02 // Default
|
||||
* #define LISTEN1_END_10 0x04
|
||||
*
|
||||
*
|
||||
* // RegListen2
|
||||
* #define LISTEN2_COEFIDLE_VALUE 0xF5 // Default
|
||||
*
|
||||
* // RegListen3
|
||||
* #define LISTEN3_COEFRX_VALUE 0x20 // Default
|
||||
*/
|
||||
|
||||
// RegPaLevel
|
||||
#define MASK_PALEVEL_PA0 0x80
|
||||
#define MASK_PALEVEL_PA1 0x40
|
||||
#define MASK_PALEVEL_PA2 0x20
|
||||
#define MASK_PALEVEL_OUTPUT_POWER 0x1F
|
||||
|
||||
// RegPaRamp
|
||||
#define PARAMP_3400 0x00
|
||||
#define PARAMP_2000 0x01
|
||||
#define PARAMP_1000 0x02
|
||||
#define PARAMP_500 0x03
|
||||
#define PARAMP_250 0x04
|
||||
#define PARAMP_125 0x05
|
||||
#define PARAMP_100 0x06
|
||||
#define PARAMP_62 0x07
|
||||
#define PARAMP_50 0x08
|
||||
#define PARAMP_40 0x09 /* default */
|
||||
#define PARAMP_31 0x0A
|
||||
#define PARAMP_25 0x0B
|
||||
#define PARAMP_20 0x0C
|
||||
#define PARAMP_15 0x0D
|
||||
#define PARAMP_12 0x0E
|
||||
#define PARAMP_10 0x0F
|
||||
|
||||
#define MASK_PARAMP 0x0F
|
||||
|
||||
/*
|
||||
* // RegOcp
|
||||
* #define OCP_OFF 0x0F
|
||||
* #define OCP_ON 0x1A // Default
|
||||
*
|
||||
* #define OCP_TRIM_45 0x00
|
||||
* #define OCP_TRIM_50 0x01
|
||||
* #define OCP_TRIM_55 0x02
|
||||
* #define OCP_TRIM_60 0x03
|
||||
* #define OCP_TRIM_65 0x04
|
||||
* #define OCP_TRIM_70 0x05
|
||||
* #define OCP_TRIM_75 0x06
|
||||
* #define OCP_TRIM_80 0x07
|
||||
* #define OCP_TRIM_85 0x08
|
||||
* #define OCP_TRIM_90 0x09
|
||||
* #define OCP_TRIM_95 0x0A
|
||||
* #define OCP_TRIM_100 0x0B // Default
|
||||
* #define OCP_TRIM_105 0x0C
|
||||
* #define OCP_TRIM_110 0x0D
|
||||
* #define OCP_TRIM_115 0x0E
|
||||
* #define OCP_TRIM_120 0x0F
|
||||
*/
|
||||
|
||||
/* RegLna (0x18) */
|
||||
#define MASK_LNA_ZIN 0x80
|
||||
#define MASK_LNA_CURRENT_GAIN 0x38
|
||||
#define MASK_LNA_GAIN 0x07
|
||||
|
||||
#define LNA_GAIN_AUTO 0x00 /* default */
|
||||
#define LNA_GAIN_MAX 0x01
|
||||
#define LNA_GAIN_MAX_MINUS_6 0x02
|
||||
#define LNA_GAIN_MAX_MINUS_12 0x03
|
||||
#define LNA_GAIN_MAX_MINUS_24 0x04
|
||||
#define LNA_GAIN_MAX_MINUS_36 0x05
|
||||
#define LNA_GAIN_MAX_MINUS_48 0x06
|
||||
|
||||
/* RegRxBw (0x19) and RegAfcBw (0x1A) */
|
||||
#define MASK_BW_DCC_FREQ 0xE0
|
||||
#define MASK_BW_MANTISSE 0x18
|
||||
#define MASK_BW_EXPONENT 0x07
|
||||
|
||||
#define BW_DCC_16_PERCENT 0x00
|
||||
#define BW_DCC_8_PERCENT 0x20
|
||||
#define BW_DCC_4_PERCENT 0x40 /* default */
|
||||
#define BW_DCC_2_PERCENT 0x60
|
||||
#define BW_DCC_1_PERCENT 0x80
|
||||
#define BW_DCC_0_5_PERCENT 0xA0
|
||||
#define BW_DCC_0_25_PERCENT 0xC0
|
||||
#define BW_DCC_0_125_PERCENT 0xE0
|
||||
|
||||
#define BW_MANT_16 0x00
|
||||
#define BW_MANT_20 0x08
|
||||
#define BW_MANT_24 0x10 /* default */
|
||||
|
||||
/* RegOokPeak (0x1B) */
|
||||
#define MASK_OOKPEAK_THRESTYPE 0xc0
|
||||
#define MASK_OOKPEAK_THRESSTEP 0x38
|
||||
#define MASK_OOKPEAK_THRESDEC 0x07
|
||||
|
||||
#define OOKPEAK_THRESHTYPE_FIXED 0x00
|
||||
#define OOKPEAK_THRESHTYPE_PEAK 0x40 /* default */
|
||||
#define OOKPEAK_THRESHTYPE_AVERAGE 0x80
|
||||
|
||||
#define OOKPEAK_THRESHSTEP_0_5_DB 0x00 /* default */
|
||||
#define OOKPEAK_THRESHSTEP_1_0_DB 0x08
|
||||
#define OOKPEAK_THRESHSTEP_1_5_DB 0x10
|
||||
#define OOKPEAK_THRESHSTEP_2_0_DB 0x18
|
||||
#define OOKPEAK_THRESHSTEP_3_0_DB 0x20
|
||||
#define OOKPEAK_THRESHSTEP_4_0_DB 0x28
|
||||
#define OOKPEAK_THRESHSTEP_5_0_DB 0x30
|
||||
#define OOKPEAK_THRESHSTEP_6_0_DB 0x38
|
||||
|
||||
#define OOKPEAK_THRESHDEC_ONCE 0x00 /* default */
|
||||
#define OOKPEAK_THRESHDEC_EVERY_2ND 0x01
|
||||
#define OOKPEAK_THRESHDEC_EVERY_4TH 0x02
|
||||
#define OOKPEAK_THRESHDEC_EVERY_8TH 0x03
|
||||
#define OOKPEAK_THRESHDEC_TWICE 0x04
|
||||
#define OOKPEAK_THRESHDEC_4_TIMES 0x05
|
||||
#define OOKPEAK_THRESHDEC_8_TIMES 0x06
|
||||
#define OOKPEAK_THRESHDEC_16_TIMES 0x07
|
||||
|
||||
/*
|
||||
* // RegOokAvg
|
||||
* #define OOKAVG_AVERAGETHRESHFILT_00 0x00
|
||||
* #define OOKAVG_AVERAGETHRESHFILT_01 0x40
|
||||
* #define OOKAVG_AVERAGETHRESHFILT_10 0x80 // Default
|
||||
* #define OOKAVG_AVERAGETHRESHFILT_11 0xC0
|
||||
*
|
||||
*
|
||||
* // RegAfcFei
|
||||
* #define AFCFEI_FEI_DONE 0x40
|
||||
* #define AFCFEI_FEI_START 0x20
|
||||
* #define AFCFEI_AFC_DONE 0x10
|
||||
* #define AFCFEI_AFCAUTOCLEAR_ON 0x08
|
||||
* #define AFCFEI_AFCAUTOCLEAR_OFF 0x00 // Default
|
||||
*
|
||||
* #define AFCFEI_AFCAUTO_ON 0x04
|
||||
* #define AFCFEI_AFCAUTO_OFF 0x00 // Default
|
||||
*
|
||||
* #define AFCFEI_AFC_CLEAR 0x02
|
||||
* #define AFCFEI_AFC_START 0x01
|
||||
*
|
||||
* // RegRssiConfig
|
||||
* #define RSSI_FASTRX_ON 0x08
|
||||
* #define RSSI_FASTRX_OFF 0x00 // Default
|
||||
* #define RSSI_DONE 0x02
|
||||
* #define RSSI_START 0x01
|
||||
*/
|
||||
|
||||
/* RegDioMapping1 */
|
||||
#define MASK_DIO0 0xC0
|
||||
#define MASK_DIO1 0x30
|
||||
#define MASK_DIO2 0x0C
|
||||
#define MASK_DIO3 0x03
|
||||
#define SHIFT_DIO0 6
|
||||
#define SHIFT_DIO1 4
|
||||
#define SHIFT_DIO2 2
|
||||
#define SHIFT_DIO3 0
|
||||
|
||||
/* RegDioMapping2 */
|
||||
#define MASK_DIO4 0xC0
|
||||
#define MASK_DIO5 0x30
|
||||
#define SHIFT_DIO4 6
|
||||
#define SHIFT_DIO5 4
|
||||
|
||||
/* DIO numbers */
|
||||
#define DIO0 0
|
||||
#define DIO1 1
|
||||
#define DIO2 2
|
||||
#define DIO3 3
|
||||
#define DIO4 4
|
||||
#define DIO5 5
|
||||
|
||||
/* DIO Mapping values (packet mode) */
|
||||
#define DIO_MODE_READY_DIO4 0x00
|
||||
#define DIO_MODE_READY_DIO5 0x03
|
||||
#define DIO_CLK_OUT 0x00
|
||||
#define DIO_DATA 0x01
|
||||
#define DIO_TIMEOUT_DIO1 0x03
|
||||
#define DIO_TIMEOUT_DIO4 0x00
|
||||
#define DIO_RSSI_DIO0 0x03
|
||||
#define DIO_RSSI_DIO3_4 0x01
|
||||
#define DIO_RX_READY 0x02
|
||||
#define DIO_PLL_LOCK 0x03
|
||||
#define DIO_TX_READY 0x01
|
||||
#define DIO_FIFO_FULL_DIO1 0x01
|
||||
#define DIO_FIFO_FULL_DIO3 0x00
|
||||
#define DIO_SYNC_ADDRESS 0x02
|
||||
#define DIO_FIFO_NOT_EMPTY_DIO1 0x02
|
||||
#define DIO_FIFO_NOT_EMPTY_FIO2 0x00
|
||||
#define DIO_AUTOMODE 0x04
|
||||
#define DIO_FIFO_LEVEL 0x00
|
||||
#define DIO_CRC_OK 0x00
|
||||
#define DIO_PAYLOAD_READY 0x01
|
||||
#define DIO_PACKET_SENT 0x00
|
||||
#define DIO_DCLK 0x00
|
||||
|
||||
/* RegDioMapping2 CLK_OUT part */
|
||||
#define MASK_DIOMAPPING2_CLK_OUT 0x07
|
||||
|
||||
#define DIOMAPPING2_CLK_OUT_NO_DIV 0x00
|
||||
#define DIOMAPPING2_CLK_OUT_DIV_2 0x01
|
||||
#define DIOMAPPING2_CLK_OUT_DIV_4 0x02
|
||||
#define DIOMAPPING2_CLK_OUT_DIV_8 0x03
|
||||
#define DIOMAPPING2_CLK_OUT_DIV_16 0x04
|
||||
#define DIOMAPPING2_CLK_OUT_DIV_32 0x05
|
||||
#define DIOMAPPING2_CLK_OUT_RC 0x06
|
||||
#define DIOMAPPING2_CLK_OUT_OFF 0x07 /* default */
|
||||
|
||||
/* RegIrqFlags1 */
|
||||
#define MASK_IRQFLAGS1_MODE_READY 0x80
|
||||
#define MASK_IRQFLAGS1_RX_READY 0x40
|
||||
#define MASK_IRQFLAGS1_TX_READY 0x20
|
||||
#define MASK_IRQFLAGS1_PLL_LOCK 0x10
|
||||
#define MASK_IRQFLAGS1_RSSI 0x08
|
||||
#define MASK_IRQFLAGS1_TIMEOUT 0x04
|
||||
#define MASK_IRQFLAGS1_AUTOMODE 0x02
|
||||
#define MASK_IRQFLAGS1_SYNC_ADDRESS_MATCH 0x01
|
||||
|
||||
/* RegIrqFlags2 */
|
||||
#define MASK_IRQFLAGS2_FIFO_FULL 0x80
|
||||
#define MASK_IRQFLAGS2_FIFO_NOT_EMPTY 0x40
|
||||
#define MASK_IRQFLAGS2_FIFO_LEVEL 0x20
|
||||
#define MASK_IRQFLAGS2_FIFO_OVERRUN 0x10
|
||||
#define MASK_IRQFLAGS2_PACKET_SENT 0x08
|
||||
#define MASK_IRQFLAGS2_PAYLOAD_READY 0x04
|
||||
#define MASK_IRQFLAGS2_CRC_OK 0x02
|
||||
#define MASK_IRQFLAGS2_LOW_BAT 0x01
|
||||
|
||||
/* RegSyncConfig */
|
||||
#define MASK_SYNC_CONFIG_SYNC_ON 0x80 /* default */
|
||||
#define MASK_SYNC_CONFIG_FIFO_FILL_CONDITION 0x40
|
||||
#define MASK_SYNC_CONFIG_SYNC_SIZE 0x38
|
||||
#define MASK_SYNC_CONFIG_SYNC_TOLERANCE 0x07
|
||||
|
||||
/* RegPacketConfig1 */
|
||||
#define MASK_PACKETCONFIG1_PACKET_FORMAT_VARIABLE 0x80
|
||||
#define MASK_PACKETCONFIG1_DCFREE 0x60
|
||||
#define MASK_PACKETCONFIG1_CRC_ON 0x10 /* default */
|
||||
#define MASK_PACKETCONFIG1_CRCAUTOCLEAR_OFF 0x08
|
||||
#define MASK_PACKETCONFIG1_ADDRESSFILTERING 0x06
|
||||
|
||||
#define PACKETCONFIG1_DCFREE_OFF 0x00 /* default */
|
||||
#define PACKETCONFIG1_DCFREE_MANCHESTER 0x20
|
||||
#define PACKETCONFIG1_DCFREE_WHITENING 0x40
|
||||
#define PACKETCONFIG1_ADDRESSFILTERING_OFF 0x00 /* default */
|
||||
#define PACKETCONFIG1_ADDRESSFILTERING_NODE 0x02
|
||||
#define PACKETCONFIG1_ADDRESSFILTERING_NODEBROADCAST 0x04
|
||||
|
||||
/*
|
||||
* // RegAutoModes
|
||||
* #define AUTOMODES_ENTER_OFF 0x00 // Default
|
||||
* #define AUTOMODES_ENTER_FIFONOTEMPTY 0x20
|
||||
* #define AUTOMODES_ENTER_FIFOLEVEL 0x40
|
||||
* #define AUTOMODES_ENTER_CRCOK 0x60
|
||||
* #define AUTOMODES_ENTER_PAYLOADREADY 0x80
|
||||
* #define AUTOMODES_ENTER_SYNCADRSMATCH 0xA0
|
||||
* #define AUTOMODES_ENTER_PACKETSENT 0xC0
|
||||
* #define AUTOMODES_ENTER_FIFOEMPTY 0xE0
|
||||
*
|
||||
* #define AUTOMODES_EXIT_OFF 0x00 // Default
|
||||
* #define AUTOMODES_EXIT_FIFOEMPTY 0x04
|
||||
* #define AUTOMODES_EXIT_FIFOLEVEL 0x08
|
||||
* #define AUTOMODES_EXIT_CRCOK 0x0C
|
||||
* #define AUTOMODES_EXIT_PAYLOADREADY 0x10
|
||||
* #define AUTOMODES_EXIT_SYNCADRSMATCH 0x14
|
||||
* #define AUTOMODES_EXIT_PACKETSENT 0x18
|
||||
* #define AUTOMODES_EXIT_RXTIMEOUT 0x1C
|
||||
*
|
||||
* #define AUTOMODES_INTERMEDIATE_SLEEP 0x00 // Default
|
||||
* #define AUTOMODES_INTERMEDIATE_STANDBY 0x01
|
||||
* #define AUTOMODES_INTERMEDIATE_RECEIVER 0x02
|
||||
* #define AUTOMODES_INTERMEDIATE_TRANSMITTER 0x03
|
||||
*
|
||||
*/
|
||||
/* RegFifoThresh (0x3c) */
|
||||
#define MASK_FIFO_THRESH_TXSTART 0x80
|
||||
#define MASK_FIFO_THRESH_VALUE 0x7F
|
||||
|
||||
/*
|
||||
*
|
||||
* // RegPacketConfig2
|
||||
* #define PACKET2_RXRESTARTDELAY_1BIT 0x00 // Default
|
||||
* #define PACKET2_RXRESTARTDELAY_2BITS 0x10
|
||||
* #define PACKET2_RXRESTARTDELAY_4BITS 0x20
|
||||
* #define PACKET2_RXRESTARTDELAY_8BITS 0x30
|
||||
* #define PACKET2_RXRESTARTDELAY_16BITS 0x40
|
||||
* #define PACKET2_RXRESTARTDELAY_32BITS 0x50
|
||||
* #define PACKET2_RXRESTARTDELAY_64BITS 0x60
|
||||
* #define PACKET2_RXRESTARTDELAY_128BITS 0x70
|
||||
* #define PACKET2_RXRESTARTDELAY_256BITS 0x80
|
||||
* #define PACKET2_RXRESTARTDELAY_512BITS 0x90
|
||||
* #define PACKET2_RXRESTARTDELAY_1024BITS 0xA0
|
||||
* #define PACKET2_RXRESTARTDELAY_2048BITS 0xB0
|
||||
* #define PACKET2_RXRESTARTDELAY_NONE 0xC0
|
||||
* #define PACKET2_RXRESTART 0x04
|
||||
*
|
||||
* #define PACKET2_AUTORXRESTART_ON 0x02 // Default
|
||||
* #define PACKET2_AUTORXRESTART_OFF 0x00
|
||||
*
|
||||
* #define PACKET2_AES_ON 0x01
|
||||
* #define PACKET2_AES_OFF 0x00 // Default
|
||||
*
|
||||
*
|
||||
* // RegTemp1
|
||||
* #define TEMP1_MEAS_START 0x08
|
||||
* #define TEMP1_MEAS_RUNNING 0x04
|
||||
* #define TEMP1_ADCLOWPOWER_ON 0x01 // Default
|
||||
* #define TEMP1_ADCLOWPOWER_OFF 0x00
|
||||
*/
|
||||
|
||||
// RegTestDagc (0x6F)
|
||||
#define DAGC_NORMAL 0x00 /* Reset value */
|
||||
#define DAGC_IMPROVED_LOWBETA1 0x20
|
||||
#define DAGC_IMPROVED_LOWBETA0 0x30 /* Recommended val */
|
||||
Loading…
Reference in New Issue
Block a user