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b43: Add support for new firmware
This patch adds support for new firmware. Old firmware is still supported until July 2008. To get new firmware, go to ftp://ftp.linksys.com/opensourcecode/wrt150nv11/1.51.3/ and download the tarball. We don't have a smaller tarball, yet. That will be fixed later. You can extract firmware out of the "wl_ap.o" file contained in this tarball using latest fwcutter. You must pass the option --unsupported to fwcutter. Fwcutter-010 with official support for a new firmware image will be released soon. Signed-off-by: Michael Buesch <mb@bu3sch.de> Signed-off-by: John W. Linville <linville@tuxdriver.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Michael Buesch
David S. Miller
parent
243dcfcc1d
commit
eb189d8bc9
@ -345,3 +345,12 @@ What (Why):
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When: January 2009 or Linux 2.7.0, whichever comes first
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Why: Superseded by newer revisions or modules
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Who: Jan Engelhardt <jengelh@computergmbh.de>
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---------------------------
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What: b43 support for firmware revision < 410
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When: July 2008
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Why: The support code for the old firmware hurts code readability/maintainability
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and slightly hurts runtime performance. Bugfixes for the old firmware
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are not provided by Broadcom anymore.
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Who: Michael Buesch <mb@bu3sch.de>
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@ -807,7 +807,7 @@ struct b43_dmaring *b43_setup_dmaring(struct b43_wldev *dev,
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goto err_kfree_ring;
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if (for_tx) {
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ring->txhdr_cache = kcalloc(nr_slots,
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sizeof(struct b43_txhdr_fw4),
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b43_txhdr_size(dev),
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GFP_KERNEL);
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if (!ring->txhdr_cache)
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goto err_kfree_meta;
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@ -815,22 +815,21 @@ struct b43_dmaring *b43_setup_dmaring(struct b43_wldev *dev,
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/* test for ability to dma to txhdr_cache */
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dma_test = dma_map_single(dev->dev->dev,
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ring->txhdr_cache,
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sizeof(struct b43_txhdr_fw4),
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b43_txhdr_size(dev),
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DMA_TO_DEVICE);
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if (dma_mapping_error(dma_test)) {
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/* ugh realloc */
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kfree(ring->txhdr_cache);
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ring->txhdr_cache = kcalloc(nr_slots,
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sizeof(struct
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b43_txhdr_fw4),
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b43_txhdr_size(dev),
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GFP_KERNEL | GFP_DMA);
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if (!ring->txhdr_cache)
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goto err_kfree_meta;
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dma_test = dma_map_single(dev->dev->dev,
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ring->txhdr_cache,
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sizeof(struct b43_txhdr_fw4),
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b43_txhdr_size(dev),
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DMA_TO_DEVICE);
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if (dma_mapping_error(dma_test))
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@ -838,7 +837,7 @@ struct b43_dmaring *b43_setup_dmaring(struct b43_wldev *dev,
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}
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dma_unmap_single(dev->dev->dev,
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dma_test, sizeof(struct b43_txhdr_fw4),
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dma_test, b43_txhdr_size(dev),
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DMA_TO_DEVICE);
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}
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@ -1122,6 +1121,7 @@ static int dma_tx_fragment(struct b43_dmaring *ring,
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struct b43_dmadesc_meta *meta_hdr;
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struct sk_buff *bounce_skb;
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u16 cookie;
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size_t hdrsize = b43_txhdr_size(ring->dev);
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#define SLOTS_PER_PACKET 2
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B43_WARN_ON(skb_shinfo(skb)->nr_frags);
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@ -1131,17 +1131,17 @@ static int dma_tx_fragment(struct b43_dmaring *ring,
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desc = ops->idx2desc(ring, slot, &meta_hdr);
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memset(meta_hdr, 0, sizeof(*meta_hdr));
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header = &(ring->txhdr_cache[slot * sizeof(struct b43_txhdr_fw4)]);
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header = &(ring->txhdr_cache[slot * hdrsize]);
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cookie = generate_cookie(ring, slot);
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b43_generate_txhdr(ring->dev, header,
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skb->data, skb->len, ctl, cookie);
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meta_hdr->dmaaddr = map_descbuffer(ring, (unsigned char *)header,
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sizeof(struct b43_txhdr_fw4), 1);
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hdrsize, 1);
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if (dma_mapping_error(meta_hdr->dmaaddr))
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return -EIO;
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ops->fill_descriptor(ring, desc, meta_hdr->dmaaddr,
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sizeof(struct b43_txhdr_fw4), 1, 0, 0);
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hdrsize, 1, 0, 0);
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/* Get a slot for the payload. */
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slot = request_slot(ring);
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@ -1189,7 +1189,7 @@ out_free_bounce:
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dev_kfree_skb_any(skb);
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out_unmap_hdr:
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unmap_descbuffer(ring, meta_hdr->dmaaddr,
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sizeof(struct b43_txhdr_fw4), 1);
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hdrsize, 1);
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return err;
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}
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@ -1298,7 +1298,7 @@ void b43_dma_handle_txstatus(struct b43_wldev *dev,
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1);
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else
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unmap_descbuffer(ring, meta->dmaaddr,
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sizeof(struct b43_txhdr_fw4), 1);
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b43_txhdr_size(dev), 1);
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if (meta->is_last_fragment) {
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B43_WARN_ON(!meta->skb);
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@ -1569,11 +1569,17 @@ static void b43_release_firmware(struct b43_wldev *dev)
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dev->fw.initvals_band = NULL;
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}
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static void b43_print_fw_helptext(struct b43_wl *wl)
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static void b43_print_fw_helptext(struct b43_wl *wl, bool error)
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{
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b43err(wl, "You must go to "
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const char *text;
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text = "You must go to "
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"http://linuxwireless.org/en/users/Drivers/b43#devicefirmware "
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"and download the correct firmware (version 4).\n");
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"and download the latest firmware (version 4).\n";
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if (error)
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b43err(wl, text);
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else
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b43warn(wl, text);
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}
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static int do_request_fw(struct b43_wldev *dev,
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@ -1725,7 +1731,7 @@ static int b43_request_firmware(struct b43_wldev *dev)
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return 0;
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err_load:
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b43_print_fw_helptext(dev->wl);
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b43_print_fw_helptext(dev->wl, 1);
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goto error;
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err_no_ucode:
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@ -1795,7 +1801,7 @@ static int b43_upload_microcode(struct b43_wldev *dev)
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i++;
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if (i >= 50) {
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b43err(dev->wl, "Microcode not responding\n");
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b43_print_fw_helptext(dev->wl);
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b43_print_fw_helptext(dev->wl, 1);
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err = -ENODEV;
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goto out;
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}
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@ -1813,7 +1819,7 @@ static int b43_upload_microcode(struct b43_wldev *dev)
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b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
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"binary drivers older than version 4.x is unsupported. "
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"You must upgrade your firmware files.\n");
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b43_print_fw_helptext(dev->wl);
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b43_print_fw_helptext(dev->wl, 1);
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b43_write32(dev, B43_MMIO_MACCTL, 0);
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err = -EOPNOTSUPP;
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goto out;
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@ -1827,7 +1833,13 @@ static int b43_upload_microcode(struct b43_wldev *dev)
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dev->fw.rev = fwrev;
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dev->fw.patch = fwpatch;
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out:
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if (b43_is_old_txhdr_format(dev)) {
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b43warn(dev->wl, "You are using an old firmware image. "
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"Support for old firmware will be removed in July 2008.\n");
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b43_print_fw_helptext(dev->wl, 0);
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}
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out:
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return err;
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}
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@ -1887,7 +1899,7 @@ static int b43_write_initvals(struct b43_wldev *dev,
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err_format:
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b43err(dev->wl, "Initial Values Firmware file-format error.\n");
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b43_print_fw_helptext(dev->wl);
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b43_print_fw_helptext(dev->wl, 1);
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return -EPROTO;
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}
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@ -2149,13 +2161,19 @@ static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
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switch (antenna) {
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case B43_ANTENNA0:
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ant |= B43_TX4_PHY_ANT0;
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ant |= B43_TXH_PHY_ANT0;
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break;
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case B43_ANTENNA1:
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ant |= B43_TX4_PHY_ANT1;
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ant |= B43_TXH_PHY_ANT1;
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break;
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case B43_ANTENNA2:
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ant |= B43_TXH_PHY_ANT2;
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break;
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case B43_ANTENNA3:
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ant |= B43_TXH_PHY_ANT3;
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break;
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case B43_ANTENNA_AUTO:
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ant |= B43_TX4_PHY_ANTLAST;
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ant |= B43_TXH_PHY_ANT01AUTO;
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break;
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default:
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B43_WARN_ON(1);
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@ -2165,15 +2183,15 @@ static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
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/* For Beacons */
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tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
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tmp = (tmp & ~B43_TX4_PHY_ANT) | ant;
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tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
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b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, tmp);
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/* For ACK/CTS */
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tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
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tmp = (tmp & ~B43_TX4_PHY_ANT) | ant;
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tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
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b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
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/* For Probe Resposes */
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tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
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tmp = (tmp & ~B43_TX4_PHY_ANT) | ant;
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tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
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b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
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}
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@ -2738,6 +2756,10 @@ static int b43_antenna_from_ieee80211(struct b43_wldev *dev, u8 antenna)
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return B43_ANTENNA0;
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case 2: /* Antenna 1 */
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return B43_ANTENNA1;
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case 3: /* Antenna 2 */
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return B43_ANTENNA2;
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case 4: /* Antenna 3 */
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return B43_ANTENNA3;
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default:
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return B43_ANTENNA_DEFAULT;
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}
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@ -180,6 +180,8 @@ enum {
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B43_ANTENNA1, /* Antenna 0 */
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B43_ANTENNA_AUTO1, /* Automatic, starting with antenna 1 */
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B43_ANTENNA_AUTO0, /* Automatic, starting with antenna 0 */
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B43_ANTENNA2,
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B43_ANTENNA3 = 8,
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B43_ANTENNA_AUTO = B43_ANTENNA_AUTO0,
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B43_ANTENNA_DEFAULT = B43_ANTENNA_AUTO,
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@ -177,13 +177,15 @@ static u8 b43_calc_fallback_rate(u8 bitrate)
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return 0;
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}
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static void generate_txhdr_fw4(struct b43_wldev *dev,
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struct b43_txhdr_fw4 *txhdr,
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const unsigned char *fragment_data,
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unsigned int fragment_len,
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const struct ieee80211_tx_control *txctl,
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u16 cookie)
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/* Generate a TX data header. */
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void b43_generate_txhdr(struct b43_wldev *dev,
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u8 *_txhdr,
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const unsigned char *fragment_data,
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unsigned int fragment_len,
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const struct ieee80211_tx_control *txctl,
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u16 cookie)
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{
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struct b43_txhdr *txhdr = (struct b43_txhdr *)_txhdr;
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const struct b43_phy *phy = &dev->phy;
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const struct ieee80211_hdr *wlhdr =
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(const struct ieee80211_hdr *)fragment_data;
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@ -241,23 +243,30 @@ static void generate_txhdr_fw4(struct b43_wldev *dev,
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plcp_fragment_len += txctl->icv_len;
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key_idx = b43_kidx_to_fw(dev, key_idx);
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mac_ctl |= (key_idx << B43_TX4_MAC_KEYIDX_SHIFT) &
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B43_TX4_MAC_KEYIDX;
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mac_ctl |= (key->algorithm << B43_TX4_MAC_KEYALG_SHIFT) &
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B43_TX4_MAC_KEYALG;
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mac_ctl |= (key_idx << B43_TXH_MAC_KEYIDX_SHIFT) &
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B43_TXH_MAC_KEYIDX;
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mac_ctl |= (key->algorithm << B43_TXH_MAC_KEYALG_SHIFT) &
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B43_TXH_MAC_KEYALG;
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wlhdr_len = ieee80211_get_hdrlen(fctl);
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iv_len = min((size_t) txctl->iv_len,
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ARRAY_SIZE(txhdr->iv));
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memcpy(txhdr->iv, ((u8 *) wlhdr) + wlhdr_len, iv_len);
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}
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b43_generate_plcp_hdr((struct b43_plcp_hdr4 *)(&txhdr->plcp),
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plcp_fragment_len, rate);
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if (b43_is_old_txhdr_format(dev)) {
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b43_generate_plcp_hdr((struct b43_plcp_hdr4 *)(&txhdr->old_format.plcp),
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plcp_fragment_len, rate);
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} else {
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b43_generate_plcp_hdr((struct b43_plcp_hdr4 *)(&txhdr->new_format.plcp),
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plcp_fragment_len, rate);
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}
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b43_generate_plcp_hdr((struct b43_plcp_hdr4 *)(&txhdr->plcp_fb),
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plcp_fragment_len, rate_fb);
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/* Extra Frame Types */
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if (rate_fb_ofdm)
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extra_ft |= B43_TX4_EFT_FBOFDM;
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extra_ft |= B43_TXH_EFT_FB_OFDM;
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else
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extra_ft |= B43_TXH_EFT_FB_CCK;
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/* Set channel radio code. Note that the micrcode ORs 0x100 to
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* this value before comparing it to the value in SHM, if this
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@ -267,19 +276,27 @@ static void generate_txhdr_fw4(struct b43_wldev *dev,
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/* PHY TX Control word */
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if (rate_ofdm)
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phy_ctl |= B43_TX4_PHY_OFDM;
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phy_ctl |= B43_TXH_PHY_ENC_OFDM;
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else
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phy_ctl |= B43_TXH_PHY_ENC_CCK;
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if (dev->short_preamble)
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phy_ctl |= B43_TX4_PHY_SHORTPRMBL;
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phy_ctl |= B43_TXH_PHY_SHORTPRMBL;
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switch (b43_ieee80211_antenna_sanitize(dev, txctl->antenna_sel_tx)) {
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case 0: /* Default */
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phy_ctl |= B43_TX4_PHY_ANTLAST;
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phy_ctl |= B43_TXH_PHY_ANT01AUTO;
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break;
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case 1: /* Antenna 0 */
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phy_ctl |= B43_TX4_PHY_ANT0;
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phy_ctl |= B43_TXH_PHY_ANT0;
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break;
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case 2: /* Antenna 1 */
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phy_ctl |= B43_TX4_PHY_ANT1;
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phy_ctl |= B43_TXH_PHY_ANT1;
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break;
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case 3: /* Antenna 2 */
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phy_ctl |= B43_TXH_PHY_ANT2;
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break;
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case 4: /* Antenna 3 */
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phy_ctl |= B43_TXH_PHY_ANT3;
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break;
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default:
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B43_WARN_ON(1);
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@ -287,16 +304,16 @@ static void generate_txhdr_fw4(struct b43_wldev *dev,
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/* MAC control */
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if (!(txctl->flags & IEEE80211_TXCTL_NO_ACK))
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mac_ctl |= B43_TX4_MAC_ACK;
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mac_ctl |= B43_TXH_MAC_ACK;
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if (!(((fctl & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_CTL) &&
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((fctl & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_PSPOLL)))
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mac_ctl |= B43_TX4_MAC_HWSEQ;
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mac_ctl |= B43_TXH_MAC_HWSEQ;
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if (txctl->flags & IEEE80211_TXCTL_FIRST_FRAGMENT)
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mac_ctl |= B43_TX4_MAC_STMSDU;
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mac_ctl |= B43_TXH_MAC_STMSDU;
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if (phy->type == B43_PHYTYPE_A)
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mac_ctl |= B43_TX4_MAC_5GHZ;
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mac_ctl |= B43_TXH_MAC_5GHZ;
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if (txctl->flags & IEEE80211_TXCTL_LONG_RETRY_LIMIT)
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mac_ctl |= B43_TX4_MAC_LONGFRAME;
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mac_ctl |= B43_TXH_MAC_LONGFRAME;
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/* Generate the RTS or CTS-to-self frame */
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if ((txctl->flags & IEEE80211_TXCTL_USE_RTS_CTS) ||
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@ -305,6 +322,7 @@ static void generate_txhdr_fw4(struct b43_wldev *dev,
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struct ieee80211_hdr *hdr;
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int rts_rate, rts_rate_fb;
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int rts_rate_ofdm, rts_rate_fb_ofdm;
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struct b43_plcp_hdr6 *plcp;
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rts_rate = txctl->rts_cts_rate;
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rts_rate_ofdm = b43_is_ofdm_rate(rts_rate);
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@ -312,58 +330,84 @@ static void generate_txhdr_fw4(struct b43_wldev *dev,
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rts_rate_fb_ofdm = b43_is_ofdm_rate(rts_rate_fb);
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if (txctl->flags & IEEE80211_TXCTL_USE_CTS_PROTECT) {
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struct ieee80211_cts *cts;
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if (b43_is_old_txhdr_format(dev)) {
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cts = (struct ieee80211_cts *)
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(txhdr->old_format.rts_frame);
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} else {
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cts = (struct ieee80211_cts *)
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(txhdr->new_format.rts_frame);
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}
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ieee80211_ctstoself_get(dev->wl->hw, txctl->vif,
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fragment_data, fragment_len,
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txctl,
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(struct ieee80211_cts *)(txhdr->
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rts_frame));
|
||||
mac_ctl |= B43_TX4_MAC_SENDCTS;
|
||||
txctl, cts);
|
||||
mac_ctl |= B43_TXH_MAC_SENDCTS;
|
||||
len = sizeof(struct ieee80211_cts);
|
||||
} else {
|
||||
struct ieee80211_rts *rts;
|
||||
|
||||
if (b43_is_old_txhdr_format(dev)) {
|
||||
rts = (struct ieee80211_rts *)
|
||||
(txhdr->old_format.rts_frame);
|
||||
} else {
|
||||
rts = (struct ieee80211_rts *)
|
||||
(txhdr->new_format.rts_frame);
|
||||
}
|
||||
ieee80211_rts_get(dev->wl->hw, txctl->vif,
|
||||
fragment_data, fragment_len, txctl,
|
||||
(struct ieee80211_rts *)(txhdr->
|
||||
rts_frame));
|
||||
mac_ctl |= B43_TX4_MAC_SENDRTS;
|
||||
fragment_data, fragment_len,
|
||||
txctl, rts);
|
||||
mac_ctl |= B43_TXH_MAC_SENDRTS;
|
||||
len = sizeof(struct ieee80211_rts);
|
||||
}
|
||||
len += FCS_LEN;
|
||||
b43_generate_plcp_hdr((struct b43_plcp_hdr4 *)(&txhdr->
|
||||
rts_plcp), len,
|
||||
rts_rate);
|
||||
b43_generate_plcp_hdr((struct b43_plcp_hdr4 *)(&txhdr->
|
||||
rts_plcp_fb),
|
||||
|
||||
/* Generate the PLCP headers for the RTS/CTS frame */
|
||||
if (b43_is_old_txhdr_format(dev))
|
||||
plcp = &txhdr->old_format.rts_plcp;
|
||||
else
|
||||
plcp = &txhdr->new_format.rts_plcp;
|
||||
b43_generate_plcp_hdr((struct b43_plcp_hdr4 *)plcp,
|
||||
len, rts_rate);
|
||||
plcp = &txhdr->rts_plcp_fb;
|
||||
b43_generate_plcp_hdr((struct b43_plcp_hdr4 *)plcp,
|
||||
len, rts_rate_fb);
|
||||
hdr = (struct ieee80211_hdr *)(&txhdr->rts_frame);
|
||||
|
||||
if (b43_is_old_txhdr_format(dev)) {
|
||||
hdr = (struct ieee80211_hdr *)
|
||||
(&txhdr->old_format.rts_frame);
|
||||
} else {
|
||||
hdr = (struct ieee80211_hdr *)
|
||||
(&txhdr->new_format.rts_frame);
|
||||
}
|
||||
txhdr->rts_dur_fb = hdr->duration_id;
|
||||
|
||||
if (rts_rate_ofdm) {
|
||||
extra_ft |= B43_TX4_EFT_RTSOFDM;
|
||||
extra_ft |= B43_TXH_EFT_RTS_OFDM;
|
||||
txhdr->phy_rate_rts =
|
||||
b43_plcp_get_ratecode_ofdm(rts_rate);
|
||||
} else
|
||||
} else {
|
||||
extra_ft |= B43_TXH_EFT_RTS_CCK;
|
||||
txhdr->phy_rate_rts =
|
||||
b43_plcp_get_ratecode_cck(rts_rate);
|
||||
}
|
||||
if (rts_rate_fb_ofdm)
|
||||
extra_ft |= B43_TX4_EFT_RTSFBOFDM;
|
||||
extra_ft |= B43_TXH_EFT_RTSFB_OFDM;
|
||||
else
|
||||
extra_ft |= B43_TXH_EFT_RTSFB_CCK;
|
||||
}
|
||||
|
||||
/* Magic cookie */
|
||||
txhdr->cookie = cpu_to_le16(cookie);
|
||||
if (b43_is_old_txhdr_format(dev))
|
||||
txhdr->old_format.cookie = cpu_to_le16(cookie);
|
||||
else
|
||||
txhdr->new_format.cookie = cpu_to_le16(cookie);
|
||||
|
||||
/* Apply the bitfields */
|
||||
txhdr->mac_ctl = cpu_to_le32(mac_ctl);
|
||||
txhdr->phy_ctl = cpu_to_le16(phy_ctl);
|
||||
txhdr->extra_ft = extra_ft;
|
||||
}
|
||||
|
||||
void b43_generate_txhdr(struct b43_wldev *dev,
|
||||
u8 * txhdr,
|
||||
const unsigned char *fragment_data,
|
||||
unsigned int fragment_len,
|
||||
const struct ieee80211_tx_control *txctl, u16 cookie)
|
||||
{
|
||||
generate_txhdr_fw4(dev, (struct b43_txhdr_fw4 *)txhdr,
|
||||
fragment_data, fragment_len, txctl, cookie);
|
||||
}
|
||||
|
||||
static s8 b43_rssi_postprocess(struct b43_wldev *dev,
|
||||
|
||||
@ -19,68 +19,160 @@ _b43_declare_plcp_hdr(6);
|
||||
#undef _b43_declare_plcp_hdr
|
||||
|
||||
/* TX header for v4 firmware */
|
||||
struct b43_txhdr_fw4 {
|
||||
__le32 mac_ctl; /* MAC TX control */
|
||||
__le16 mac_frame_ctl; /* Copy of the FrameControl field */
|
||||
struct b43_txhdr {
|
||||
__le32 mac_ctl; /* MAC TX control */
|
||||
__le16 mac_frame_ctl; /* Copy of the FrameControl field */
|
||||
__le16 tx_fes_time_norm; /* TX FES Time Normal */
|
||||
__le16 phy_ctl; /* PHY TX control */
|
||||
__le16 phy_ctl_0; /* Unused */
|
||||
__le16 phy_ctl_1; /* Unused */
|
||||
__le16 phy_ctl_rts_0; /* Unused */
|
||||
__le16 phy_ctl_rts_1; /* Unused */
|
||||
__u8 phy_rate; /* PHY rate */
|
||||
__u8 phy_rate_rts; /* PHY rate for RTS/CTS */
|
||||
__u8 extra_ft; /* Extra Frame Types */
|
||||
__u8 chan_radio_code; /* Channel Radio Code */
|
||||
__u8 iv[16]; /* Encryption IV */
|
||||
__u8 tx_receiver[6]; /* TX Frame Receiver address */
|
||||
__le16 tx_fes_time_fb; /* TX FES Time Fallback */
|
||||
struct b43_plcp_hdr6 rts_plcp_fb; /* RTS fallback PLCP */
|
||||
__le16 rts_dur_fb; /* RTS fallback duration */
|
||||
struct b43_plcp_hdr6 plcp_fb; /* Fallback PLCP */
|
||||
__le16 dur_fb; /* Fallback duration */
|
||||
__le16 mm_dur_time; /* Unused */
|
||||
__le16 mm_dur_time_fb; /* Unused */
|
||||
__le32 time_stamp; /* Timestamp */
|
||||
PAD_BYTES(2);
|
||||
__le16 cookie; /* TX frame cookie */
|
||||
__le16 tx_status; /* TX status */
|
||||
struct b43_plcp_hdr6 rts_plcp; /* RTS PLCP */
|
||||
__u8 rts_frame[16]; /* The RTS frame (if used) */
|
||||
PAD_BYTES(2);
|
||||
struct b43_plcp_hdr6 plcp; /* Main PLCP */
|
||||
__le16 phy_ctl; /* PHY TX control */
|
||||
__le16 phy_ctl1; /* PHY TX control word 1 */
|
||||
__le16 phy_ctl1_fb; /* PHY TX control word 1 for fallback rates */
|
||||
__le16 phy_ctl1_rts; /* PHY TX control word 1 RTS */
|
||||
__le16 phy_ctl1_rts_fb; /* PHY TX control word 1 RTS for fallback rates */
|
||||
__u8 phy_rate; /* PHY rate */
|
||||
__u8 phy_rate_rts; /* PHY rate for RTS/CTS */
|
||||
__u8 extra_ft; /* Extra Frame Types */
|
||||
__u8 chan_radio_code; /* Channel Radio Code */
|
||||
__u8 iv[16]; /* Encryption IV */
|
||||
__u8 tx_receiver[6]; /* TX Frame Receiver address */
|
||||
__le16 tx_fes_time_fb; /* TX FES Time Fallback */
|
||||
struct b43_plcp_hdr6 rts_plcp_fb; /* RTS fallback PLCP header */
|
||||
__le16 rts_dur_fb; /* RTS fallback duration */
|
||||
struct b43_plcp_hdr6 plcp_fb; /* Fallback PLCP header */
|
||||
__le16 dur_fb; /* Fallback duration */
|
||||
__le16 mimo_modelen; /* MIMO mode length */
|
||||
__le16 mimo_ratelen_fb; /* MIMO fallback rate length */
|
||||
__le32 timeout; /* Timeout */
|
||||
|
||||
union {
|
||||
/* The new r410 format. */
|
||||
struct {
|
||||
__le16 mimo_antenna; /* MIMO antenna select */
|
||||
__le16 preload_size; /* Preload size */
|
||||
PAD_BYTES(2);
|
||||
__le16 cookie; /* TX frame cookie */
|
||||
__le16 tx_status; /* TX status */
|
||||
struct b43_plcp_hdr6 rts_plcp; /* RTS PLCP header */
|
||||
__u8 rts_frame[16]; /* The RTS frame (if used) */
|
||||
PAD_BYTES(2);
|
||||
struct b43_plcp_hdr6 plcp; /* Main PLCP header */
|
||||
} new_format __attribute__ ((__packed__));
|
||||
|
||||
/* The old r351 format. */
|
||||
struct {
|
||||
PAD_BYTES(2);
|
||||
__le16 cookie; /* TX frame cookie */
|
||||
__le16 tx_status; /* TX status */
|
||||
struct b43_plcp_hdr6 rts_plcp; /* RTS PLCP header */
|
||||
__u8 rts_frame[16]; /* The RTS frame (if used) */
|
||||
PAD_BYTES(2);
|
||||
struct b43_plcp_hdr6 plcp; /* Main PLCP header */
|
||||
} old_format __attribute__ ((__packed__));
|
||||
|
||||
} __attribute__ ((__packed__));
|
||||
} __attribute__ ((__packed__));
|
||||
|
||||
/* MAC TX control */
|
||||
#define B43_TX4_MAC_KEYIDX 0x0FF00000 /* Security key index */
|
||||
#define B43_TX4_MAC_KEYIDX_SHIFT 20
|
||||
#define B43_TX4_MAC_KEYALG 0x00070000 /* Security key algorithm */
|
||||
#define B43_TX4_MAC_KEYALG_SHIFT 16
|
||||
#define B43_TX4_MAC_LIFETIME 0x00001000
|
||||
#define B43_TX4_MAC_FRAMEBURST 0x00000800
|
||||
#define B43_TX4_MAC_SENDCTS 0x00000400
|
||||
#define B43_TX4_MAC_AMPDU 0x00000300
|
||||
#define B43_TX4_MAC_AMPDU_SHIFT 8
|
||||
#define B43_TX4_MAC_5GHZ 0x00000080
|
||||
#define B43_TX4_MAC_IGNPMQ 0x00000020
|
||||
#define B43_TX4_MAC_HWSEQ 0x00000010 /* Use Hardware Sequence Number */
|
||||
#define B43_TX4_MAC_STMSDU 0x00000008 /* Start MSDU */
|
||||
#define B43_TX4_MAC_SENDRTS 0x00000004
|
||||
#define B43_TX4_MAC_LONGFRAME 0x00000002
|
||||
#define B43_TX4_MAC_ACK 0x00000001
|
||||
#define B43_TXH_MAC_USEFBR 0x10000000 /* Use fallback rate for this AMPDU */
|
||||
#define B43_TXH_MAC_KEYIDX 0x0FF00000 /* Security key index */
|
||||
#define B43_TXH_MAC_KEYIDX_SHIFT 20
|
||||
#define B43_TXH_MAC_KEYALG 0x00070000 /* Security key algorithm */
|
||||
#define B43_TXH_MAC_KEYALG_SHIFT 16
|
||||
#define B43_TXH_MAC_AMIC 0x00008000 /* AMIC */
|
||||
#define B43_TXH_MAC_RIFS 0x00004000 /* Use RIFS */
|
||||
#define B43_TXH_MAC_LIFETIME 0x00002000 /* Lifetime */
|
||||
#define B43_TXH_MAC_FRAMEBURST 0x00001000 /* Frameburst */
|
||||
#define B43_TXH_MAC_SENDCTS 0x00000800 /* Send CTS-to-self */
|
||||
#define B43_TXH_MAC_AMPDU 0x00000600 /* AMPDU status */
|
||||
#define B43_TXH_MAC_AMPDU_MPDU 0x00000000 /* Regular MPDU, not an AMPDU */
|
||||
#define B43_TXH_MAC_AMPDU_FIRST 0x00000200 /* First MPDU or AMPDU */
|
||||
#define B43_TXH_MAC_AMPDU_INTER 0x00000400 /* Intermediate MPDU or AMPDU */
|
||||
#define B43_TXH_MAC_AMPDU_LAST 0x00000600 /* Last (or only) MPDU of AMPDU */
|
||||
#define B43_TXH_MAC_40MHZ 0x00000100 /* Use 40 MHz bandwidth */
|
||||
#define B43_TXH_MAC_5GHZ 0x00000080 /* 5GHz band */
|
||||
#define B43_TXH_MAC_DFCS 0x00000040 /* DFCS */
|
||||
#define B43_TXH_MAC_IGNPMQ 0x00000020 /* Ignore PMQ */
|
||||
#define B43_TXH_MAC_HWSEQ 0x00000010 /* Use Hardware Sequence Number */
|
||||
#define B43_TXH_MAC_STMSDU 0x00000008 /* Start MSDU */
|
||||
#define B43_TXH_MAC_SENDRTS 0x00000004 /* Send RTS */
|
||||
#define B43_TXH_MAC_LONGFRAME 0x00000002 /* Long frame */
|
||||
#define B43_TXH_MAC_ACK 0x00000001 /* Immediate ACK */
|
||||
|
||||
/* Extra Frame Types */
|
||||
#define B43_TX4_EFT_FBOFDM 0x0001 /* Data frame fallback rate type */
|
||||
#define B43_TX4_EFT_RTSOFDM 0x0004 /* RTS/CTS rate type */
|
||||
#define B43_TX4_EFT_RTSFBOFDM 0x0010 /* RTS/CTS fallback rate type */
|
||||
#define B43_TXH_EFT_FB 0x03 /* Data frame fallback encoding */
|
||||
#define B43_TXH_EFT_FB_CCK 0x00 /* CCK */
|
||||
#define B43_TXH_EFT_FB_OFDM 0x01 /* OFDM */
|
||||
#define B43_TXH_EFT_FB_EWC 0x02 /* EWC */
|
||||
#define B43_TXH_EFT_FB_N 0x03 /* N */
|
||||
#define B43_TXH_EFT_RTS 0x0C /* RTS/CTS encoding */
|
||||
#define B43_TXH_EFT_RTS_CCK 0x00 /* CCK */
|
||||
#define B43_TXH_EFT_RTS_OFDM 0x04 /* OFDM */
|
||||
#define B43_TXH_EFT_RTS_EWC 0x08 /* EWC */
|
||||
#define B43_TXH_EFT_RTS_N 0x0C /* N */
|
||||
#define B43_TXH_EFT_RTSFB 0x30 /* RTS/CTS fallback encoding */
|
||||
#define B43_TXH_EFT_RTSFB_CCK 0x00 /* CCK */
|
||||
#define B43_TXH_EFT_RTSFB_OFDM 0x10 /* OFDM */
|
||||
#define B43_TXH_EFT_RTSFB_EWC 0x20 /* EWC */
|
||||
#define B43_TXH_EFT_RTSFB_N 0x30 /* N */
|
||||
|
||||
/* PHY TX control word */
|
||||
#define B43_TX4_PHY_OFDM 0x0001 /* Data frame rate type */
|
||||
#define B43_TX4_PHY_SHORTPRMBL 0x0010 /* Use short preamble */
|
||||
#define B43_TX4_PHY_ANT 0x03C0 /* Antenna selection */
|
||||
#define B43_TX4_PHY_ANT0 0x0000 /* Use antenna 0 */
|
||||
#define B43_TX4_PHY_ANT1 0x0100 /* Use antenna 1 */
|
||||
#define B43_TX4_PHY_ANTLAST 0x0300 /* Use last used antenna */
|
||||
#define B43_TXH_PHY_ENC 0x0003 /* Data frame encoding */
|
||||
#define B43_TXH_PHY_ENC_CCK 0x0000 /* CCK */
|
||||
#define B43_TXH_PHY_ENC_OFDM 0x0001 /* OFDM */
|
||||
#define B43_TXH_PHY_ENC_EWC 0x0002 /* EWC */
|
||||
#define B43_TXH_PHY_ENC_N 0x0003 /* N */
|
||||
#define B43_TXH_PHY_SHORTPRMBL 0x0010 /* Use short preamble */
|
||||
#define B43_TXH_PHY_ANT 0x03C0 /* Antenna selection */
|
||||
#define B43_TXH_PHY_ANT0 0x0000 /* Use antenna 0 */
|
||||
#define B43_TXH_PHY_ANT1 0x0040 /* Use antenna 1 */
|
||||
#define B43_TXH_PHY_ANT01AUTO 0x00C0 /* Use antenna 0/1 auto */
|
||||
#define B43_TXH_PHY_ANT2 0x0100 /* Use antenna 2 */
|
||||
#define B43_TXH_PHY_ANT3 0x0200 /* Use antenna 3 */
|
||||
#define B43_TXH_PHY_TXPWR 0xFC00 /* TX power */
|
||||
#define B43_TXH_PHY_TXPWR_SHIFT 10
|
||||
|
||||
/* PHY TX control word 1 */
|
||||
#define B43_TXH_PHY1_BW 0x0007 /* Bandwidth */
|
||||
#define B43_TXH_PHY1_BW_10 0x0000 /* 10 MHz */
|
||||
#define B43_TXH_PHY1_BW_10U 0x0001 /* 10 MHz upper */
|
||||
#define B43_TXH_PHY1_BW_20 0x0002 /* 20 MHz */
|
||||
#define B43_TXH_PHY1_BW_20U 0x0003 /* 20 MHz upper */
|
||||
#define B43_TXH_PHY1_BW_40 0x0004 /* 40 MHz */
|
||||
#define B43_TXH_PHY1_BW_40DUP 0x0005 /* 50 MHz duplicate */
|
||||
#define B43_TXH_PHY1_MODE 0x0038 /* Mode */
|
||||
#define B43_TXH_PHY1_MODE_SISO 0x0000 /* SISO */
|
||||
#define B43_TXH_PHY1_MODE_CDD 0x0008 /* CDD */
|
||||
#define B43_TXH_PHY1_MODE_STBC 0x0010 /* STBC */
|
||||
#define B43_TXH_PHY1_MODE_SDM 0x0018 /* SDM */
|
||||
#define B43_TXH_PHY1_CRATE 0x0700 /* Coding rate */
|
||||
#define B43_TXH_PHY1_CRATE_1_2 0x0000 /* 1/2 */
|
||||
#define B43_TXH_PHY1_CRATE_2_3 0x0100 /* 2/3 */
|
||||
#define B43_TXH_PHY1_CRATE_3_4 0x0200 /* 3/4 */
|
||||
#define B43_TXH_PHY1_CRATE_4_5 0x0300 /* 4/5 */
|
||||
#define B43_TXH_PHY1_CRATE_5_6 0x0400 /* 5/6 */
|
||||
#define B43_TXH_PHY1_CRATE_7_8 0x0600 /* 7/8 */
|
||||
#define B43_TXH_PHY1_MODUL 0x3800 /* Modulation scheme */
|
||||
#define B43_TXH_PHY1_MODUL_BPSK 0x0000 /* BPSK */
|
||||
#define B43_TXH_PHY1_MODUL_QPSK 0x0800 /* QPSK */
|
||||
#define B43_TXH_PHY1_MODUL_QAM16 0x1000 /* QAM16 */
|
||||
#define B43_TXH_PHY1_MODUL_QAM64 0x1800 /* QAM64 */
|
||||
#define B43_TXH_PHY1_MODUL_QAM256 0x2000 /* QAM256 */
|
||||
|
||||
|
||||
/* r351 firmware compatibility stuff. */
|
||||
static inline
|
||||
bool b43_is_old_txhdr_format(struct b43_wldev *dev)
|
||||
{
|
||||
return (dev->fw.rev <= 351);
|
||||
}
|
||||
|
||||
static inline
|
||||
size_t b43_txhdr_size(struct b43_wldev *dev)
|
||||
{
|
||||
if (b43_is_old_txhdr_format(dev))
|
||||
return 100 + sizeof(struct b43_plcp_hdr6);
|
||||
return 104 + sizeof(struct b43_plcp_hdr6);
|
||||
}
|
||||
|
||||
|
||||
void b43_generate_txhdr(struct b43_wldev *dev,
|
||||
u8 * txhdr,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user