mirror of
https://github.com/torvalds/linux.git
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Merge branch 'next/dt' into next/multiplatform
* next/dt: (182 commits) ARM: tegra: Add Avionic Design Tamonten Evaluation Carrier support ARM: tegra: Add Avionic Design Medcom-Wide support ARM: tegra: Add Avionic Design Plutux support ARM: tegra: Add Avionic Design Tamonten support ARM: tegra: dts: Add pwm label ARM: dt: tegra: whistler: configure power off ARM: mxs: m28evk: Disable OCOTP OUI loading ARM: imx6q: use pll2_pfd2_396m as the enfc_sel's parent ARM: dts: imx6q-sabrelite: add usbotg pinctrl support ARM: dts: imx23-olinuxino: Add USB host support ARM: dts: imx6q-sabrelite: add usbmisc device ARM: dts: mx23: Add USB resources ARM: dts: mxs: Add ethernetX to macX aliases ARM: msm: Remove non-DT targets from 8960 ARM: msm: Add DT support for 8960 ARM: msm: Move io mapping prototypes to common.h ARM: msm: Rename board-msm8x60 to signify its DT only status ARM: msm: Make 8660 a DT only target ARM: msm: Move 8660 to DT timer ARM: msm: Add DT support to msm_timer ...
This commit is contained in:
Olof Johansson
commit
ea832c41da
17
Documentation/devicetree/bindings/arm/mrvl/tauros2.txt
Normal file
17
Documentation/devicetree/bindings/arm/mrvl/tauros2.txt
Normal file
@ -0,0 +1,17 @@
|
||||
* Marvell Tauros2 Cache
|
||||
|
||||
Required properties:
|
||||
- compatible : Should be "marvell,tauros2-cache".
|
||||
- marvell,tauros2-cache-features : Specify the features supported for the
|
||||
tauros2 cache.
|
||||
The features including
|
||||
CACHE_TAUROS2_PREFETCH_ON (1 << 0)
|
||||
CACHE_TAUROS2_LINEFILL_BURST8 (1 << 1)
|
||||
The definition can be found at
|
||||
arch/arm/include/asm/hardware/cache-tauros2.h
|
||||
|
||||
Example:
|
||||
L2: l2-cache {
|
||||
compatible = "marvell,tauros2-cache";
|
||||
marvell,tauros2-cache-features = <0x3>;
|
||||
};
|
||||
38
Documentation/devicetree/bindings/arm/msm/timer.txt
Normal file
38
Documentation/devicetree/bindings/arm/msm/timer.txt
Normal file
@ -0,0 +1,38 @@
|
||||
* MSM Timer
|
||||
|
||||
Properties:
|
||||
|
||||
- compatible : Should at least contain "qcom,msm-timer". More specific
|
||||
properties such as "qcom,msm-gpt" and "qcom,msm-dgt" specify a general
|
||||
purpose timer and a debug timer respectively.
|
||||
|
||||
- interrupts : Interrupt indicating a match event.
|
||||
|
||||
- reg : Specifies the base address of the timer registers. The second region
|
||||
specifies an optional register used to configure the clock divider.
|
||||
|
||||
- clock-frequency : The frequency of the timer in Hz.
|
||||
|
||||
Optional:
|
||||
|
||||
- cpu-offset : per-cpu offset used when the timer is accessed without the
|
||||
CPU remapping facilities. The offset is cpu-offset * cpu-nr.
|
||||
|
||||
Example:
|
||||
|
||||
timer@200a004 {
|
||||
compatible = "qcom,msm-gpt", "qcom,msm-timer";
|
||||
interrupts = <1 2 0x301>;
|
||||
reg = <0x0200a004 0x10>;
|
||||
clock-frequency = <32768>;
|
||||
cpu-offset = <0x40000>;
|
||||
};
|
||||
|
||||
timer@200a024 {
|
||||
compatible = "qcom,msm-dgt", "qcom,msm-timer";
|
||||
interrupts = <1 3 0x301>;
|
||||
reg = <0x0200a024 0x10>,
|
||||
<0x0200a034 0x4>;
|
||||
clock-frequency = <6750000>;
|
||||
cpu-offset = <0x40000>;
|
||||
};
|
||||
@ -36,6 +36,9 @@ Boards:
|
||||
- OMAP3 BeagleBoard : Low cost community board
|
||||
compatible = "ti,omap3-beagle", "ti,omap3"
|
||||
|
||||
- OMAP3 Tobi with Overo : Commercial expansion board with daughter board
|
||||
compatible = "ti,omap3-tobi", "ti,omap3-overo", "ti,omap3"
|
||||
|
||||
- OMAP4 SDP : Software Developement Board
|
||||
compatible = "ti,omap4-sdp", "ti,omap4430"
|
||||
|
||||
|
||||
76
Documentation/devicetree/bindings/clock/imx23-clock.txt
Normal file
76
Documentation/devicetree/bindings/clock/imx23-clock.txt
Normal file
@ -0,0 +1,76 @@
|
||||
* Clock bindings for Freescale i.MX23
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "fsl,imx23-clkctrl"
|
||||
- reg: Address and length of the register set
|
||||
- #clock-cells: Should be <1>
|
||||
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. The following is a full list of i.MX23
|
||||
clocks and IDs.
|
||||
|
||||
Clock ID
|
||||
------------------
|
||||
ref_xtal 0
|
||||
pll 1
|
||||
ref_cpu 2
|
||||
ref_emi 3
|
||||
ref_pix 4
|
||||
ref_io 5
|
||||
saif_sel 6
|
||||
lcdif_sel 7
|
||||
gpmi_sel 8
|
||||
ssp_sel 9
|
||||
emi_sel 10
|
||||
cpu 11
|
||||
etm_sel 12
|
||||
cpu_pll 13
|
||||
cpu_xtal 14
|
||||
hbus 15
|
||||
xbus 16
|
||||
lcdif_div 17
|
||||
ssp_div 18
|
||||
gpmi_div 19
|
||||
emi_pll 20
|
||||
emi_xtal 21
|
||||
etm_div 22
|
||||
saif_div 23
|
||||
clk32k_div 24
|
||||
rtc 25
|
||||
adc 26
|
||||
spdif_div 27
|
||||
clk32k 28
|
||||
dri 29
|
||||
pwm 30
|
||||
filt 31
|
||||
uart 32
|
||||
ssp 33
|
||||
gpmi 34
|
||||
spdif 35
|
||||
emi 36
|
||||
saif 37
|
||||
lcdif 38
|
||||
etm 39
|
||||
usb 40
|
||||
usb_pwr 41
|
||||
|
||||
Examples:
|
||||
|
||||
clks: clkctrl@80040000 {
|
||||
compatible = "fsl,imx23-clkctrl";
|
||||
reg = <0x80040000 0x2000>;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names =
|
||||
...
|
||||
"uart", /* 32 */
|
||||
...
|
||||
"end_of_list";
|
||||
};
|
||||
|
||||
auart0: serial@8006c000 {
|
||||
compatible = "fsl,imx23-auart";
|
||||
reg = <0x8006c000 0x2000>;
|
||||
interrupts = <24 25 23>;
|
||||
clocks = <&clks 32>;
|
||||
status = "disabled";
|
||||
};
|
||||
99
Documentation/devicetree/bindings/clock/imx28-clock.txt
Normal file
99
Documentation/devicetree/bindings/clock/imx28-clock.txt
Normal file
@ -0,0 +1,99 @@
|
||||
* Clock bindings for Freescale i.MX28
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "fsl,imx28-clkctrl"
|
||||
- reg: Address and length of the register set
|
||||
- #clock-cells: Should be <1>
|
||||
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. The following is a full list of i.MX28
|
||||
clocks and IDs.
|
||||
|
||||
Clock ID
|
||||
------------------
|
||||
ref_xtal 0
|
||||
pll0 1
|
||||
pll1 2
|
||||
pll2 3
|
||||
ref_cpu 4
|
||||
ref_emi 5
|
||||
ref_io0 6
|
||||
ref_io1 7
|
||||
ref_pix 8
|
||||
ref_hsadc 9
|
||||
ref_gpmi 10
|
||||
saif0_sel 11
|
||||
saif1_sel 12
|
||||
gpmi_sel 13
|
||||
ssp0_sel 14
|
||||
ssp1_sel 15
|
||||
ssp2_sel 16
|
||||
ssp3_sel 17
|
||||
emi_sel 18
|
||||
etm_sel 19
|
||||
lcdif_sel 20
|
||||
cpu 21
|
||||
ptp_sel 22
|
||||
cpu_pll 23
|
||||
cpu_xtal 24
|
||||
hbus 25
|
||||
xbus 26
|
||||
ssp0_div 27
|
||||
ssp1_div 28
|
||||
ssp2_div 29
|
||||
ssp3_div 30
|
||||
gpmi_div 31
|
||||
emi_pll 32
|
||||
emi_xtal 33
|
||||
lcdif_div 34
|
||||
etm_div 35
|
||||
ptp 36
|
||||
saif0_div 37
|
||||
saif1_div 38
|
||||
clk32k_div 39
|
||||
rtc 40
|
||||
lradc 41
|
||||
spdif_div 42
|
||||
clk32k 43
|
||||
pwm 44
|
||||
uart 45
|
||||
ssp0 46
|
||||
ssp1 47
|
||||
ssp2 48
|
||||
ssp3 49
|
||||
gpmi 50
|
||||
spdif 51
|
||||
emi 52
|
||||
saif0 53
|
||||
saif1 54
|
||||
lcdif 55
|
||||
etm 56
|
||||
fec 57
|
||||
can0 58
|
||||
can1 59
|
||||
usb0 60
|
||||
usb1 61
|
||||
usb0_pwr 62
|
||||
usb1_pwr 63
|
||||
enet_out 64
|
||||
|
||||
Examples:
|
||||
|
||||
clks: clkctrl@80040000 {
|
||||
compatible = "fsl,imx28-clkctrl";
|
||||
reg = <0x80040000 0x2000>;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names =
|
||||
...
|
||||
"uart", /* 45 */
|
||||
...
|
||||
"end_of_list";
|
||||
};
|
||||
|
||||
auart0: serial@8006a000 {
|
||||
compatible = "fsl,imx28-auart", "fsl,imx23-auart";
|
||||
reg = <0x8006a000 0x2000>;
|
||||
interrupts = <112 70 71>;
|
||||
clocks = <&clks 45>;
|
||||
status = "disabled";
|
||||
};
|
||||
222
Documentation/devicetree/bindings/clock/imx6q-clock.txt
Normal file
222
Documentation/devicetree/bindings/clock/imx6q-clock.txt
Normal file
@ -0,0 +1,222 @@
|
||||
* Clock bindings for Freescale i.MX6 Quad
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "fsl,imx6q-ccm"
|
||||
- reg: Address and length of the register set
|
||||
- interrupts: Should contain CCM interrupt
|
||||
- #clock-cells: Should be <1>
|
||||
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. The following is a full list of i.MX6Q
|
||||
clocks and IDs.
|
||||
|
||||
Clock ID
|
||||
---------------------------
|
||||
dummy 0
|
||||
ckil 1
|
||||
ckih 2
|
||||
osc 3
|
||||
pll2_pfd0_352m 4
|
||||
pll2_pfd1_594m 5
|
||||
pll2_pfd2_396m 6
|
||||
pll3_pfd0_720m 7
|
||||
pll3_pfd1_540m 8
|
||||
pll3_pfd2_508m 9
|
||||
pll3_pfd3_454m 10
|
||||
pll2_198m 11
|
||||
pll3_120m 12
|
||||
pll3_80m 13
|
||||
pll3_60m 14
|
||||
twd 15
|
||||
step 16
|
||||
pll1_sw 17
|
||||
periph_pre 18
|
||||
periph2_pre 19
|
||||
periph_clk2_sel 20
|
||||
periph2_clk2_sel 21
|
||||
axi_sel 22
|
||||
esai_sel 23
|
||||
asrc_sel 24
|
||||
spdif_sel 25
|
||||
gpu2d_axi 26
|
||||
gpu3d_axi 27
|
||||
gpu2d_core_sel 28
|
||||
gpu3d_core_sel 29
|
||||
gpu3d_shader_sel 30
|
||||
ipu1_sel 31
|
||||
ipu2_sel 32
|
||||
ldb_di0_sel 33
|
||||
ldb_di1_sel 34
|
||||
ipu1_di0_pre_sel 35
|
||||
ipu1_di1_pre_sel 36
|
||||
ipu2_di0_pre_sel 37
|
||||
ipu2_di1_pre_sel 38
|
||||
ipu1_di0_sel 39
|
||||
ipu1_di1_sel 40
|
||||
ipu2_di0_sel 41
|
||||
ipu2_di1_sel 42
|
||||
hsi_tx_sel 43
|
||||
pcie_axi_sel 44
|
||||
ssi1_sel 45
|
||||
ssi2_sel 46
|
||||
ssi3_sel 47
|
||||
usdhc1_sel 48
|
||||
usdhc2_sel 49
|
||||
usdhc3_sel 50
|
||||
usdhc4_sel 51
|
||||
enfc_sel 52
|
||||
emi_sel 53
|
||||
emi_slow_sel 54
|
||||
vdo_axi_sel 55
|
||||
vpu_axi_sel 56
|
||||
cko1_sel 57
|
||||
periph 58
|
||||
periph2 59
|
||||
periph_clk2 60
|
||||
periph2_clk2 61
|
||||
ipg 62
|
||||
ipg_per 63
|
||||
esai_pred 64
|
||||
esai_podf 65
|
||||
asrc_pred 66
|
||||
asrc_podf 67
|
||||
spdif_pred 68
|
||||
spdif_podf 69
|
||||
can_root 70
|
||||
ecspi_root 71
|
||||
gpu2d_core_podf 72
|
||||
gpu3d_core_podf 73
|
||||
gpu3d_shader 74
|
||||
ipu1_podf 75
|
||||
ipu2_podf 76
|
||||
ldb_di0_podf 77
|
||||
ldb_di1_podf 78
|
||||
ipu1_di0_pre 79
|
||||
ipu1_di1_pre 80
|
||||
ipu2_di0_pre 81
|
||||
ipu2_di1_pre 82
|
||||
hsi_tx_podf 83
|
||||
ssi1_pred 84
|
||||
ssi1_podf 85
|
||||
ssi2_pred 86
|
||||
ssi2_podf 87
|
||||
ssi3_pred 88
|
||||
ssi3_podf 89
|
||||
uart_serial_podf 90
|
||||
usdhc1_podf 91
|
||||
usdhc2_podf 92
|
||||
usdhc3_podf 93
|
||||
usdhc4_podf 94
|
||||
enfc_pred 95
|
||||
enfc_podf 96
|
||||
emi_podf 97
|
||||
emi_slow_podf 98
|
||||
vpu_axi_podf 99
|
||||
cko1_podf 100
|
||||
axi 101
|
||||
mmdc_ch0_axi_podf 102
|
||||
mmdc_ch1_axi_podf 103
|
||||
arm 104
|
||||
ahb 105
|
||||
apbh_dma 106
|
||||
asrc 107
|
||||
can1_ipg 108
|
||||
can1_serial 109
|
||||
can2_ipg 110
|
||||
can2_serial 111
|
||||
ecspi1 112
|
||||
ecspi2 113
|
||||
ecspi3 114
|
||||
ecspi4 115
|
||||
ecspi5 116
|
||||
enet 117
|
||||
esai 118
|
||||
gpt_ipg 119
|
||||
gpt_ipg_per 120
|
||||
gpu2d_core 121
|
||||
gpu3d_core 122
|
||||
hdmi_iahb 123
|
||||
hdmi_isfr 124
|
||||
i2c1 125
|
||||
i2c2 126
|
||||
i2c3 127
|
||||
iim 128
|
||||
enfc 129
|
||||
ipu1 130
|
||||
ipu1_di0 131
|
||||
ipu1_di1 132
|
||||
ipu2 133
|
||||
ipu2_di0 134
|
||||
ldb_di0 135
|
||||
ldb_di1 136
|
||||
ipu2_di1 137
|
||||
hsi_tx 138
|
||||
mlb 139
|
||||
mmdc_ch0_axi 140
|
||||
mmdc_ch1_axi 141
|
||||
ocram 142
|
||||
openvg_axi 143
|
||||
pcie_axi 144
|
||||
pwm1 145
|
||||
pwm2 146
|
||||
pwm3 147
|
||||
pwm4 148
|
||||
per1_bch 149
|
||||
gpmi_bch_apb 150
|
||||
gpmi_bch 151
|
||||
gpmi_io 152
|
||||
gpmi_apb 153
|
||||
sata 154
|
||||
sdma 155
|
||||
spba 156
|
||||
ssi1 157
|
||||
ssi2 158
|
||||
ssi3 159
|
||||
uart_ipg 160
|
||||
uart_serial 161
|
||||
usboh3 162
|
||||
usdhc1 163
|
||||
usdhc2 164
|
||||
usdhc3 165
|
||||
usdhc4 166
|
||||
vdo_axi 167
|
||||
vpu_axi 168
|
||||
cko1 169
|
||||
pll1_sys 170
|
||||
pll2_bus 171
|
||||
pll3_usb_otg 172
|
||||
pll4_audio 173
|
||||
pll5_video 174
|
||||
pll6_mlb 175
|
||||
pll7_usb_host 176
|
||||
pll8_enet 177
|
||||
ssi1_ipg 178
|
||||
ssi2_ipg 179
|
||||
ssi3_ipg 180
|
||||
rom 181
|
||||
usbphy1 182
|
||||
usbphy2 183
|
||||
ldb_di0_div_3_5 184
|
||||
ldb_di1_div_3_5 185
|
||||
|
||||
Examples:
|
||||
|
||||
clks: ccm@020c4000 {
|
||||
compatible = "fsl,imx6q-ccm";
|
||||
reg = <0x020c4000 0x4000>;
|
||||
interrupts = <0 87 0x04 0 88 0x04>;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = ...
|
||||
"uart_ipg",
|
||||
"uart_serial",
|
||||
...;
|
||||
};
|
||||
|
||||
uart1: serial@02020000 {
|
||||
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
|
||||
reg = <0x02020000 0x4000>;
|
||||
interrupts = <0 26 0x04>;
|
||||
clocks = <&clks 160>, <&clks 161>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
@ -39,3 +39,46 @@ Example:
|
||||
#gpio-cells = <4>;
|
||||
gpio-controller;
|
||||
};
|
||||
|
||||
|
||||
Samsung S3C24XX GPIO Controller
|
||||
|
||||
Required properties:
|
||||
- compatible: Compatible property value should be "samsung,s3c24xx-gpio".
|
||||
|
||||
- reg: Physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
|
||||
- #gpio-cells: Should be 3. The syntax of the gpio specifier used by client nodes
|
||||
should be the following with values derived from the SoC user manual.
|
||||
<[phandle of the gpio controller node]
|
||||
[pin number within the gpio controller]
|
||||
[mux function]
|
||||
[flags and pull up/down]
|
||||
|
||||
Values for gpio specifier:
|
||||
- Pin number: depending on the controller a number from 0 up to 15.
|
||||
- Mux function: Depending on the SoC and the gpio bank the gpio can be set
|
||||
as input, output or a special function
|
||||
- Flags and Pull Up/Down: the values to use differ for the individual SoCs
|
||||
example S3C2416/S3C2450:
|
||||
0 - Pull Up/Down Disabled.
|
||||
1 - Pull Down Enabled.
|
||||
2 - Pull Up Enabled.
|
||||
Bit 16 (0x00010000) - Input is active low.
|
||||
Consult the user manual for the correct values of Mux and Pull Up/Down.
|
||||
|
||||
- gpio-controller: Specifies that the node is a gpio controller.
|
||||
- #address-cells: should be 1.
|
||||
- #size-cells: should be 1.
|
||||
|
||||
Example:
|
||||
|
||||
gpa: gpio-controller@56000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "samsung,s3c24xx-gpio";
|
||||
reg = <0x56000000 0x10>;
|
||||
#gpio-cells = <3>;
|
||||
gpio-controller;
|
||||
};
|
||||
|
||||
@ -11,6 +11,11 @@ Required properties:
|
||||
- interrupt-controller: Mark the device node as an interrupt controller
|
||||
The first cell is the GPIO number.
|
||||
The second cell is not used.
|
||||
- ti,use-leds : Enables LEDA and LEDB outputs if set
|
||||
- ti,debounce : if n-th bit is set, debounces GPIO-n
|
||||
- ti,mmc-cd : if n-th bit is set, GPIO-n controls VMMC(n+1)
|
||||
- ti,pullups : if n-th bit is set, set a pullup on GPIO-n
|
||||
- ti,pulldowns : if n-th bit is set, set a pulldown on GPIO-n
|
||||
|
||||
Example:
|
||||
|
||||
@ -20,4 +25,5 @@ twl_gpio: gpio {
|
||||
gpio-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
ti,use-leds;
|
||||
};
|
||||
|
||||
@ -56,3 +56,4 @@ stm,m41t00 Serial Access TIMEKEEPER
|
||||
stm,m41t62 Serial real-time clock (RTC) with alarm
|
||||
stm,m41t80 M41T80 - SERIAL ACCESS RTC WITH ALARMS
|
||||
ti,tsc2003 I2C Touch-Screen Controller
|
||||
ti,tmp102 Low Power Digital Temperature Sensor with SMBUS/Two Wire Serial Interface
|
||||
|
||||
52
Documentation/devicetree/bindings/lpddr2/lpddr2-timings.txt
Normal file
52
Documentation/devicetree/bindings/lpddr2/lpddr2-timings.txt
Normal file
@ -0,0 +1,52 @@
|
||||
* AC timing parameters of LPDDR2(JESD209-2) memories for a given speed-bin
|
||||
|
||||
Required properties:
|
||||
- compatible : Should be "jedec,lpddr2-timings"
|
||||
- min-freq : minimum DDR clock frequency for the speed-bin. Type is <u32>
|
||||
- max-freq : maximum DDR clock frequency for the speed-bin. Type is <u32>
|
||||
|
||||
Optional properties:
|
||||
|
||||
The following properties represent AC timing parameters from the memory
|
||||
data-sheet of the device for a given speed-bin. All these properties are
|
||||
of type <u32> and the default unit is ps (pico seconds). Parameters with
|
||||
a different unit have a suffix indicating the unit such as 'tRAS-max-ns'
|
||||
- tRCD
|
||||
- tWR
|
||||
- tRAS-min
|
||||
- tRRD
|
||||
- tWTR
|
||||
- tXP
|
||||
- tRTP
|
||||
- tDQSCK-max
|
||||
- tFAW
|
||||
- tZQCS
|
||||
- tZQinit
|
||||
- tRPab
|
||||
- tZQCL
|
||||
- tCKESR
|
||||
- tRAS-max-ns
|
||||
- tDQSCK-max-derated
|
||||
|
||||
Example:
|
||||
|
||||
timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 {
|
||||
compatible = "jedec,lpddr2-timings";
|
||||
min-freq = <10000000>;
|
||||
max-freq = <400000000>;
|
||||
tRPab = <21000>;
|
||||
tRCD = <18000>;
|
||||
tWR = <15000>;
|
||||
tRAS-min = <42000>;
|
||||
tRRD = <10000>;
|
||||
tWTR = <7500>;
|
||||
tXP = <7500>;
|
||||
tRTP = <7500>;
|
||||
tCKESR = <15000>;
|
||||
tDQSCK-max = <5500>;
|
||||
tFAW = <50000>;
|
||||
tZQCS = <90000>;
|
||||
tZQCL = <360000>;
|
||||
tZQinit = <1000000>;
|
||||
tRAS-max-ns = <70000>;
|
||||
};
|
||||
102
Documentation/devicetree/bindings/lpddr2/lpddr2.txt
Normal file
102
Documentation/devicetree/bindings/lpddr2/lpddr2.txt
Normal file
@ -0,0 +1,102 @@
|
||||
* LPDDR2 SDRAM memories compliant to JEDEC JESD209-2
|
||||
|
||||
Required properties:
|
||||
- compatible : Should be one of - "jedec,lpddr2-nvm", "jedec,lpddr2-s2",
|
||||
"jedec,lpddr2-s4"
|
||||
|
||||
"ti,jedec-lpddr2-s2" should be listed if the memory part is LPDDR2-S2 type
|
||||
|
||||
"ti,jedec-lpddr2-s4" should be listed if the memory part is LPDDR2-S4 type
|
||||
|
||||
"ti,jedec-lpddr2-nvm" should be listed if the memory part is LPDDR2-NVM type
|
||||
|
||||
- density : <u32> representing density in Mb (Mega bits)
|
||||
|
||||
- io-width : <u32> representing bus width. Possible values are 8, 16, and 32
|
||||
|
||||
Optional properties:
|
||||
|
||||
The following optional properties represent the minimum value of some AC
|
||||
timing parameters of the DDR device in terms of number of clock cycles.
|
||||
These values shall be obtained from the device data-sheet.
|
||||
- tRRD-min-tck
|
||||
- tWTR-min-tck
|
||||
- tXP-min-tck
|
||||
- tRTP-min-tck
|
||||
- tCKE-min-tck
|
||||
- tRPab-min-tck
|
||||
- tRCD-min-tck
|
||||
- tWR-min-tck
|
||||
- tRASmin-min-tck
|
||||
- tCKESR-min-tck
|
||||
- tFAW-min-tck
|
||||
|
||||
Child nodes:
|
||||
- The lpddr2 node may have one or more child nodes of type "lpddr2-timings".
|
||||
"lpddr2-timings" provides AC timing parameters of the device for
|
||||
a given speed-bin. The user may provide the timings for as many
|
||||
speed-bins as is required. Please see Documentation/devicetree/
|
||||
bindings/lpddr2/lpddr2-timings.txt for more information on "lpddr2-timings"
|
||||
|
||||
Example:
|
||||
|
||||
elpida_ECB240ABACN : lpddr2 {
|
||||
compatible = "Elpida,ECB240ABACN","jedec,lpddr2-s4";
|
||||
density = <2048>;
|
||||
io-width = <32>;
|
||||
|
||||
tRPab-min-tck = <3>;
|
||||
tRCD-min-tck = <3>;
|
||||
tWR-min-tck = <3>;
|
||||
tRASmin-min-tck = <3>;
|
||||
tRRD-min-tck = <2>;
|
||||
tWTR-min-tck = <2>;
|
||||
tXP-min-tck = <2>;
|
||||
tRTP-min-tck = <2>;
|
||||
tCKE-min-tck = <3>;
|
||||
tCKESR-min-tck = <3>;
|
||||
tFAW-min-tck = <8>;
|
||||
|
||||
timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 {
|
||||
compatible = "jedec,lpddr2-timings";
|
||||
min-freq = <10000000>;
|
||||
max-freq = <400000000>;
|
||||
tRPab = <21000>;
|
||||
tRCD = <18000>;
|
||||
tWR = <15000>;
|
||||
tRAS-min = <42000>;
|
||||
tRRD = <10000>;
|
||||
tWTR = <7500>;
|
||||
tXP = <7500>;
|
||||
tRTP = <7500>;
|
||||
tCKESR = <15000>;
|
||||
tDQSCK-max = <5500>;
|
||||
tFAW = <50000>;
|
||||
tZQCS = <90000>;
|
||||
tZQCL = <360000>;
|
||||
tZQinit = <1000000>;
|
||||
tRAS-max-ns = <70000>;
|
||||
};
|
||||
|
||||
timings_elpida_ECB240ABACN_200mhz: lpddr2-timings@1 {
|
||||
compatible = "jedec,lpddr2-timings";
|
||||
min-freq = <10000000>;
|
||||
max-freq = <200000000>;
|
||||
tRPab = <21000>;
|
||||
tRCD = <18000>;
|
||||
tWR = <15000>;
|
||||
tRAS-min = <42000>;
|
||||
tRRD = <10000>;
|
||||
tWTR = <10000>;
|
||||
tXP = <7500>;
|
||||
tRTP = <7500>;
|
||||
tCKESR = <15000>;
|
||||
tDQSCK-max = <5500>;
|
||||
tFAW = <50000>;
|
||||
tZQCS = <90000>;
|
||||
tZQCL = <360000>;
|
||||
tZQinit = <1000000>;
|
||||
tRAS-max-ns = <70000>;
|
||||
};
|
||||
|
||||
}
|
||||
@ -0,0 +1,55 @@
|
||||
* EMIF family of TI SDRAM controllers
|
||||
|
||||
EMIF - External Memory Interface - is an SDRAM controller used in
|
||||
TI SoCs. EMIF supports, based on the IP revision, one or more of
|
||||
DDR2/DDR3/LPDDR2 protocols. This binding describes a given instance
|
||||
of the EMIF IP and memory parts attached to it.
|
||||
|
||||
Required properties:
|
||||
- compatible : Should be of the form "ti,emif-<ip-rev>" where <ip-rev>
|
||||
is the IP revision of the specific EMIF instance.
|
||||
|
||||
- phy-type : <u32> indicating the DDR phy type. Following are the
|
||||
allowed values
|
||||
<1> : Attila PHY
|
||||
<2> : Intelli PHY
|
||||
|
||||
- device-handle : phandle to a "lpddr2" node representing the memory part
|
||||
|
||||
- ti,hwmods : For TI hwmods processing and omap device creation
|
||||
the value shall be "emif<n>" where <n> is the number of the EMIF
|
||||
instance with base 1.
|
||||
|
||||
Optional properties:
|
||||
- cs1-used : Have this property if CS1 of this EMIF
|
||||
instance has a memory part attached to it. If there is a memory
|
||||
part attached to CS1, it should be the same type as the one on CS0,
|
||||
so there is no need to give the details of this memory part.
|
||||
|
||||
- cal-resistor-per-cs : Have this property if the board has one
|
||||
calibration resistor per chip-select.
|
||||
|
||||
- hw-caps-read-idle-ctrl: Have this property if the controller
|
||||
supports read idle window programming
|
||||
|
||||
- hw-caps-dll-calib-ctrl: Have this property if the controller
|
||||
supports dll calibration control
|
||||
|
||||
- hw-caps-ll-interface : Have this property if the controller
|
||||
has a low latency interface and corresponding interrupt events
|
||||
|
||||
- hw-caps-temp-alert : Have this property if the controller
|
||||
has capability for generating SDRAM temperature alerts
|
||||
|
||||
Example:
|
||||
|
||||
emif1: emif@0x4c000000 {
|
||||
compatible = "ti,emif-4d";
|
||||
ti,hwmods = "emif2";
|
||||
phy-type = <1>;
|
||||
device-handle = <&elpida_ECB240ABACN>;
|
||||
cs1-used;
|
||||
hw-caps-read-idle-ctrl;
|
||||
hw-caps-ll-interface;
|
||||
hw-caps-temp-alert;
|
||||
};
|
||||
31
Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt
Normal file
31
Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt
Normal file
@ -0,0 +1,31 @@
|
||||
PXA3xx NAND DT bindings
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: Should be "marvell,pxa3xx-nand"
|
||||
- reg: The register base for the controller
|
||||
- interrupts: The interrupt to map
|
||||
- #address-cells: Set to <1> if the node includes partitions
|
||||
|
||||
Optional properties:
|
||||
|
||||
- marvell,nand-enable-arbiter: Set to enable the bus arbiter
|
||||
- marvell,nand-keep-config: Set to keep the NAND controller config as set
|
||||
by the bootloader
|
||||
- num-cs: Number of chipselect lines to usw
|
||||
|
||||
Example:
|
||||
|
||||
nand0: nand@43100000 {
|
||||
compatible = "marvell,pxa3xx-nand";
|
||||
reg = <0x43100000 90>;
|
||||
interrupts = <45>;
|
||||
#address-cells = <1>;
|
||||
|
||||
marvell,nand-enable-arbiter;
|
||||
marvell,nand-keep-config;
|
||||
num-cs = <1>;
|
||||
|
||||
/* partitions (optional) */
|
||||
};
|
||||
|
||||
14
Documentation/devicetree/bindings/rtc/pxa-rtc.txt
Normal file
14
Documentation/devicetree/bindings/rtc/pxa-rtc.txt
Normal file
@ -0,0 +1,14 @@
|
||||
* PXA RTC
|
||||
|
||||
PXA specific RTC driver.
|
||||
|
||||
Required properties:
|
||||
- compatible : Should be "marvell,pxa-rtc"
|
||||
|
||||
Examples:
|
||||
|
||||
rtc@40900000 {
|
||||
compatible = "marvell,pxa-rtc";
|
||||
reg = <0x40900000 0x3c>;
|
||||
interrupts = <30 31>;
|
||||
};
|
||||
@ -273,7 +273,7 @@ config ARCH_INTEGRATOR
|
||||
select ARM_AMBA
|
||||
select ARCH_HAS_CPUFREQ
|
||||
select COMMON_CLK
|
||||
select CLK_VERSATILE
|
||||
select COMMON_CLK_VERSATILE
|
||||
select HAVE_TCM
|
||||
select ICST
|
||||
select GENERIC_CLOCKEVENTS
|
||||
@ -288,13 +288,12 @@ config ARCH_INTEGRATOR
|
||||
config ARCH_REALVIEW
|
||||
bool "ARM Ltd. RealView family"
|
||||
select ARM_AMBA
|
||||
select CLKDEV_LOOKUP
|
||||
select HAVE_MACH_CLKDEV
|
||||
select COMMON_CLK
|
||||
select COMMON_CLK_VERSATILE
|
||||
select ICST
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select ARCH_WANT_OPTIONAL_GPIOLIB
|
||||
select PLAT_VERSATILE
|
||||
select PLAT_VERSATILE_CLOCK
|
||||
select PLAT_VERSATILE_CLCD
|
||||
select ARM_TIMER_SP804
|
||||
select GPIO_PL061 if GPIOLIB
|
||||
|
||||
@ -17,4 +17,64 @@
|
||||
device_type = "memory";
|
||||
reg = <0x80000000 0x10000000>; /* 256 MB */
|
||||
};
|
||||
|
||||
ocp {
|
||||
uart1: serial@44e09000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2c1: i2c@44e0b000 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
tps: tps@24 {
|
||||
reg = <0x24>;
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "tps65217.dtsi"
|
||||
|
||||
&tps {
|
||||
regulators {
|
||||
dcdc1_reg: regulator@0 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
dcdc2_reg: regulator@1 {
|
||||
/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
|
||||
regulator-name = "vdd_mpu";
|
||||
regulator-min-microvolt = <925000>;
|
||||
regulator-max-microvolt = <1325000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
dcdc3_reg: regulator@2 {
|
||||
/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
|
||||
regulator-name = "vdd_core";
|
||||
regulator-min-microvolt = <925000>;
|
||||
regulator-max-microvolt = <1150000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo1_reg: regulator@3 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo2_reg: regulator@4 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo3_reg: regulator@5 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo4_reg: regulator@6 {
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -17,4 +17,104 @@
|
||||
device_type = "memory";
|
||||
reg = <0x80000000 0x10000000>; /* 256 MB */
|
||||
};
|
||||
|
||||
ocp {
|
||||
uart1: serial@44e09000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2c1: i2c@44e0b000 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
tps: tps@2d {
|
||||
reg = <0x2d>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
vbat: fixedregulator@0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vbat";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-boot-on;
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "tps65910.dtsi"
|
||||
|
||||
&tps {
|
||||
vcc1-supply = <&vbat>;
|
||||
vcc2-supply = <&vbat>;
|
||||
vcc3-supply = <&vbat>;
|
||||
vcc4-supply = <&vbat>;
|
||||
vcc5-supply = <&vbat>;
|
||||
vcc6-supply = <&vbat>;
|
||||
vcc7-supply = <&vbat>;
|
||||
vccio-supply = <&vbat>;
|
||||
|
||||
regulators {
|
||||
vrtc_reg: regulator@0 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vio_reg: regulator@1 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdd1_reg: regulator@2 {
|
||||
/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
|
||||
regulator-name = "vdd_mpu";
|
||||
regulator-min-microvolt = <912500>;
|
||||
regulator-max-microvolt = <1312500>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdd2_reg: regulator@3 {
|
||||
/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
|
||||
regulator-name = "vdd_core";
|
||||
regulator-min-microvolt = <912500>;
|
||||
regulator-max-microvolt = <1150000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdd3_reg: regulator@4 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdig1_reg: regulator@5 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdig2_reg: regulator@6 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vpll_reg: regulator@7 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdac_reg: regulator@8 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vaux1_reg: regulator@9 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vaux2_reg: regulator@10 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vaux33_reg: regulator@11 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vmmc_reg: regulator@12 {
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -69,95 +69,146 @@
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
reg = <0x44e07000 0x1000>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <96>;
|
||||
};
|
||||
|
||||
gpio2: gpio@4804C000 {
|
||||
gpio2: gpio@4804c000 {
|
||||
compatible = "ti,omap4-gpio";
|
||||
ti,hwmods = "gpio2";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
reg = <0x4804c000 0x1000>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <98>;
|
||||
};
|
||||
|
||||
gpio3: gpio@481AC000 {
|
||||
gpio3: gpio@481ac000 {
|
||||
compatible = "ti,omap4-gpio";
|
||||
ti,hwmods = "gpio3";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
reg = <0x481ac000 0x1000>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <32>;
|
||||
};
|
||||
|
||||
gpio4: gpio@481AE000 {
|
||||
gpio4: gpio@481ae000 {
|
||||
compatible = "ti,omap4-gpio";
|
||||
ti,hwmods = "gpio4";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
reg = <0x481ae000 0x1000>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <62>;
|
||||
};
|
||||
|
||||
uart1: serial@44E09000 {
|
||||
uart1: serial@44e09000 {
|
||||
compatible = "ti,omap3-uart";
|
||||
ti,hwmods = "uart1";
|
||||
clock-frequency = <48000000>;
|
||||
reg = <0x44e09000 0x2000>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <72>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@48022000 {
|
||||
compatible = "ti,omap3-uart";
|
||||
ti,hwmods = "uart2";
|
||||
clock-frequency = <48000000>;
|
||||
reg = <0x48022000 0x2000>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <73>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: serial@48024000 {
|
||||
compatible = "ti,omap3-uart";
|
||||
ti,hwmods = "uart3";
|
||||
clock-frequency = <48000000>;
|
||||
reg = <0x48024000 0x2000>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <74>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart4: serial@481A6000 {
|
||||
uart4: serial@481a6000 {
|
||||
compatible = "ti,omap3-uart";
|
||||
ti,hwmods = "uart4";
|
||||
clock-frequency = <48000000>;
|
||||
reg = <0x481a6000 0x2000>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <44>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart5: serial@481A8000 {
|
||||
uart5: serial@481a8000 {
|
||||
compatible = "ti,omap3-uart";
|
||||
ti,hwmods = "uart5";
|
||||
clock-frequency = <48000000>;
|
||||
reg = <0x481a8000 0x2000>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <45>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart6: serial@481AA000 {
|
||||
uart6: serial@481aa000 {
|
||||
compatible = "ti,omap3-uart";
|
||||
ti,hwmods = "uart6";
|
||||
clock-frequency = <48000000>;
|
||||
reg = <0x481aa000 0x2000>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <46>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@44E0B000 {
|
||||
i2c1: i2c@44e0b000 {
|
||||
compatible = "ti,omap4-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
ti,hwmods = "i2c1";
|
||||
reg = <0x44e0b000 0x1000>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <70>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c@4802A000 {
|
||||
i2c2: i2c@4802a000 {
|
||||
compatible = "ti,omap4-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
ti,hwmods = "i2c2";
|
||||
reg = <0x4802a000 0x1000>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <71>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c3: i2c@4819C000 {
|
||||
i2c3: i2c@4819c000 {
|
||||
compatible = "ti,omap4-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
ti,hwmods = "i2c3";
|
||||
reg = <0x4819c000 0x1000>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <30>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wdt2: wdt@44e35000 {
|
||||
compatible = "ti,omap3-wdt";
|
||||
ti,hwmods = "wd_timer2";
|
||||
reg = <0x44e35000 0x1000>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <91>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -166,9 +166,116 @@
|
||||
#size-cells = <0>;
|
||||
autorepeat;
|
||||
button@21 {
|
||||
label = "GPIO Key UP";
|
||||
label = "Interrupt Key";
|
||||
linux,code = <103>;
|
||||
gpios = <&gpio 4 1 0>; /* GPI_P3 1 */
|
||||
};
|
||||
key1 {
|
||||
label = "KEY1";
|
||||
linux,code = <1>;
|
||||
gpios = <&pca9532 0 0>;
|
||||
};
|
||||
key2 {
|
||||
label = "KEY2";
|
||||
linux,code = <2>;
|
||||
gpios = <&pca9532 1 0>;
|
||||
};
|
||||
key3 {
|
||||
label = "KEY3";
|
||||
linux,code = <3>;
|
||||
gpios = <&pca9532 2 0>;
|
||||
};
|
||||
key4 {
|
||||
label = "KEY4";
|
||||
linux,code = <4>;
|
||||
gpios = <&pca9532 3 0>;
|
||||
};
|
||||
joy0 {
|
||||
label = "Joystick Key 0";
|
||||
linux,code = <10>;
|
||||
gpios = <&gpio 2 0 0>; /* P2.0 */
|
||||
};
|
||||
joy1 {
|
||||
label = "Joystick Key 1";
|
||||
linux,code = <11>;
|
||||
gpios = <&gpio 2 1 0>; /* P2.1 */
|
||||
};
|
||||
joy2 {
|
||||
label = "Joystick Key 2";
|
||||
linux,code = <12>;
|
||||
gpios = <&gpio 2 2 0>; /* P2.2 */
|
||||
};
|
||||
joy3 {
|
||||
label = "Joystick Key 3";
|
||||
linux,code = <13>;
|
||||
gpios = <&gpio 2 3 0>; /* P2.3 */
|
||||
};
|
||||
joy4 {
|
||||
label = "Joystick Key 4";
|
||||
linux,code = <14>;
|
||||
gpios = <&gpio 2 4 0>; /* P2.4 */
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
/* LEDs on OEM Board */
|
||||
|
||||
led1 {
|
||||
gpios = <&gpio 5 14 1>; /* GPO_P3 14, GPIO 93, active low */
|
||||
linux,default-trigger = "timer";
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led2 {
|
||||
gpios = <&gpio 2 10 1>; /* P2.10, active low */
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led3 {
|
||||
gpios = <&gpio 2 11 1>; /* P2.11, active low */
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led4 {
|
||||
gpios = <&gpio 2 12 1>; /* P2.12, active low */
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
/* LEDs on Base Board */
|
||||
|
||||
lede1 {
|
||||
gpios = <&pca9532 8 0>;
|
||||
default-state = "off";
|
||||
};
|
||||
lede2 {
|
||||
gpios = <&pca9532 9 0>;
|
||||
default-state = "off";
|
||||
};
|
||||
lede3 {
|
||||
gpios = <&pca9532 10 0>;
|
||||
default-state = "off";
|
||||
};
|
||||
lede4 {
|
||||
gpios = <&pca9532 11 0>;
|
||||
default-state = "off";
|
||||
};
|
||||
lede5 {
|
||||
gpios = <&pca9532 12 0>;
|
||||
default-state = "off";
|
||||
};
|
||||
lede6 {
|
||||
gpios = <&pca9532 13 0>;
|
||||
default-state = "off";
|
||||
};
|
||||
lede7 {
|
||||
gpios = <&pca9532 14 0>;
|
||||
default-state = "off";
|
||||
};
|
||||
lede8 {
|
||||
gpios = <&pca9532 15 0>;
|
||||
default-state = "off";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
67
arch/arm/boot/dts/elpida_ecb240abacn.dtsi
Normal file
67
arch/arm/boot/dts/elpida_ecb240abacn.dtsi
Normal file
@ -0,0 +1,67 @@
|
||||
/*
|
||||
* Common devices used in different OMAP boards
|
||||
*/
|
||||
|
||||
/ {
|
||||
elpida_ECB240ABACN: lpddr2 {
|
||||
compatible = "Elpida,ECB240ABACN","jedec,lpddr2-s4";
|
||||
density = <2048>;
|
||||
io-width = <32>;
|
||||
|
||||
tRPab-min-tck = <3>;
|
||||
tRCD-min-tck = <3>;
|
||||
tWR-min-tck = <3>;
|
||||
tRASmin-min-tck = <3>;
|
||||
tRRD-min-tck = <2>;
|
||||
tWTR-min-tck = <2>;
|
||||
tXP-min-tck = <2>;
|
||||
tRTP-min-tck = <2>;
|
||||
tCKE-min-tck = <3>;
|
||||
tCKESR-min-tck = <3>;
|
||||
tFAW-min-tck = <8>;
|
||||
|
||||
timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 {
|
||||
compatible = "jedec,lpddr2-timings";
|
||||
min-freq = <10000000>;
|
||||
max-freq = <400000000>;
|
||||
tRPab = <21000>;
|
||||
tRCD = <18000>;
|
||||
tWR = <15000>;
|
||||
tRAS-min = <42000>;
|
||||
tRRD = <10000>;
|
||||
tWTR = <7500>;
|
||||
tXP = <7500>;
|
||||
tRTP = <7500>;
|
||||
tCKESR = <15000>;
|
||||
tDQSCK-max = <5500>;
|
||||
tFAW = <50000>;
|
||||
tZQCS = <90000>;
|
||||
tZQCL = <360000>;
|
||||
tZQinit = <1000000>;
|
||||
tRAS-max-ns = <70000>;
|
||||
tDQSCK-max-derated = <6000>;
|
||||
};
|
||||
|
||||
timings_elpida_ECB240ABACN_200mhz: lpddr2-timings@1 {
|
||||
compatible = "jedec,lpddr2-timings";
|
||||
min-freq = <10000000>;
|
||||
max-freq = <200000000>;
|
||||
tRPab = <21000>;
|
||||
tRCD = <18000>;
|
||||
tWR = <15000>;
|
||||
tRAS-min = <42000>;
|
||||
tRRD = <10000>;
|
||||
tWTR = <10000>;
|
||||
tXP = <7500>;
|
||||
tRTP = <7500>;
|
||||
tCKESR = <15000>;
|
||||
tDQSCK-max = <5500>;
|
||||
tFAW = <50000>;
|
||||
tZQCS = <90000>;
|
||||
tZQCL = <360000>;
|
||||
tZQinit = <1000000>;
|
||||
tRAS-max-ns = <70000>;
|
||||
tDQSCK-max-derated = <6000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -42,12 +42,13 @@
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hog_pins_a>;
|
||||
|
||||
hog_pins_a: hog-gpios@0 {
|
||||
hog_pins_a: hog@0 {
|
||||
reg = <0>;
|
||||
fsl,pinmux-ids = <
|
||||
0x1123 /* MX23_PAD_LCD_RESET__GPIO_1_18 */
|
||||
0x11d3 /* MX23_PAD_PWM3__GPIO_1_29 */
|
||||
0x11e3 /* MX23_PAD_PWM4__GPIO_1_30 */
|
||||
0x2010 /* MX23_PAD_SSP1_DETECT__SSP1_DETECT */
|
||||
>;
|
||||
fsl,drive-strength = <0>;
|
||||
fsl,voltage = <1>;
|
||||
|
||||
@ -31,6 +31,22 @@
|
||||
bus-width = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pinctrl@80018000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hog_pins_a>;
|
||||
|
||||
hog_pins_a: hog@0 {
|
||||
reg = <0>;
|
||||
fsl,pinmux-ids = <
|
||||
0x2013 /* MX23_PAD_SSP1_DETECT__GPIO_2_1 */
|
||||
0x0113 /* MX23_PAD_GPMI_ALE__GPIO_0_17 */
|
||||
>;
|
||||
fsl,drive-strength = <0>;
|
||||
fsl,voltage = <1>;
|
||||
fsl,pull-up = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
apbx@80040000 {
|
||||
@ -39,6 +55,47 @@
|
||||
pinctrl-0 = <&duart_pins_a>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
auart0: serial@8006c000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&auart0_2pins_a>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usbphy0: usbphy@8007c000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ahb@80080000 {
|
||||
usb0: usb@80080000 {
|
||||
vbus-supply = <®_usb0_vbus>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
|
||||
reg_usb0_vbus: usb0_vbus {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "usb0_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
startup-delay-us = <300>; /* LAN9215 requires a POR of 200us minimum */
|
||||
gpio = <&gpio0 17 0>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
user {
|
||||
label = "green";
|
||||
gpios = <&gpio2 1 0>;
|
||||
linux,default-trigger = "default-on";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -36,7 +36,7 @@
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hog_pins_a>;
|
||||
|
||||
hog_pins_a: hog-gpios@0 {
|
||||
hog_pins_a: hog@0 {
|
||||
reg = <0>;
|
||||
fsl,pinmux-ids = <
|
||||
0x11d3 /* MX23_PAD_PWM3__GPIO_1_29 */
|
||||
|
||||
@ -52,6 +52,7 @@
|
||||
dma-apbh@80004000 {
|
||||
compatible = "fsl,imx23-dma-apbh";
|
||||
reg = <0x80004000 0x2000>;
|
||||
clocks = <&clks 15>;
|
||||
};
|
||||
|
||||
ecc@80008000 {
|
||||
@ -67,6 +68,7 @@
|
||||
reg-names = "gpmi-nand", "bch";
|
||||
interrupts = <13>, <56>;
|
||||
interrupt-names = "gpmi-dma", "bch";
|
||||
clocks = <&clks 34>;
|
||||
fsl,gpmi-dma-channel = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
@ -74,6 +76,7 @@
|
||||
ssp0: ssp@80010000 {
|
||||
reg = <0x80010000 0x2000>;
|
||||
interrupts = <15 14>;
|
||||
clocks = <&clks 33>;
|
||||
fsl,ssp-dma-channel = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
@ -140,6 +143,17 @@
|
||||
fsl,pull-up = <0>;
|
||||
};
|
||||
|
||||
auart0_2pins_a: auart0-2pins@0 {
|
||||
reg = <0>;
|
||||
fsl,pinmux-ids = <
|
||||
0x01e2 /* MX23_PAD_I2C_SCL__AUART1_TX */
|
||||
0x01f2 /* MX23_PAD_I2C_SDA__AUART1_RX */
|
||||
>;
|
||||
fsl,drive-strength = <0>;
|
||||
fsl,voltage = <1>;
|
||||
fsl,pull-up = <0>;
|
||||
};
|
||||
|
||||
gpmi_pins_a: gpmi-nand@0 {
|
||||
reg = <0>;
|
||||
fsl,pinmux-ids = <
|
||||
@ -183,7 +197,6 @@
|
||||
0x2040 /* MX23_PAD_SSP1_DATA2__SSP1_DATA2 */
|
||||
0x2050 /* MX23_PAD_SSP1_DATA3__SSP1_DATA3 */
|
||||
0x2000 /* MX23_PAD_SSP1_CMD__SSP1_CMD */
|
||||
0x2010 /* MX23_PAD_SSP1_DETECT__SSP1_DETECT */
|
||||
0x2060 /* MX23_PAD_SSP1_SCK__SSP1_SCK */
|
||||
>;
|
||||
fsl,drive-strength = <1>;
|
||||
@ -280,6 +293,7 @@
|
||||
dma-apbx@80024000 {
|
||||
compatible = "fsl,imx23-dma-apbx";
|
||||
reg = <0x80024000 0x2000>;
|
||||
clocks = <&clks 16>;
|
||||
};
|
||||
|
||||
dcp@80028000 {
|
||||
@ -306,12 +320,14 @@
|
||||
compatible = "fsl,imx23-lcdif";
|
||||
reg = <0x80030000 2000>;
|
||||
interrupts = <46 45>;
|
||||
clocks = <&clks 38>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ssp1: ssp@80034000 {
|
||||
reg = <0x80034000 0x2000>;
|
||||
interrupts = <2 20>;
|
||||
clocks = <&clks 33>;
|
||||
fsl,ssp-dma-channel = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
@ -329,9 +345,10 @@
|
||||
reg = <0x80040000 0x40000>;
|
||||
ranges;
|
||||
|
||||
clkctl@80040000 {
|
||||
clks: clkctrl@80040000 {
|
||||
compatible = "fsl,imx23-clkctrl";
|
||||
reg = <0x80040000 0x2000>;
|
||||
status = "disabled";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
saif0: saif@80042000 {
|
||||
@ -383,6 +400,7 @@
|
||||
pwm: pwm@80064000 {
|
||||
compatible = "fsl,imx23-pwm";
|
||||
reg = <0x80064000 0x2000>;
|
||||
clocks = <&clks 30>;
|
||||
#pwm-cells = <2>;
|
||||
fsl,pwm-number = <5>;
|
||||
status = "disabled";
|
||||
@ -397,6 +415,7 @@
|
||||
compatible = "fsl,imx23-auart";
|
||||
reg = <0x8006c000 0x2000>;
|
||||
interrupts = <24 25 23>;
|
||||
clocks = <&clks 32>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -404,6 +423,7 @@
|
||||
compatible = "fsl,imx23-auart";
|
||||
reg = <0x8006e000 0x2000>;
|
||||
interrupts = <59 60 58>;
|
||||
clocks = <&clks 32>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -411,11 +431,15 @@
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x80070000 0x2000>;
|
||||
interrupts = <0>;
|
||||
clocks = <&clks 32>, <&clks 16>;
|
||||
clock-names = "uart", "apb_pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbphy@8007c000 {
|
||||
usbphy0: usbphy@8007c000 {
|
||||
compatible = "fsl,imx23-usbphy";
|
||||
reg = <0x8007c000 0x2000>;
|
||||
clocks = <&clks 41>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
@ -428,8 +452,12 @@
|
||||
reg = <0x80080000 0x80000>;
|
||||
ranges;
|
||||
|
||||
usbctrl@80080000 {
|
||||
usb0: usb@80080000 {
|
||||
compatible = "fsl,imx23-usb", "fsl,imx27-usb";
|
||||
reg = <0x80080000 0x40000>;
|
||||
interrupts = <11>;
|
||||
fsl,usbphy = <&usbphy0>;
|
||||
clocks = <&clks 40>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
@ -23,10 +23,6 @@
|
||||
soc {
|
||||
aipi@10000000 { /* aipi */
|
||||
|
||||
wdog@10002000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
serial@1000a000 {
|
||||
fsl,uart-has-rtscts;
|
||||
status = "okay";
|
||||
|
||||
@ -62,7 +62,6 @@
|
||||
compatible = "fsl,imx27-wdt", "fsl,imx21-wdt";
|
||||
reg = <0x10002000 0x4000>;
|
||||
interrupts = <27>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@1000a000 {
|
||||
|
||||
@ -37,7 +37,7 @@
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hog_pins_a>;
|
||||
|
||||
hog_pins_a: hog-gpios@0 {
|
||||
hog_pins_a: hog@0 {
|
||||
reg = <0>;
|
||||
fsl,pinmux-ids = <
|
||||
0x0113 /* MX28_PAD_GPMI_CE1N__GPIO_0_17 */
|
||||
|
||||
99
arch/arm/boot/dts/imx28-cfa10049.dts
Normal file
99
arch/arm/boot/dts/imx28-cfa10049.dts
Normal file
@ -0,0 +1,99 @@
|
||||
/*
|
||||
* Copyright 2012 Free Electrons
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/*
|
||||
* The CFA-10049 is an expansion board for the CFA-10036 module, thus we
|
||||
* need to include the CFA-10036 DTS.
|
||||
*/
|
||||
/include/ "imx28-cfa10036.dts"
|
||||
|
||||
/ {
|
||||
model = "Crystalfontz CFA-10049 Board";
|
||||
compatible = "crystalfontz,cfa10049", "crystalfontz,cfa10036", "fsl,imx28";
|
||||
|
||||
apb@80000000 {
|
||||
apbh@80000000 {
|
||||
pinctrl@80018000 {
|
||||
spi3_pins_cfa10049: spi3-cfa10049@0 {
|
||||
reg = <0>;
|
||||
fsl,pinmux-ids = <
|
||||
0x0181 /* MX28_PAD_GPMI_RDN__SSP3_SCK */
|
||||
0x01c1 /* MX28_PAD_GPMI_RESETN__SSP3_CMD */
|
||||
0x0111 /* MX28_PAD_GPMI_CE1N__SSP3_D3 */
|
||||
0x01a2 /* MX28_PAD_GPMI_ALE__SSP3_D4 */
|
||||
>;
|
||||
fsl,drive-strength = <1>;
|
||||
fsl,voltage = <1>;
|
||||
fsl,pull-up = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
ssp3: ssp@80016000 {
|
||||
compatible = "fsl,imx28-spi";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi3_pins_cfa10049>;
|
||||
status = "okay";
|
||||
|
||||
gpio5: gpio5@0 {
|
||||
compatible = "fairchild,74hc595";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0>;
|
||||
registers-number = <2>;
|
||||
spi-max-frequency = <100000>;
|
||||
};
|
||||
|
||||
gpio6: gpio6@1 {
|
||||
compatible = "fairchild,74hc595";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <1>;
|
||||
registers-number = <4>;
|
||||
spi-max-frequency = <100000>;
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
|
||||
apbx@80040000 {
|
||||
i2c1: i2c@8005a000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c1_pins_a>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usbphy1: usbphy@8007e000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ahb@80080000 {
|
||||
usb1: usb@80090000 {
|
||||
vbus-supply = <®_usb1_vbus>;
|
||||
pinctrl-0 = <&usbphy1_pins_a>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
|
||||
reg_usb1_vbus: usb1_vbus {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "usb1_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&gpio0 7 1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -46,11 +46,28 @@
|
||||
wp-gpios = <&gpio0 28 0>;
|
||||
};
|
||||
|
||||
ssp2: ssp@80014000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx28-spi";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi2_pins_a>;
|
||||
status = "okay";
|
||||
|
||||
flash: m25p80@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "sst,sst25vf016b";
|
||||
spi-max-frequency = <40000000>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl@80018000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hog_pins_a>;
|
||||
|
||||
hog_pins_a: hog-gpios@0 {
|
||||
hog_pins_a: hog@0 {
|
||||
reg = <0>;
|
||||
fsl,pinmux-ids = <
|
||||
0x20d3 /* MX28_PAD_SSP1_CMD__GPIO_2_13 */
|
||||
@ -128,6 +145,10 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
lradc@80050000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2c0: i2c@80058000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c0_pins_a>;
|
||||
@ -140,6 +161,12 @@
|
||||
VDDIO-supply = <®_3p3v>;
|
||||
|
||||
};
|
||||
|
||||
at24@51 {
|
||||
compatible = "at24,24c32";
|
||||
pagesize = <32>;
|
||||
reg = <0x51>;
|
||||
};
|
||||
};
|
||||
|
||||
pwm: pwm@80064000 {
|
||||
|
||||
@ -23,6 +23,8 @@
|
||||
apb@80000000 {
|
||||
apbh@80000000 {
|
||||
gpmi-nand@8000c000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>;
|
||||
status = "okay";
|
||||
@ -61,19 +63,40 @@
|
||||
&mmc0_cd_cfg
|
||||
&mmc0_sck_cfg>;
|
||||
bus-width = <8>;
|
||||
wp-gpios = <&gpio3 10 1>;
|
||||
wp-gpios = <&gpio3 10 0>;
|
||||
vmmc-supply = <®_vddio_sd0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ssp2: ssp@80014000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx28-spi";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi2_pins_a>;
|
||||
status = "okay";
|
||||
|
||||
flash: m25p80@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "m25p80";
|
||||
spi-max-frequency = <40000000>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl@80018000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hog_pins_a>;
|
||||
|
||||
hog_pins_a: hog-gpios@0 {
|
||||
hog_pins_a: hog@0 {
|
||||
reg = <0>;
|
||||
fsl,pinmux-ids = <
|
||||
0x31c3 /* MX28_PAD_PWM3__GPIO_3_28 */
|
||||
0x30a3 /* MX28_PAD_AUART2_CTS__GPIO_3_10 */
|
||||
0x30b3 /* MX28_PAD_AUART2_RTS__GPIO_3_11 */
|
||||
0x30c3 /* MX28_PAD_AUART3_RX__GPIO_3_12 */
|
||||
0x30d3 /* MX28_PAD_AUART3_TX__GPIO_3_13 */
|
||||
>;
|
||||
fsl,drive-strength = <0>;
|
||||
fsl,voltage = <1>;
|
||||
@ -129,6 +152,7 @@
|
||||
i2c0: i2c@80058000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c0_pins_a>;
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
|
||||
sgtl5000: codec@0a {
|
||||
@ -151,32 +175,51 @@
|
||||
};
|
||||
};
|
||||
|
||||
lradc@80050000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
duart: serial@80074000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&duart_pins_a>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usbphy0: usbphy@8007c000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usbphy1: usbphy@8007e000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
auart0: serial@8006a000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&auart0_2pins_a>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
auart3: serial@80070000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&auart3_pins_a>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ahb@80080000 {
|
||||
usb0: usb@80080000 {
|
||||
vbus-supply = <®_usb0_vbus>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&usbphy0_pins_a>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb1: usb@80090000 {
|
||||
vbus-supply = <®_usb1_vbus>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&usbphy1_pins_a>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
mac0: ethernet@800f0000 {
|
||||
phy-mode = "rmii";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mac0_pins_a>;
|
||||
phy-reset-gpios = <&gpio3 11 0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@ -198,6 +241,30 @@
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_vddio_sd0: vddio-sd0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vddio-sd0";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpio = <&gpio3 28 0>;
|
||||
};
|
||||
|
||||
reg_usb0_vbus: usb0_vbus {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "usb0_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&gpio3 12 0>;
|
||||
};
|
||||
|
||||
reg_usb1_vbus: usb1_vbus {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "usb1_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&gpio3 13 0>;
|
||||
};
|
||||
};
|
||||
|
||||
sound {
|
||||
|
||||
@ -25,7 +25,7 @@
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hog_pins_a>;
|
||||
|
||||
hog_pins_a: hog-gpios@0 {
|
||||
hog_pins_a: hog@0 {
|
||||
reg = <0>;
|
||||
fsl,pinmux-ids = <
|
||||
0x40a3 /* MX28_PAD_ENET0_RXD3__GPIO_4_10 */
|
||||
@ -34,6 +34,24 @@
|
||||
fsl,voltage = <1>;
|
||||
fsl,pull-up = <0>;
|
||||
};
|
||||
|
||||
mac0_pins_gpio: mac0-gpio-mode@0 {
|
||||
reg = <0>;
|
||||
fsl,pinmux-ids = <
|
||||
0x4003 /* MX28_PAD_ENET0_MDC__GPIO_4_0 */
|
||||
0x4013 /* MX28_PAD_ENET0_MDIO__GPIO_4_1 */
|
||||
0x4023 /* MX28_PAD_ENET0_RX_EN__GPIO_4_2 */
|
||||
0x4033 /* MX28_PAD_ENET0_RXD0__GPIO_4_3 */
|
||||
0x4043 /* MX28_PAD_ENET0_RXD1__GPIO_4_4 */
|
||||
0x4063 /* MX28_PAD_ENET0_TX_EN__GPIO_4_6 */
|
||||
0x4073 /* MX28_PAD_ENET0_TXD0__GPIO_4_7 */
|
||||
0x4083 /* MX28_PAD_ENET0_TXD1__GPIO_4_8 */
|
||||
0x4103 /* MX28_PAD_ENET_CLK__GPIO_4_16 */
|
||||
>;
|
||||
fsl,drive-strength = <0>;
|
||||
fsl,voltage = <1>;
|
||||
fsl,pull-up = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -72,8 +90,9 @@
|
||||
ahb@80080000 {
|
||||
mac0: ethernet@800f0000 {
|
||||
phy-mode = "rmii";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-names = "default", "gpio_mode";
|
||||
pinctrl-0 = <&mac0_pins_a>;
|
||||
pinctrl-1 = <&mac0_pins_gpio>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
@ -27,6 +27,8 @@
|
||||
serial2 = &auart2;
|
||||
serial3 = &auart3;
|
||||
serial4 = &auart4;
|
||||
ethernet0 = &mac0;
|
||||
ethernet1 = &mac1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
@ -65,6 +67,7 @@
|
||||
dma-apbh@80004000 {
|
||||
compatible = "fsl,imx28-dma-apbh";
|
||||
reg = <0x80004000 0x2000>;
|
||||
clocks = <&clks 25>;
|
||||
};
|
||||
|
||||
perfmon@80006000 {
|
||||
@ -81,34 +84,47 @@
|
||||
reg-names = "gpmi-nand", "bch";
|
||||
interrupts = <88>, <41>;
|
||||
interrupt-names = "gpmi-dma", "bch";
|
||||
clocks = <&clks 50>;
|
||||
fsl,gpmi-dma-channel = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ssp0: ssp@80010000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x80010000 0x2000>;
|
||||
interrupts = <96 82>;
|
||||
clocks = <&clks 46>;
|
||||
fsl,ssp-dma-channel = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ssp1: ssp@80012000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x80012000 0x2000>;
|
||||
interrupts = <97 83>;
|
||||
clocks = <&clks 47>;
|
||||
fsl,ssp-dma-channel = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ssp2: ssp@80014000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x80014000 0x2000>;
|
||||
interrupts = <98 84>;
|
||||
clocks = <&clks 48>;
|
||||
fsl,ssp-dma-channel = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ssp3: ssp@80016000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x80016000 0x2000>;
|
||||
interrupts = <99 85>;
|
||||
clocks = <&clks 49>;
|
||||
fsl,ssp-dma-channel = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
@ -410,6 +426,28 @@
|
||||
fsl,pull-up = <1>;
|
||||
};
|
||||
|
||||
i2c0_pins_b: i2c0@1 {
|
||||
reg = <1>;
|
||||
fsl,pinmux-ids = <
|
||||
0x3001 /* MX28_PAD_AUART0_RX__I2C0_SCL */
|
||||
0x3011 /* MX28_PAD_AUART0_TX__I2C0_SDA */
|
||||
>;
|
||||
fsl,drive-strength = <1>;
|
||||
fsl,voltage = <1>;
|
||||
fsl,pull-up = <1>;
|
||||
};
|
||||
|
||||
i2c1_pins_a: i2c1@0 {
|
||||
reg = <0>;
|
||||
fsl,pinmux-ids = <
|
||||
0x3101 /* MX28_PAD_PWM0__I2C1_SCL */
|
||||
0x3111 /* MX28_PAD_PWM1__I2C1_SDA */
|
||||
>;
|
||||
fsl,drive-strength = <1>;
|
||||
fsl,voltage = <1>;
|
||||
fsl,pull-up = <1>;
|
||||
};
|
||||
|
||||
saif0_pins_a: saif0@0 {
|
||||
reg = <0>;
|
||||
fsl,pinmux-ids = <
|
||||
@ -453,6 +491,16 @@
|
||||
fsl,pull-up = <0>;
|
||||
};
|
||||
|
||||
pwm4_pins_a: pwm4@0 {
|
||||
reg = <0>;
|
||||
fsl,pinmux-ids = <
|
||||
0x31d0 /* MX28_PAD_PWM4__PWM_4 */
|
||||
>;
|
||||
fsl,drive-strength = <0>;
|
||||
fsl,voltage = <1>;
|
||||
fsl,pull-up = <0>;
|
||||
};
|
||||
|
||||
lcdif_24bit_pins_a: lcdif-24bit@0 {
|
||||
reg = <0>;
|
||||
fsl,pinmux-ids = <
|
||||
@ -507,6 +555,49 @@
|
||||
fsl,voltage = <1>;
|
||||
fsl,pull-up = <0>;
|
||||
};
|
||||
|
||||
spi2_pins_a: spi2@0 {
|
||||
reg = <0>;
|
||||
fsl,pinmux-ids = <
|
||||
0x2100 /* MX28_PAD_SSP2_SCK__SSP2_SCK */
|
||||
0x2110 /* MX28_PAD_SSP2_MOSI__SSP2_CMD */
|
||||
0x2120 /* MX28_PAD_SSP2_MISO__SSP2_D0 */
|
||||
0x2130 /* MX28_PAD_SSP2_SS0__SSP2_D3 */
|
||||
>;
|
||||
fsl,drive-strength = <1>;
|
||||
fsl,voltage = <1>;
|
||||
fsl,pull-up = <1>;
|
||||
};
|
||||
|
||||
usbphy0_pins_a: usbphy0@0 {
|
||||
reg = <0>;
|
||||
fsl,pinmux-ids = <
|
||||
0x2152 /* MX28_PAD_SSP2_SS2__USB0_OVERCURRENT */
|
||||
>;
|
||||
fsl,drive-strength = <2>;
|
||||
fsl,voltage = <1>;
|
||||
fsl,pull-up = <0>;
|
||||
};
|
||||
|
||||
usbphy0_pins_b: usbphy0@1 {
|
||||
reg = <1>;
|
||||
fsl,pinmux-ids = <
|
||||
0x3061 /* MX28_PAD_AUART1_CTS__USB0_OVERCURRENT */
|
||||
>;
|
||||
fsl,drive-strength = <2>;
|
||||
fsl,voltage = <1>;
|
||||
fsl,pull-up = <0>;
|
||||
};
|
||||
|
||||
usbphy1_pins_a: usbphy1@0 {
|
||||
reg = <0>;
|
||||
fsl,pinmux-ids = <
|
||||
0x2142 /* MX28_PAD_SSP2_SS1__USB1_OVERCURRENT */
|
||||
>;
|
||||
fsl,drive-strength = <2>;
|
||||
fsl,voltage = <1>;
|
||||
fsl,pull-up = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
digctl@8001c000 {
|
||||
@ -523,6 +614,7 @@
|
||||
dma-apbx@80024000 {
|
||||
compatible = "fsl,imx28-dma-apbx";
|
||||
reg = <0x80024000 0x2000>;
|
||||
clocks = <&clks 26>;
|
||||
};
|
||||
|
||||
dcp@80028000 {
|
||||
@ -551,6 +643,7 @@
|
||||
compatible = "fsl,imx28-lcdif";
|
||||
reg = <0x80030000 0x2000>;
|
||||
interrupts = <38 86>;
|
||||
clocks = <&clks 55>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -558,6 +651,8 @@
|
||||
compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
|
||||
reg = <0x80032000 0x2000>;
|
||||
interrupts = <8>;
|
||||
clocks = <&clks 58>, <&clks 58>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -565,6 +660,8 @@
|
||||
compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
|
||||
reg = <0x80034000 0x2000>;
|
||||
interrupts = <9>;
|
||||
clocks = <&clks 59>, <&clks 59>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -611,15 +708,17 @@
|
||||
reg = <0x80040000 0x40000>;
|
||||
ranges;
|
||||
|
||||
clkctl@80040000 {
|
||||
clks: clkctrl@80040000 {
|
||||
compatible = "fsl,imx28-clkctrl";
|
||||
reg = <0x80040000 0x2000>;
|
||||
status = "disabled";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
saif0: saif@80042000 {
|
||||
compatible = "fsl,imx28-saif";
|
||||
reg = <0x80042000 0x2000>;
|
||||
interrupts = <59 80>;
|
||||
clocks = <&clks 53>;
|
||||
fsl,saif-dma-channel = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
@ -633,12 +732,16 @@
|
||||
compatible = "fsl,imx28-saif";
|
||||
reg = <0x80046000 0x2000>;
|
||||
interrupts = <58 81>;
|
||||
clocks = <&clks 54>;
|
||||
fsl,saif-dma-channel = <5>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lradc@80050000 {
|
||||
compatible = "fsl,imx28-lradc";
|
||||
reg = <0x80050000 0x2000>;
|
||||
interrupts = <10 14 15 16 17 18 19
|
||||
20 21 22 23 24 25>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -677,6 +780,7 @@
|
||||
pwm: pwm@80064000 {
|
||||
compatible = "fsl,imx28-pwm", "fsl,imx23-pwm";
|
||||
reg = <0x80064000 0x2000>;
|
||||
clocks = <&clks 44>;
|
||||
#pwm-cells = <2>;
|
||||
fsl,pwm-number = <8>;
|
||||
status = "disabled";
|
||||
@ -691,6 +795,7 @@
|
||||
compatible = "fsl,imx28-auart", "fsl,imx23-auart";
|
||||
reg = <0x8006a000 0x2000>;
|
||||
interrupts = <112 70 71>;
|
||||
clocks = <&clks 45>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -698,6 +803,7 @@
|
||||
compatible = "fsl,imx28-auart", "fsl,imx23-auart";
|
||||
reg = <0x8006c000 0x2000>;
|
||||
interrupts = <113 72 73>;
|
||||
clocks = <&clks 45>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -705,6 +811,7 @@
|
||||
compatible = "fsl,imx28-auart", "fsl,imx23-auart";
|
||||
reg = <0x8006e000 0x2000>;
|
||||
interrupts = <114 74 75>;
|
||||
clocks = <&clks 45>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -712,6 +819,7 @@
|
||||
compatible = "fsl,imx28-auart", "fsl,imx23-auart";
|
||||
reg = <0x80070000 0x2000>;
|
||||
interrupts = <115 76 77>;
|
||||
clocks = <&clks 45>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -719,6 +827,7 @@
|
||||
compatible = "fsl,imx28-auart", "fsl,imx23-auart";
|
||||
reg = <0x80072000 0x2000>;
|
||||
interrupts = <116 78 79>;
|
||||
clocks = <&clks 45>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -726,18 +835,22 @@
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x80074000 0x1000>;
|
||||
interrupts = <47>;
|
||||
clocks = <&clks 45>, <&clks 26>;
|
||||
clock-names = "uart", "apb_pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbphy0: usbphy@8007c000 {
|
||||
compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
|
||||
reg = <0x8007c000 0x2000>;
|
||||
clocks = <&clks 62>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbphy1: usbphy@8007e000 {
|
||||
compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
|
||||
reg = <0x8007e000 0x2000>;
|
||||
clocks = <&clks 63>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
@ -754,6 +867,7 @@
|
||||
compatible = "fsl,imx28-usb", "fsl,imx27-usb";
|
||||
reg = <0x80080000 0x10000>;
|
||||
interrupts = <93>;
|
||||
clocks = <&clks 60>;
|
||||
fsl,usbphy = <&usbphy0>;
|
||||
status = "disabled";
|
||||
};
|
||||
@ -762,6 +876,7 @@
|
||||
compatible = "fsl,imx28-usb", "fsl,imx27-usb";
|
||||
reg = <0x80090000 0x10000>;
|
||||
interrupts = <92>;
|
||||
clocks = <&clks 61>;
|
||||
fsl,usbphy = <&usbphy1>;
|
||||
status = "disabled";
|
||||
};
|
||||
@ -775,6 +890,8 @@
|
||||
compatible = "fsl,imx28-fec";
|
||||
reg = <0x800f0000 0x4000>;
|
||||
interrupts = <101>;
|
||||
clocks = <&clks 57>, <&clks 57>;
|
||||
clock-names = "ipg", "ahb";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -782,6 +899,8 @@
|
||||
compatible = "fsl,imx28-fec";
|
||||
reg = <0x800f4000 0x4000>;
|
||||
interrupts = <102>;
|
||||
clocks = <&clks 57>, <&clks 57>;
|
||||
clock-names = "ipg", "ahb";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
||||
@ -25,23 +25,31 @@
|
||||
aips@70000000 { /* aips-1 */
|
||||
spba@70000000 {
|
||||
esdhc@70004000 { /* ESDHC1 */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_esdhc1_1>;
|
||||
fsl,cd-controller;
|
||||
fsl,wp-controller;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
esdhc@70008000 { /* ESDHC2 */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_esdhc2_1>;
|
||||
cd-gpios = <&gpio1 6 0>;
|
||||
wp-gpios = <&gpio1 5 0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
uart3: serial@7000c000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart3_1>;
|
||||
fsl,uart-has-rtscts;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ecspi@70010000 { /* ECSPI1 */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ecspi1_1>;
|
||||
fsl,spi-num-chipselects = <2>;
|
||||
cs-gpios = <&gpio4 24 0>, <&gpio4 25 0>;
|
||||
status = "okay";
|
||||
@ -169,31 +177,43 @@
|
||||
};
|
||||
};
|
||||
|
||||
wdog@73f98000 { /* WDOG1 */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
iomuxc@73fa8000 {
|
||||
compatible = "fsl,imx51-iomuxc-babbage";
|
||||
reg = <0x73fa8000 0x4000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hog>;
|
||||
|
||||
hog {
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
694 0x20d5 /* MX51_PAD_GPIO1_0__SD1_CD */
|
||||
697 0x20d5 /* MX51_PAD_GPIO1_1__SD1_WP */
|
||||
737 0x100 /* MX51_PAD_GPIO1_5__GPIO1_5 */
|
||||
740 0x100 /* MX51_PAD_GPIO1_6__GPIO1_6 */
|
||||
121 0x5 /* MX51_PAD_EIM_A27__GPIO2_21 */
|
||||
402 0x85 /* MX51_PAD_CSPI1_SS0__GPIO4_24 */
|
||||
405 0x85 /* MX51_PAD_CSPI1_SS1__GPIO4_25 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
uart1: serial@73fbc000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1_1>;
|
||||
fsl,uart-has-rtscts;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
uart2: serial@73fc0000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2_1>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
aips@80000000 { /* aips-2 */
|
||||
sdma@83fb0000 {
|
||||
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
|
||||
};
|
||||
|
||||
i2c@83fc4000 { /* I2C2 */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2_1>;
|
||||
status = "okay";
|
||||
|
||||
sgtl5000: codec@0a {
|
||||
@ -206,10 +226,14 @@
|
||||
};
|
||||
|
||||
audmux@83fd0000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_audmux_1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ethernet@83fec000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_fec_1>;
|
||||
phy-mode = "mii";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@ -130,6 +130,34 @@
|
||||
};
|
||||
};
|
||||
|
||||
usb@73f80000 {
|
||||
compatible = "fsl,imx51-usb", "fsl,imx27-usb";
|
||||
reg = <0x73f80000 0x0200>;
|
||||
interrupts = <18>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb@73f80200 {
|
||||
compatible = "fsl,imx51-usb", "fsl,imx27-usb";
|
||||
reg = <0x73f80200 0x0200>;
|
||||
interrupts = <14>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb@73f80400 {
|
||||
compatible = "fsl,imx51-usb", "fsl,imx27-usb";
|
||||
reg = <0x73f80400 0x0200>;
|
||||
interrupts = <16>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb@73f80600 {
|
||||
compatible = "fsl,imx51-usb", "fsl,imx27-usb";
|
||||
reg = <0x73f80600 0x0200>;
|
||||
interrupts = <17>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio1: gpio@73f84000 {
|
||||
compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x73f84000 0x4000>;
|
||||
@ -174,7 +202,6 @@
|
||||
compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
|
||||
reg = <0x73f98000 0x4000>;
|
||||
interrupts = <58>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wdog@73f9c000 { /* WDOG2 */
|
||||
@ -184,6 +211,122 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
iomuxc@73fa8000 {
|
||||
compatible = "fsl,imx51-iomuxc";
|
||||
reg = <0x73fa8000 0x4000>;
|
||||
|
||||
audmux {
|
||||
pinctrl_audmux_1: audmuxgrp-1 {
|
||||
fsl,pins = <
|
||||
384 0x80000000 /* MX51_PAD_AUD3_BB_TXD__AUD3_TXD */
|
||||
386 0x80000000 /* MX51_PAD_AUD3_BB_RXD__AUD3_RXD */
|
||||
389 0x80000000 /* MX51_PAD_AUD3_BB_CK__AUD3_TXC */
|
||||
391 0x80000000 /* MX51_PAD_AUD3_BB_FS__AUD3_TXFS */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
fec {
|
||||
pinctrl_fec_1: fecgrp-1 {
|
||||
fsl,pins = <
|
||||
128 0x80000000 /* MX51_PAD_EIM_EB2__FEC_MDIO */
|
||||
134 0x80000000 /* MX51_PAD_EIM_EB3__FEC_RDATA1 */
|
||||
146 0x80000000 /* MX51_PAD_EIM_CS2__FEC_RDATA2 */
|
||||
152 0x80000000 /* MX51_PAD_EIM_CS3__FEC_RDATA3 */
|
||||
158 0x80000000 /* MX51_PAD_EIM_CS4__FEC_RX_ER */
|
||||
165 0x80000000 /* MX51_PAD_EIM_CS5__FEC_CRS */
|
||||
206 0x80000000 /* MX51_PAD_NANDF_RB2__FEC_COL */
|
||||
213 0x80000000 /* MX51_PAD_NANDF_RB3__FEC_RX_CLK */
|
||||
293 0x80000000 /* MX51_PAD_NANDF_D9__FEC_RDATA0 */
|
||||
298 0x80000000 /* MX51_PAD_NANDF_D8__FEC_TDATA0 */
|
||||
225 0x80000000 /* MX51_PAD_NANDF_CS2__FEC_TX_ER */
|
||||
231 0x80000000 /* MX51_PAD_NANDF_CS3__FEC_MDC */
|
||||
237 0x80000000 /* MX51_PAD_NANDF_CS4__FEC_TDATA1 */
|
||||
243 0x80000000 /* MX51_PAD_NANDF_CS5__FEC_TDATA2 */
|
||||
250 0x80000000 /* MX51_PAD_NANDF_CS6__FEC_TDATA3 */
|
||||
255 0x80000000 /* MX51_PAD_NANDF_CS7__FEC_TX_EN */
|
||||
260 0x80000000 /* MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
ecspi1 {
|
||||
pinctrl_ecspi1_1: ecspi1grp-1 {
|
||||
fsl,pins = <
|
||||
398 0x185 /* MX51_PAD_CSPI1_MISO__ECSPI1_MISO */
|
||||
394 0x185 /* MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI */
|
||||
409 0x185 /* MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
esdhc1 {
|
||||
pinctrl_esdhc1_1: esdhc1grp-1 {
|
||||
fsl,pins = <
|
||||
666 0x400020d5 /* MX51_PAD_SD1_CMD__SD1_CMD */
|
||||
669 0x20d5 /* MX51_PAD_SD1_CLK__SD1_CLK */
|
||||
672 0x20d5 /* MX51_PAD_SD1_DATA0__SD1_DATA0 */
|
||||
678 0x20d5 /* MX51_PAD_SD1_DATA1__SD1_DATA1 */
|
||||
684 0x20d5 /* MX51_PAD_SD1_DATA2__SD1_DATA2 */
|
||||
691 0x20d5 /* MX51_PAD_SD1_DATA3__SD1_DATA3 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
esdhc2 {
|
||||
pinctrl_esdhc2_1: esdhc2grp-1 {
|
||||
fsl,pins = <
|
||||
704 0x400020d5 /* MX51_PAD_SD2_CMD__SD2_CMD */
|
||||
707 0x20d5 /* MX51_PAD_SD2_CLK__SD2_CLK */
|
||||
710 0x20d5 /* MX51_PAD_SD2_DATA0__SD2_DATA0 */
|
||||
712 0x20d5 /* MX51_PAD_SD2_DATA1__SD2_DATA1 */
|
||||
715 0x20d5 /* MX51_PAD_SD2_DATA2__SD2_DATA2 */
|
||||
719 0x20d5 /* MX51_PAD_SD2_DATA3__SD2_DATA3 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c2 {
|
||||
pinctrl_i2c2_1: i2c2grp-1 {
|
||||
fsl,pins = <
|
||||
449 0x400001ed /* MX51_PAD_KEY_COL4__I2C2_SCL */
|
||||
454 0x400001ed /* MX51_PAD_KEY_COL5__I2C2_SDA */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
uart1 {
|
||||
pinctrl_uart1_1: uart1grp-1 {
|
||||
fsl,pins = <
|
||||
413 0x1c5 /* MX51_PAD_UART1_RXD__UART1_RXD */
|
||||
416 0x1c5 /* MX51_PAD_UART1_TXD__UART1_TXD */
|
||||
418 0x1c5 /* MX51_PAD_UART1_RTS__UART1_RTS */
|
||||
420 0x1c5 /* MX51_PAD_UART1_CTS__UART1_CTS */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
uart2 {
|
||||
pinctrl_uart2_1: uart2grp-1 {
|
||||
fsl,pins = <
|
||||
423 0x1c5 /* MX51_PAD_UART2_RXD__UART2_RXD */
|
||||
426 0x1c5 /* MX51_PAD_UART2_TXD__UART2_TXD */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
uart3 {
|
||||
pinctrl_uart3_1: uart3grp-1 {
|
||||
fsl,pins = <
|
||||
54 0x1c5 /* MX51_PAD_EIM_D25__UART3_RXD */
|
||||
59 0x1c5 /* MX51_PAD_EIM_D26__UART3_TXD */
|
||||
65 0x1c5 /* MX51_PAD_EIM_D27__UART3_RTS */
|
||||
49 0x1c5 /* MX51_PAD_EIM_D24__UART3_CTS */
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
uart1: serial@73fbc000 {
|
||||
compatible = "fsl,imx51-uart", "fsl,imx21-uart";
|
||||
reg = <0x73fbc000 0x4000>;
|
||||
@ -219,6 +362,7 @@
|
||||
compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
|
||||
reg = <0x83fb0000 0x4000>;
|
||||
interrupts = <6>;
|
||||
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
|
||||
};
|
||||
|
||||
cspi@83fc0000 {
|
||||
|
||||
@ -25,31 +25,66 @@
|
||||
aips@50000000 { /* AIPS1 */
|
||||
spba@50000000 {
|
||||
esdhc@50004000 { /* ESDHC1 */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_esdhc1_2>;
|
||||
cd-gpios = <&gpio1 1 0>;
|
||||
wp-gpios = <&gpio1 9 0>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
wdog@53f98000 { /* WDOG1 */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
iomuxc@53fa8000 {
|
||||
compatible = "fsl,imx53-iomuxc-ard";
|
||||
reg = <0x53fa8000 0x4000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hog>;
|
||||
|
||||
hog {
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
1077 0x80000000 /* MX53_PAD_GPIO_1__GPIO1_1 */
|
||||
1085 0x80000000 /* MX53_PAD_GPIO_9__GPIO1_9 */
|
||||
486 0x80000000 /* MX53_PAD_EIM_EB3__GPIO2_31 */
|
||||
739 0x80000000 /* MX53_PAD_GPIO_10__GPIO4_0 */
|
||||
218 0x80000000 /* MX53_PAD_DISP0_DAT16__GPIO5_10 */
|
||||
226 0x80000000 /* MX53_PAD_DISP0_DAT17__GPIO5_11 */
|
||||
233 0x80000000 /* MX53_PAD_DISP0_DAT18__GPIO5_12 */
|
||||
241 0x80000000 /* MX53_PAD_DISP0_DAT19__GPIO5_13 */
|
||||
429 0x80000000 /* MX53_PAD_EIM_D16__EMI_WEIM_D_16 */
|
||||
435 0x80000000 /* MX53_PAD_EIM_D17__EMI_WEIM_D_17 */
|
||||
441 0x80000000 /* MX53_PAD_EIM_D18__EMI_WEIM_D_18 */
|
||||
448 0x80000000 /* MX53_PAD_EIM_D19__EMI_WEIM_D_19 */
|
||||
456 0x80000000 /* MX53_PAD_EIM_D20__EMI_WEIM_D_20 */
|
||||
464 0x80000000 /* MX53_PAD_EIM_D21__EMI_WEIM_D_21 */
|
||||
471 0x80000000 /* MX53_PAD_EIM_D22__EMI_WEIM_D_22 */
|
||||
477 0x80000000 /* MX53_PAD_EIM_D23__EMI_WEIM_D_23 */
|
||||
492 0x80000000 /* MX53_PAD_EIM_D24__EMI_WEIM_D_24 */
|
||||
500 0x80000000 /* MX53_PAD_EIM_D25__EMI_WEIM_D_25 */
|
||||
508 0x80000000 /* MX53_PAD_EIM_D26__EMI_WEIM_D_26 */
|
||||
516 0x80000000 /* MX53_PAD_EIM_D27__EMI_WEIM_D_27 */
|
||||
524 0x80000000 /* MX53_PAD_EIM_D28__EMI_WEIM_D_28 */
|
||||
532 0x80000000 /* MX53_PAD_EIM_D29__EMI_WEIM_D_29 */
|
||||
540 0x80000000 /* MX53_PAD_EIM_D30__EMI_WEIM_D_30 */
|
||||
548 0x80000000 /* MX53_PAD_EIM_D31__EMI_WEIM_D_31 */
|
||||
637 0x80000000 /* MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 */
|
||||
642 0x80000000 /* MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 */
|
||||
647 0x80000000 /* MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 */
|
||||
652 0x80000000 /* MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 */
|
||||
657 0x80000000 /* MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 */
|
||||
662 0x80000000 /* MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 */
|
||||
667 0x80000000 /* MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 */
|
||||
611 0x80000000 /* MX53_PAD_EIM_OE__EMI_WEIM_OE */
|
||||
616 0x80000000 /* MX53_PAD_EIM_RW__EMI_WEIM_RW */
|
||||
607 0x80000000 /* MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
uart1: serial@53fbc000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1_2>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
aips@60000000 { /* AIPS2 */
|
||||
sdma@63fb0000 {
|
||||
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
eim-cs1@f4000000 {
|
||||
|
||||
@ -25,12 +25,16 @@
|
||||
aips@50000000 { /* AIPS1 */
|
||||
spba@50000000 {
|
||||
esdhc@50004000 { /* ESDHC1 */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_esdhc1_1>;
|
||||
cd-gpios = <&gpio3 13 0>;
|
||||
wp-gpios = <&gpio3 14 0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ecspi@50010000 { /* ECSPI1 */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ecspi1_1>;
|
||||
fsl,spi-num-chipselects = <2>;
|
||||
cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>;
|
||||
status = "okay";
|
||||
@ -56,32 +60,45 @@
|
||||
};
|
||||
|
||||
esdhc@50020000 { /* ESDHC3 */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_esdhc3_1>;
|
||||
cd-gpios = <&gpio3 11 0>;
|
||||
wp-gpios = <&gpio3 12 0>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
wdog@53f98000 { /* WDOG1 */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
iomuxc@53fa8000 {
|
||||
compatible = "fsl,imx53-iomuxc-evk";
|
||||
reg = <0x53fa8000 0x4000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hog>;
|
||||
|
||||
hog {
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
424 0x80000000 /* MX53_PAD_EIM_EB2__GPIO2_30 */
|
||||
449 0x80000000 /* MX53_PAD_EIM_D19__GPIO3_19 */
|
||||
693 0x80000000 /* MX53_PAD_EIM_DA11__GPIO3_11 */
|
||||
697 0x80000000 /* MX53_PAD_EIM_DA12__GPIO3_12 */
|
||||
701 0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */
|
||||
705 0x80000000 /* MX53_PAD_EIM_DA14__GPIO3_14 */
|
||||
868 0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */
|
||||
873 0x80000000 /* MX53_PAD_PATA_DA_1__GPIO7_7 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
uart1: serial@53fbc000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1_1>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
aips@60000000 { /* AIPS2 */
|
||||
sdma@63fb0000 {
|
||||
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
|
||||
};
|
||||
|
||||
i2c@63fc4000 { /* I2C2 */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2_1>;
|
||||
status = "okay";
|
||||
|
||||
pmic: mc13892@08 {
|
||||
@ -96,6 +113,8 @@
|
||||
};
|
||||
|
||||
ethernet@63fec000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_fec_1>;
|
||||
phy-mode = "rmii";
|
||||
phy-reset-gpios = <&gpio7 6 0>;
|
||||
status = "okay";
|
||||
|
||||
@ -25,6 +25,8 @@
|
||||
aips@50000000 { /* AIPS1 */
|
||||
spba@50000000 {
|
||||
esdhc@50004000 { /* ESDHC1 */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_esdhc1_1>;
|
||||
cd-gpios = <&gpio3 13 0>;
|
||||
status = "okay";
|
||||
};
|
||||
@ -35,32 +37,46 @@
|
||||
};
|
||||
|
||||
esdhc@50020000 { /* ESDHC3 */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_esdhc3_1>;
|
||||
cd-gpios = <&gpio3 11 0>;
|
||||
wp-gpios = <&gpio3 12 0>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
wdog@53f98000 { /* WDOG1 */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
iomuxc@53fa8000 {
|
||||
compatible = "fsl,imx53-iomuxc-qsb";
|
||||
reg = <0x53fa8000 0x4000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hog>;
|
||||
|
||||
hog {
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
1071 0x80000000 /* MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK */
|
||||
1141 0x80000000 /* MX53_PAD_GPIO_8__GPIO1_8 */
|
||||
982 0x80000000 /* MX53_PAD_PATA_DATA14__GPIO2_14 */
|
||||
989 0x80000000 /* MX53_PAD_PATA_DATA15__GPIO2_15 */
|
||||
693 0x80000000 /* MX53_PAD_EIM_DA11__GPIO3_11 */
|
||||
697 0x80000000 /* MX53_PAD_EIM_DA12__GPIO3_12 */
|
||||
701 0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */
|
||||
868 0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */
|
||||
873 0x80000000 /* MX53_PAD_PATA_DA_1__GPIO7_7 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
uart1: serial@53fbc000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1_1>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
aips@60000000 { /* AIPS2 */
|
||||
sdma@63fb0000 {
|
||||
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
|
||||
};
|
||||
|
||||
i2c@63fc4000 { /* I2C2 */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2_1>;
|
||||
status = "okay";
|
||||
|
||||
sgtl5000: codec@0a {
|
||||
@ -72,6 +88,8 @@
|
||||
};
|
||||
|
||||
i2c@63fc8000 { /* I2C1 */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c1_1>;
|
||||
status = "okay";
|
||||
|
||||
accelerometer: mma8450@1c {
|
||||
@ -158,10 +176,14 @@
|
||||
};
|
||||
|
||||
audmux@63fd0000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_audmux_1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ethernet@63fec000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_fec_1>;
|
||||
phy-mode = "rmii";
|
||||
phy-reset-gpios = <&gpio7 6 0>;
|
||||
status = "okay";
|
||||
|
||||
@ -25,22 +25,30 @@
|
||||
aips@50000000 { /* AIPS1 */
|
||||
spba@50000000 {
|
||||
esdhc@50004000 { /* ESDHC1 */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_esdhc1_1>;
|
||||
cd-gpios = <&gpio3 13 0>;
|
||||
wp-gpios = <&gpio4 11 0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
esdhc@50008000 { /* ESDHC2 */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_esdhc2_1>;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
uart3: serial@5000c000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart3_1>;
|
||||
fsl,uart-has-rtscts;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ecspi@50010000 { /* ECSPI1 */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ecspi1_1>;
|
||||
fsl,spi-num-chipselects = <2>;
|
||||
cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>;
|
||||
status = "okay";
|
||||
@ -72,35 +80,49 @@
|
||||
};
|
||||
|
||||
esdhc@50020000 { /* ESDHC3 */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_esdhc3_1>;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
wdog@53f98000 { /* WDOG1 */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
iomuxc@53fa8000 {
|
||||
compatible = "fsl,imx53-iomuxc-smd";
|
||||
reg = <0x53fa8000 0x4000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hog>;
|
||||
|
||||
hog {
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
982 0x80000000 /* MX53_PAD_PATA_DATA14__GPIO2_14 */
|
||||
989 0x80000000 /* MX53_PAD_PATA_DATA15__GPIO2_15 */
|
||||
424 0x80000000 /* MX53_PAD_EIM_EB2__GPIO2_30 */
|
||||
701 0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */
|
||||
449 0x80000000 /* MX53_PAD_EIM_D19__GPIO3_19 */
|
||||
43 0x80000000 /* MX53_PAD_KEY_ROW2__GPIO4_11 */
|
||||
868 0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
uart1: serial@53fbc000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1_1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
uart2: serial@53fc0000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2_1>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
aips@60000000 { /* AIPS2 */
|
||||
sdma@63fb0000 {
|
||||
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
|
||||
};
|
||||
|
||||
i2c@63fc4000 { /* I2C2 */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2_1>;
|
||||
status = "okay";
|
||||
|
||||
codec: sgtl5000@0a {
|
||||
@ -120,6 +142,8 @@
|
||||
};
|
||||
|
||||
i2c@63fc8000 { /* I2C1 */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c1_1>;
|
||||
status = "okay";
|
||||
|
||||
accelerometer: mma8450@1c {
|
||||
@ -139,6 +163,8 @@
|
||||
};
|
||||
|
||||
ethernet@63fec000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_fec_1>;
|
||||
phy-mode = "rmii";
|
||||
phy-reset-gpios = <&gpio7 6 0>;
|
||||
status = "okay";
|
||||
|
||||
@ -135,6 +135,34 @@
|
||||
};
|
||||
};
|
||||
|
||||
usb@53f80000 {
|
||||
compatible = "fsl,imx53-usb", "fsl,imx27-usb";
|
||||
reg = <0x53f80000 0x0200>;
|
||||
interrupts = <18>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb@53f80200 {
|
||||
compatible = "fsl,imx53-usb", "fsl,imx27-usb";
|
||||
reg = <0x53f80200 0x0200>;
|
||||
interrupts = <14>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb@53f80400 {
|
||||
compatible = "fsl,imx53-usb", "fsl,imx27-usb";
|
||||
reg = <0x53f80400 0x0200>;
|
||||
interrupts = <16>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb@53f80600 {
|
||||
compatible = "fsl,imx53-usb", "fsl,imx27-usb";
|
||||
reg = <0x53f80600 0x0200>;
|
||||
interrupts = <17>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio1: gpio@53f84000 {
|
||||
compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x53f84000 0x4000>;
|
||||
@ -179,7 +207,6 @@
|
||||
compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
|
||||
reg = <0x53f98000 0x4000>;
|
||||
interrupts = <58>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wdog@53f9c000 { /* WDOG2 */
|
||||
@ -189,6 +216,161 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
iomuxc@53fa8000 {
|
||||
compatible = "fsl,imx53-iomuxc";
|
||||
reg = <0x53fa8000 0x4000>;
|
||||
|
||||
audmux {
|
||||
pinctrl_audmux_1: audmuxgrp-1 {
|
||||
fsl,pins = <
|
||||
10 0x80000000 /* MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC */
|
||||
17 0x80000000 /* MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD */
|
||||
23 0x80000000 /* MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS */
|
||||
30 0x80000000 /* MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
fec {
|
||||
pinctrl_fec_1: fecgrp-1 {
|
||||
fsl,pins = <
|
||||
820 0x80000000 /* MX53_PAD_FEC_MDC__FEC_MDC */
|
||||
779 0x80000000 /* MX53_PAD_FEC_MDIO__FEC_MDIO */
|
||||
786 0x80000000 /* MX53_PAD_FEC_REF_CLK__FEC_TX_CLK */
|
||||
791 0x80000000 /* MX53_PAD_FEC_RX_ER__FEC_RX_ER */
|
||||
796 0x80000000 /* MX53_PAD_FEC_CRS_DV__FEC_RX_DV */
|
||||
799 0x80000000 /* MX53_PAD_FEC_RXD1__FEC_RDATA_1 */
|
||||
804 0x80000000 /* MX53_PAD_FEC_RXD0__FEC_RDATA_0 */
|
||||
808 0x80000000 /* MX53_PAD_FEC_TX_EN__FEC_TX_EN */
|
||||
811 0x80000000 /* MX53_PAD_FEC_TXD1__FEC_TDATA_1 */
|
||||
816 0x80000000 /* MX53_PAD_FEC_TXD0__FEC_TDATA_0 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
ecspi1 {
|
||||
pinctrl_ecspi1_1: ecspi1grp-1 {
|
||||
fsl,pins = <
|
||||
433 0x80000000 /* MX53_PAD_EIM_D16__ECSPI1_SCLK */
|
||||
439 0x80000000 /* MX53_PAD_EIM_D17__ECSPI1_MISO */
|
||||
445 0x80000000 /* MX53_PAD_EIM_D18__ECSPI1_MOSI */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
esdhc1 {
|
||||
pinctrl_esdhc1_1: esdhc1grp-1 {
|
||||
fsl,pins = <
|
||||
995 0x1d5 /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */
|
||||
1000 0x1d5 /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */
|
||||
1010 0x1d5 /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */
|
||||
1024 0x1d5 /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */
|
||||
1005 0x1d5 /* MX53_PAD_SD1_CMD__ESDHC1_CMD */
|
||||
1018 0x1d5 /* MX53_PAD_SD1_CLK__ESDHC1_CLK */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_esdhc1_2: esdhc1grp-2 {
|
||||
fsl,pins = <
|
||||
995 0x1d5 /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */
|
||||
1000 0x1d5 /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */
|
||||
1010 0x1d5 /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */
|
||||
1024 0x1d5 /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */
|
||||
941 0x1d5 /* MX53_PAD_PATA_DATA8__ESDHC1_DAT4 */
|
||||
948 0x1d5 /* MX53_PAD_PATA_DATA9__ESDHC1_DAT5 */
|
||||
955 0x1d5 /* MX53_PAD_PATA_DATA10__ESDHC1_DAT6 */
|
||||
962 0x1d5 /* MX53_PAD_PATA_DATA11__ESDHC1_DAT7 */
|
||||
1005 0x1d5 /* MX53_PAD_SD1_CMD__ESDHC1_CMD */
|
||||
1018 0x1d5 /* MX53_PAD_SD1_CLK__ESDHC1_CLK */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
esdhc2 {
|
||||
pinctrl_esdhc2_1: esdhc2grp-1 {
|
||||
fsl,pins = <
|
||||
1038 0x1d5 /* MX53_PAD_SD2_CMD__ESDHC2_CMD */
|
||||
1032 0x1d5 /* MX53_PAD_SD2_CLK__ESDHC2_CLK */
|
||||
1062 0x1d5 /* MX53_PAD_SD2_DATA0__ESDHC2_DAT0 */
|
||||
1056 0x1d5 /* MX53_PAD_SD2_DATA1__ESDHC2_DAT1 */
|
||||
1050 0x1d5 /* MX53_PAD_SD2_DATA2__ESDHC2_DAT2 */
|
||||
1044 0x1d5 /* MX53_PAD_SD2_DATA3__ESDHC2_DAT3 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
esdhc3 {
|
||||
pinctrl_esdhc3_1: esdhc3grp-1 {
|
||||
fsl,pins = <
|
||||
943 0x1d5 /* MX53_PAD_PATA_DATA8__ESDHC3_DAT0 */
|
||||
950 0x1d5 /* MX53_PAD_PATA_DATA9__ESDHC3_DAT1 */
|
||||
957 0x1d5 /* MX53_PAD_PATA_DATA10__ESDHC3_DAT2 */
|
||||
964 0x1d5 /* MX53_PAD_PATA_DATA11__ESDHC3_DAT3 */
|
||||
893 0x1d5 /* MX53_PAD_PATA_DATA0__ESDHC3_DAT4 */
|
||||
900 0x1d5 /* MX53_PAD_PATA_DATA1__ESDHC3_DAT5 */
|
||||
906 0x1d5 /* MX53_PAD_PATA_DATA2__ESDHC3_DAT6 */
|
||||
912 0x1d5 /* MX53_PAD_PATA_DATA3__ESDHC3_DAT7 */
|
||||
857 0x1d5 /* MX53_PAD_PATA_RESET_B__ESDHC3_CMD */
|
||||
863 0x1d5 /* MX53_PAD_PATA_IORDY__ESDHC3_CLK */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c1 {
|
||||
pinctrl_i2c1_1: i2c1grp-1 {
|
||||
fsl,pins = <
|
||||
333 0xc0000000 /* MX53_PAD_CSI0_DAT8__I2C1_SDA */
|
||||
341 0xc0000000 /* MX53_PAD_CSI0_DAT9__I2C1_SCL */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c2 {
|
||||
pinctrl_i2c2_1: i2c2grp-1 {
|
||||
fsl,pins = <
|
||||
61 0xc0000000 /* MX53_PAD_KEY_ROW3__I2C2_SDA */
|
||||
53 0xc0000000 /* MX53_PAD_KEY_COL3__I2C2_SCL */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
uart1 {
|
||||
pinctrl_uart1_1: uart1grp-1 {
|
||||
fsl,pins = <
|
||||
346 0x1c5 /* MX53_PAD_CSI0_DAT10__UART1_TXD_MUX */
|
||||
354 0x1c5 /* MX53_PAD_CSI0_DAT11__UART1_RXD_MUX */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart1_2: uart1grp-2 {
|
||||
fsl,pins = <
|
||||
828 0x1c5 /* MX53_PAD_PATA_DIOW__UART1_TXD_MUX */
|
||||
832 0x1c5 /* MX53_PAD_PATA_DMACK__UART1_RXD_MUX */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
uart2 {
|
||||
pinctrl_uart2_1: uart2grp-1 {
|
||||
fsl,pins = <
|
||||
841 0x1c5 /* MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX */
|
||||
836 0x1c5 /* MX53_PAD_PATA_DMARQ__UART2_TXD_MUX */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
uart3 {
|
||||
pinctrl_uart3_1: uart3grp-1 {
|
||||
fsl,pins = <
|
||||
884 0x1c5 /* MX53_PAD_PATA_CS_0__UART3_TXD_MUX */
|
||||
888 0x1c5 /* MX53_PAD_PATA_CS_1__UART3_RXD_MUX */
|
||||
875 0x1c5 /* MX53_PAD_PATA_DA_1__UART3_CTS */
|
||||
880 0x1c5 /* MX53_PAD_PATA_DA_2__UART3_RTS */
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
uart1: serial@53fbc000 {
|
||||
compatible = "fsl,imx53-uart", "fsl,imx21-uart";
|
||||
reg = <0x53fbc000 0x4000>;
|
||||
@ -203,6 +385,20 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
can1: can@53fc8000 {
|
||||
compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
|
||||
reg = <0x53fc8000 0x4000>;
|
||||
interrupts = <82>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
can2: can@53fcc000 {
|
||||
compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
|
||||
reg = <0x53fcc000 0x4000>;
|
||||
interrupts = <83>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio5: gpio@53fdc000 {
|
||||
compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x53fdc000 0x4000>;
|
||||
@ -277,6 +473,7 @@
|
||||
compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
|
||||
reg = <0x63fb0000 0x4000>;
|
||||
interrupts = <6>;
|
||||
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
|
||||
};
|
||||
|
||||
cspi@63fc0000 {
|
||||
|
||||
@ -28,8 +28,27 @@
|
||||
status = "disabled"; /* gpmi nand conflicts with SD */
|
||||
};
|
||||
|
||||
aips-bus@02000000 { /* AIPS1 */
|
||||
iomuxc@020e0000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hog>;
|
||||
|
||||
hog {
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
176 0x80000000 /* MX6Q_PAD_EIM_D25__GPIO_3_25 */
|
||||
1363 0x80000000 /* MX6Q_PAD_NANDF_CS0__GPIO_6_11 */
|
||||
1369 0x80000000 /* MX6Q_PAD_NANDF_CS1__GPIO_6_14 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
aips-bus@02100000 { /* AIPS2 */
|
||||
ethernet@02188000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_enet_2>;
|
||||
phy-mode = "rgmii";
|
||||
status = "okay";
|
||||
};
|
||||
@ -52,6 +71,8 @@
|
||||
};
|
||||
|
||||
uart4: serial@021f0000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart4_1>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
@ -46,15 +46,20 @@
|
||||
|
||||
iomuxc@020e0000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_gpio_hog>;
|
||||
pinctrl-0 = <&pinctrl_hog>;
|
||||
|
||||
gpios {
|
||||
pinctrl_gpio_hog: gpiohog {
|
||||
hog {
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
144 0x80000000 /* MX6Q_PAD_EIM_D22__GPIO_3_22 */
|
||||
121 0x80000000 /* MX6Q_PAD_EIM_D19__GPIO_3_19 */
|
||||
953 0x80000000 /* MX6Q_PAD_GPIO_0__CCM_CLKO */
|
||||
>;
|
||||
1450 0x80000000 /* MX6Q_PAD_NANDF_D6__GPIO_2_6 */
|
||||
1458 0x80000000 /* MX6Q_PAD_NANDF_D7__GPIO_2_7 */
|
||||
121 0x80000000 /* MX6Q_PAD_EIM_D19__GPIO_3_19 */
|
||||
144 0x80000000 /* MX6Q_PAD_EIM_D22__GPIO_3_22 */
|
||||
152 0x80000000 /* MX6Q_PAD_EIM_D23__GPIO_3_23 */
|
||||
1262 0x80000000 /* MX6Q_PAD_SD3_DAT5__GPIO_7_0 */
|
||||
1270 0x1f0b0 /* MX6Q_PAD_SD3_DAT4__GPIO_7_1 */
|
||||
953 0x80000000 /* MX6Q_PAD_GPIO_0__CCM_CLKO */
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -63,6 +68,9 @@
|
||||
aips-bus@02100000 { /* AIPS2 */
|
||||
usb@02184000 { /* USB OTG */
|
||||
vbus-supply = <®_usb_otg_vbus>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usbotg_1>;
|
||||
disable-over-current;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@ -71,12 +79,16 @@
|
||||
};
|
||||
|
||||
ethernet@02188000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_enet_1>;
|
||||
phy-mode = "rgmii";
|
||||
phy-reset-gpios = <&gpio3 23 0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usdhc@02198000 { /* uSDHC3 */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc3_2>;
|
||||
cd-gpios = <&gpio7 0 0>;
|
||||
wp-gpios = <&gpio7 1 0>;
|
||||
vmmc-supply = <®_3p3v>;
|
||||
@ -84,6 +96,8 @@
|
||||
};
|
||||
|
||||
usdhc@0219c000 { /* uSDHC4 */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc4_2>;
|
||||
cd-gpios = <&gpio2 6 0>;
|
||||
wp-gpios = <&gpio2 7 0>;
|
||||
vmmc-supply = <®_3p3v>;
|
||||
@ -99,7 +113,7 @@
|
||||
uart2: serial@021e8000 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_serial2_1>;
|
||||
pinctrl-0 = <&pinctrl_uart2_1>;
|
||||
};
|
||||
|
||||
i2c@021a0000 { /* I2C1 */
|
||||
@ -111,6 +125,7 @@
|
||||
codec: sgtl5000@0a {
|
||||
compatible = "fsl,sgtl5000";
|
||||
reg = <0x0a>;
|
||||
clocks = <&clks 169>;
|
||||
VDDA-supply = <®_2p5v>;
|
||||
VDDIO-supply = <®_3p3v>;
|
||||
};
|
||||
|
||||
@ -22,28 +22,51 @@
|
||||
};
|
||||
|
||||
soc {
|
||||
|
||||
aips-bus@02000000 { /* AIPS1 */
|
||||
spba-bus@02000000 {
|
||||
uart1: serial@02020000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1_1>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
iomuxc@020e0000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hog>;
|
||||
|
||||
hog {
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
1402 0x80000000 /* MX6Q_PAD_NANDF_D0__GPIO_2_0 */
|
||||
1410 0x80000000 /* MX6Q_PAD_NANDF_D1__GPIO_2_1 */
|
||||
1418 0x80000000 /* MX6Q_PAD_NANDF_D2__GPIO_2_2 */
|
||||
1426 0x80000000 /* MX6Q_PAD_NANDF_D3__GPIO_2_3 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
aips-bus@02100000 { /* AIPS2 */
|
||||
ethernet@02188000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_enet_1>;
|
||||
phy-mode = "rgmii";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usdhc@02194000 { /* uSDHC2 */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc2_1>;
|
||||
cd-gpios = <&gpio2 2 0>;
|
||||
wp-gpios = <&gpio2 3 0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usdhc@02198000 { /* uSDHC3 */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc3_1>;
|
||||
cd-gpios = <&gpio2 0 0>;
|
||||
wp-gpios = <&gpio2 1 0>;
|
||||
status = "okay";
|
||||
|
||||
@ -97,18 +97,23 @@
|
||||
dma-apbh@00110000 {
|
||||
compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
|
||||
reg = <0x00110000 0x2000>;
|
||||
clocks = <&clks 106>;
|
||||
};
|
||||
|
||||
gpmi-nand@00112000 {
|
||||
compatible = "fsl,imx6q-gpmi-nand";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
|
||||
reg-names = "gpmi-nand", "bch";
|
||||
interrupts = <0 13 0x04>, <0 15 0x04>;
|
||||
interrupt-names = "gpmi-dma", "bch";
|
||||
fsl,gpmi-dma-channel = <0>;
|
||||
status = "disabled";
|
||||
compatible = "fsl,imx6q-gpmi-nand";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
|
||||
reg-names = "gpmi-nand", "bch";
|
||||
interrupts = <0 13 0x04>, <0 15 0x04>;
|
||||
interrupt-names = "gpmi-dma", "bch";
|
||||
clocks = <&clks 152>, <&clks 153>, <&clks 151>,
|
||||
<&clks 150>, <&clks 149>;
|
||||
clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
|
||||
"gpmi_bch_apb", "per1_bch";
|
||||
fsl,gpmi-dma-channel = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer@00a00600 {
|
||||
@ -150,6 +155,8 @@
|
||||
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
|
||||
reg = <0x02008000 0x4000>;
|
||||
interrupts = <0 31 0x04>;
|
||||
clocks = <&clks 112>, <&clks 112>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -159,6 +166,8 @@
|
||||
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
|
||||
reg = <0x0200c000 0x4000>;
|
||||
interrupts = <0 32 0x04>;
|
||||
clocks = <&clks 113>, <&clks 113>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -168,6 +177,8 @@
|
||||
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
|
||||
reg = <0x02010000 0x4000>;
|
||||
interrupts = <0 33 0x04>;
|
||||
clocks = <&clks 114>, <&clks 114>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -177,6 +188,8 @@
|
||||
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
|
||||
reg = <0x02014000 0x4000>;
|
||||
interrupts = <0 34 0x04>;
|
||||
clocks = <&clks 115>, <&clks 115>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -186,6 +199,8 @@
|
||||
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
|
||||
reg = <0x02018000 0x4000>;
|
||||
interrupts = <0 35 0x04>;
|
||||
clocks = <&clks 116>, <&clks 116>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -193,6 +208,8 @@
|
||||
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
|
||||
reg = <0x02020000 0x4000>;
|
||||
interrupts = <0 26 0x04>;
|
||||
clocks = <&clks 160>, <&clks 161>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -205,6 +222,7 @@
|
||||
compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
|
||||
reg = <0x02028000 0x4000>;
|
||||
interrupts = <0 46 0x04>;
|
||||
clocks = <&clks 178>;
|
||||
fsl,fifo-depth = <15>;
|
||||
fsl,ssi-dma-events = <38 37>;
|
||||
status = "disabled";
|
||||
@ -214,6 +232,7 @@
|
||||
compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
|
||||
reg = <0x0202c000 0x4000>;
|
||||
interrupts = <0 47 0x04>;
|
||||
clocks = <&clks 179>;
|
||||
fsl,fifo-depth = <15>;
|
||||
fsl,ssi-dma-events = <42 41>;
|
||||
status = "disabled";
|
||||
@ -223,6 +242,7 @@
|
||||
compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
|
||||
reg = <0x02030000 0x4000>;
|
||||
interrupts = <0 48 0x04>;
|
||||
clocks = <&clks 180>;
|
||||
fsl,fifo-depth = <15>;
|
||||
fsl,ssi-dma-events = <46 45>;
|
||||
status = "disabled";
|
||||
@ -362,20 +382,22 @@
|
||||
compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
|
||||
reg = <0x020bc000 0x4000>;
|
||||
interrupts = <0 80 0x04>;
|
||||
status = "disabled";
|
||||
clocks = <&clks 0>;
|
||||
};
|
||||
|
||||
wdog@020c0000 { /* WDOG2 */
|
||||
compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
|
||||
reg = <0x020c0000 0x4000>;
|
||||
interrupts = <0 81 0x04>;
|
||||
clocks = <&clks 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ccm@020c4000 {
|
||||
clks: ccm@020c4000 {
|
||||
compatible = "fsl,imx6q-ccm";
|
||||
reg = <0x020c4000 0x4000>;
|
||||
interrupts = <0 87 0x04 0 88 0x04>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
anatop@020c8000 {
|
||||
@ -472,12 +494,14 @@
|
||||
compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
|
||||
reg = <0x020c9000 0x1000>;
|
||||
interrupts = <0 44 0x04>;
|
||||
clocks = <&clks 182>;
|
||||
};
|
||||
|
||||
usbphy2: usbphy@020ca000 {
|
||||
compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
|
||||
reg = <0x020ca000 0x1000>;
|
||||
interrupts = <0 45 0x04>;
|
||||
clocks = <&clks 183>;
|
||||
};
|
||||
|
||||
snvs@020cc000 {
|
||||
@ -514,86 +538,207 @@
|
||||
/* shared pinctrl settings */
|
||||
audmux {
|
||||
pinctrl_audmux_1: audmux-1 {
|
||||
fsl,pins = <18 0x80000000 /* MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */
|
||||
1586 0x80000000 /* MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */
|
||||
11 0x80000000 /* MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */
|
||||
3 0x80000000>; /* MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */
|
||||
};
|
||||
};
|
||||
|
||||
gpmi-nand {
|
||||
pinctrl_gpmi_nand_1: gpmi-nand-1 {
|
||||
fsl,pins = <1328 0xb0b1 /* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */
|
||||
1336 0xb0b1 /* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */
|
||||
1344 0xb0b1 /* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */
|
||||
1352 0xb000 /* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */
|
||||
1360 0xb0b1 /* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */
|
||||
1365 0xb0b1 /* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */
|
||||
1371 0xb0b1 /* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */
|
||||
1378 0xb0b1 /* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */
|
||||
1387 0xb0b1 /* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */
|
||||
1393 0xb0b1 /* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */
|
||||
1397 0xb0b1 /* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */
|
||||
1405 0xb0b1 /* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */
|
||||
1413 0xb0b1 /* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */
|
||||
1421 0xb0b1 /* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */
|
||||
1429 0xb0b1 /* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */
|
||||
1437 0xb0b1 /* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */
|
||||
1445 0xb0b1 /* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */
|
||||
1453 0xb0b1 /* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */
|
||||
1463 0x00b1>; /* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */
|
||||
};
|
||||
};
|
||||
|
||||
i2c1 {
|
||||
pinctrl_i2c1_1: i2c1grp-1 {
|
||||
fsl,pins = <137 0x4001b8b1 /* MX6Q_PAD_EIM_D21__I2C1_SCL */
|
||||
196 0x4001b8b1>; /* MX6Q_PAD_EIM_D28__I2C1_SDA */
|
||||
};
|
||||
};
|
||||
|
||||
serial2 {
|
||||
pinctrl_serial2_1: serial2grp-1 {
|
||||
fsl,pins = <183 0x1b0b1 /* MX6Q_PAD_EIM_D26__UART2_TXD */
|
||||
191 0x1b0b1>; /* MX6Q_PAD_EIM_D27__UART2_RXD */
|
||||
};
|
||||
};
|
||||
|
||||
usdhc3 {
|
||||
pinctrl_usdhc3_1: usdhc3grp-1 {
|
||||
fsl,pins = <1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
|
||||
1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */
|
||||
1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
|
||||
1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
|
||||
1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
|
||||
1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
|
||||
1265 0x17059 /* MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 */
|
||||
1257 0x17059 /* MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 */
|
||||
1249 0x17059 /* MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 */
|
||||
1241 0x17059>; /* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */
|
||||
};
|
||||
};
|
||||
|
||||
usdhc4 {
|
||||
pinctrl_usdhc4_1: usdhc4grp-1 {
|
||||
fsl,pins = <1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
|
||||
1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
|
||||
1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
|
||||
1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
|
||||
1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
|
||||
1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
|
||||
1493 0x17059 /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */
|
||||
1501 0x17059 /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */
|
||||
1509 0x17059 /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */
|
||||
1517 0x17059>; /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */
|
||||
fsl,pins = <
|
||||
18 0x80000000 /* MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */
|
||||
1586 0x80000000 /* MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */
|
||||
11 0x80000000 /* MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */
|
||||
3 0x80000000 /* MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
ecspi1 {
|
||||
pinctrl_ecspi1_1: ecspi1grp-1 {
|
||||
fsl,pins = <101 0x100b1 /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */
|
||||
109 0x100b1 /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */
|
||||
94 0x100b1>; /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */
|
||||
fsl,pins = <
|
||||
101 0x100b1 /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */
|
||||
109 0x100b1 /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */
|
||||
94 0x100b1 /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
enet {
|
||||
pinctrl_enet_1: enetgrp-1 {
|
||||
fsl,pins = <
|
||||
695 0x1b0b0 /* MX6Q_PAD_ENET_MDIO__ENET_MDIO */
|
||||
756 0x1b0b0 /* MX6Q_PAD_ENET_MDC__ENET_MDC */
|
||||
24 0x1b0b0 /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */
|
||||
30 0x1b0b0 /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */
|
||||
34 0x1b0b0 /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */
|
||||
39 0x1b0b0 /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */
|
||||
44 0x1b0b0 /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */
|
||||
56 0x1b0b0 /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */
|
||||
702 0x1b0b0 /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */
|
||||
74 0x1b0b0 /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */
|
||||
52 0x1b0b0 /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */
|
||||
61 0x1b0b0 /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */
|
||||
66 0x1b0b0 /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */
|
||||
70 0x1b0b0 /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */
|
||||
48 0x1b0b0 /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_enet_2: enetgrp-2 {
|
||||
fsl,pins = <
|
||||
890 0x1b0b0 /* MX6Q_PAD_KEY_COL1__ENET_MDIO */
|
||||
909 0x1b0b0 /* MX6Q_PAD_KEY_COL2__ENET_MDC */
|
||||
24 0x1b0b0 /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */
|
||||
30 0x1b0b0 /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */
|
||||
34 0x1b0b0 /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */
|
||||
39 0x1b0b0 /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */
|
||||
44 0x1b0b0 /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */
|
||||
56 0x1b0b0 /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */
|
||||
702 0x1b0b0 /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */
|
||||
74 0x1b0b0 /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */
|
||||
52 0x1b0b0 /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */
|
||||
61 0x1b0b0 /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */
|
||||
66 0x1b0b0 /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */
|
||||
70 0x1b0b0 /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */
|
||||
48 0x1b0b0 /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
gpmi-nand {
|
||||
pinctrl_gpmi_nand_1: gpmi-nand-1 {
|
||||
fsl,pins = <
|
||||
1328 0xb0b1 /* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */
|
||||
1336 0xb0b1 /* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */
|
||||
1344 0xb0b1 /* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */
|
||||
1352 0xb000 /* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */
|
||||
1360 0xb0b1 /* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */
|
||||
1365 0xb0b1 /* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */
|
||||
1371 0xb0b1 /* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */
|
||||
1378 0xb0b1 /* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */
|
||||
1387 0xb0b1 /* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */
|
||||
1393 0xb0b1 /* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */
|
||||
1397 0xb0b1 /* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */
|
||||
1405 0xb0b1 /* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */
|
||||
1413 0xb0b1 /* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */
|
||||
1421 0xb0b1 /* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */
|
||||
1429 0xb0b1 /* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */
|
||||
1437 0xb0b1 /* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */
|
||||
1445 0xb0b1 /* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */
|
||||
1453 0xb0b1 /* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */
|
||||
1463 0x00b1 /* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c1 {
|
||||
pinctrl_i2c1_1: i2c1grp-1 {
|
||||
fsl,pins = <
|
||||
137 0x4001b8b1 /* MX6Q_PAD_EIM_D21__I2C1_SCL */
|
||||
196 0x4001b8b1 /* MX6Q_PAD_EIM_D28__I2C1_SDA */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
uart1 {
|
||||
pinctrl_uart1_1: uart1grp-1 {
|
||||
fsl,pins = <
|
||||
1140 0x1b0b1 /* MX6Q_PAD_CSI0_DAT10__UART1_TXD */
|
||||
1148 0x1b0b1 /* MX6Q_PAD_CSI0_DAT11__UART1_RXD */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
uart2 {
|
||||
pinctrl_uart2_1: uart2grp-1 {
|
||||
fsl,pins = <
|
||||
183 0x1b0b1 /* MX6Q_PAD_EIM_D26__UART2_TXD */
|
||||
191 0x1b0b1 /* MX6Q_PAD_EIM_D27__UART2_RXD */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
uart4 {
|
||||
pinctrl_uart4_1: uart4grp-1 {
|
||||
fsl,pins = <
|
||||
877 0x1b0b1 /* MX6Q_PAD_KEY_COL0__UART4_TXD */
|
||||
885 0x1b0b1 /* MX6Q_PAD_KEY_ROW0__UART4_RXD */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
usbotg {
|
||||
pinctrl_usbotg_1: usbotggrp-1 {
|
||||
fsl,pins = <
|
||||
1592 0x17059 /* MX6Q_PAD_GPIO_1__ANATOP_USBOTG_ID */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
usdhc2 {
|
||||
pinctrl_usdhc2_1: usdhc2grp-1 {
|
||||
fsl,pins = <
|
||||
1577 0x17059 /* MX6Q_PAD_SD2_CMD__USDHC2_CMD */
|
||||
1569 0x10059 /* MX6Q_PAD_SD2_CLK__USDHC2_CLK */
|
||||
16 0x17059 /* MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 */
|
||||
0 0x17059 /* MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 */
|
||||
8 0x17059 /* MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 */
|
||||
1583 0x17059 /* MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 */
|
||||
1430 0x17059 /* MX6Q_PAD_NANDF_D4__USDHC2_DAT4 */
|
||||
1438 0x17059 /* MX6Q_PAD_NANDF_D5__USDHC2_DAT5 */
|
||||
1446 0x17059 /* MX6Q_PAD_NANDF_D6__USDHC2_DAT6 */
|
||||
1454 0x17059 /* MX6Q_PAD_NANDF_D7__USDHC2_DAT7 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
usdhc3 {
|
||||
pinctrl_usdhc3_1: usdhc3grp-1 {
|
||||
fsl,pins = <
|
||||
1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
|
||||
1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */
|
||||
1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
|
||||
1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
|
||||
1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
|
||||
1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
|
||||
1265 0x17059 /* MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 */
|
||||
1257 0x17059 /* MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 */
|
||||
1249 0x17059 /* MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 */
|
||||
1241 0x17059 /* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3_2: usdhc3grp-2 {
|
||||
fsl,pins = <
|
||||
1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
|
||||
1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */
|
||||
1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
|
||||
1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
|
||||
1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
|
||||
1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
usdhc4 {
|
||||
pinctrl_usdhc4_1: usdhc4grp-1 {
|
||||
fsl,pins = <
|
||||
1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
|
||||
1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
|
||||
1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
|
||||
1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
|
||||
1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
|
||||
1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
|
||||
1493 0x17059 /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */
|
||||
1501 0x17059 /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */
|
||||
1509 0x17059 /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */
|
||||
1517 0x17059 /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc4_2: usdhc4grp-2 {
|
||||
fsl,pins = <
|
||||
1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
|
||||
1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
|
||||
1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
|
||||
1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
|
||||
1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
|
||||
1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -612,6 +757,9 @@
|
||||
compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
|
||||
reg = <0x020ec000 0x4000>;
|
||||
interrupts = <0 2 0x04>;
|
||||
clocks = <&clks 155>, <&clks 155>;
|
||||
clock-names = "ipg", "ahb";
|
||||
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q-to1.bin";
|
||||
};
|
||||
};
|
||||
|
||||
@ -635,7 +783,9 @@
|
||||
compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
|
||||
reg = <0x02184000 0x200>;
|
||||
interrupts = <0 43 0x04>;
|
||||
clocks = <&clks 162>;
|
||||
fsl,usbphy = <&usbphy1>;
|
||||
fsl,usbmisc = <&usbmisc 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -643,7 +793,9 @@
|
||||
compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
|
||||
reg = <0x02184200 0x200>;
|
||||
interrupts = <0 40 0x04>;
|
||||
clocks = <&clks 162>;
|
||||
fsl,usbphy = <&usbphy2>;
|
||||
fsl,usbmisc = <&usbmisc 1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -651,6 +803,8 @@
|
||||
compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
|
||||
reg = <0x02184400 0x200>;
|
||||
interrupts = <0 41 0x04>;
|
||||
clocks = <&clks 162>;
|
||||
fsl,usbmisc = <&usbmisc 2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -658,13 +812,24 @@
|
||||
compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
|
||||
reg = <0x02184600 0x200>;
|
||||
interrupts = <0 42 0x04>;
|
||||
clocks = <&clks 162>;
|
||||
fsl,usbmisc = <&usbmisc 3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbmisc: usbmisc@02184800 {
|
||||
#index-cells = <1>;
|
||||
compatible = "fsl,imx6q-usbmisc";
|
||||
reg = <0x02184800 0x200>;
|
||||
clocks = <&clks 162>;
|
||||
};
|
||||
|
||||
ethernet@02188000 {
|
||||
compatible = "fsl,imx6q-fec";
|
||||
reg = <0x02188000 0x4000>;
|
||||
interrupts = <0 118 0x04 0 119 0x04>;
|
||||
clocks = <&clks 117>, <&clks 117>;
|
||||
clock-names = "ipg", "ahb";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -677,6 +842,8 @@
|
||||
compatible = "fsl,imx6q-usdhc";
|
||||
reg = <0x02190000 0x4000>;
|
||||
interrupts = <0 22 0x04>;
|
||||
clocks = <&clks 163>, <&clks 163>, <&clks 163>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -684,6 +851,8 @@
|
||||
compatible = "fsl,imx6q-usdhc";
|
||||
reg = <0x02194000 0x4000>;
|
||||
interrupts = <0 23 0x04>;
|
||||
clocks = <&clks 164>, <&clks 164>, <&clks 164>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -691,6 +860,8 @@
|
||||
compatible = "fsl,imx6q-usdhc";
|
||||
reg = <0x02198000 0x4000>;
|
||||
interrupts = <0 24 0x04>;
|
||||
clocks = <&clks 165>, <&clks 165>, <&clks 165>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -698,6 +869,8 @@
|
||||
compatible = "fsl,imx6q-usdhc";
|
||||
reg = <0x0219c000 0x4000>;
|
||||
interrupts = <0 25 0x04>;
|
||||
clocks = <&clks 166>, <&clks 166>, <&clks 166>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -707,6 +880,7 @@
|
||||
compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
|
||||
reg = <0x021a0000 0x4000>;
|
||||
interrupts = <0 36 0x04>;
|
||||
clocks = <&clks 125>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -716,6 +890,7 @@
|
||||
compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
|
||||
reg = <0x021a4000 0x4000>;
|
||||
interrupts = <0 37 0x04>;
|
||||
clocks = <&clks 126>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -725,6 +900,7 @@
|
||||
compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
|
||||
reg = <0x021a8000 0x4000>;
|
||||
interrupts = <0 38 0x04>;
|
||||
clocks = <&clks 127>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -788,6 +964,8 @@
|
||||
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
|
||||
reg = <0x021e8000 0x4000>;
|
||||
interrupts = <0 27 0x04>;
|
||||
clocks = <&clks 160>, <&clks 161>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -795,6 +973,8 @@
|
||||
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
|
||||
reg = <0x021ec000 0x4000>;
|
||||
interrupts = <0 28 0x04>;
|
||||
clocks = <&clks 160>, <&clks 161>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -802,6 +982,8 @@
|
||||
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
|
||||
reg = <0x021f0000 0x4000>;
|
||||
interrupts = <0 29 0x04>;
|
||||
clocks = <&clks 160>, <&clks 161>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -809,6 +991,8 @@
|
||||
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
|
||||
reg = <0x021f4000 0x4000>;
|
||||
interrupts = <0 30 0x04>;
|
||||
clocks = <&clks 160>, <&clks 161>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
@ -26,6 +26,11 @@
|
||||
interrupt-parent = <&intc>;
|
||||
ranges;
|
||||
|
||||
L2: l2-cache {
|
||||
compatible = "marvell,tauros2-cache";
|
||||
marvell,tauros2-cache-features = <0x3>;
|
||||
};
|
||||
|
||||
axi@d4200000 { /* AXI */
|
||||
compatible = "mrvl,axi-bus", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
|
||||
@ -7,7 +7,7 @@
|
||||
compatible = "qcom,msm8660-surf", "qcom,msm8660";
|
||||
interrupt-parent = <&intc>;
|
||||
|
||||
intc: interrupt-controller@02080000 {
|
||||
intc: interrupt-controller@2080000 {
|
||||
compatible = "qcom,msm-8660-qgic";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
@ -15,6 +15,23 @@
|
||||
< 0x02081000 0x1000 >;
|
||||
};
|
||||
|
||||
timer@2000004 {
|
||||
compatible = "qcom,msm-gpt", "qcom,msm-timer";
|
||||
interrupts = <1 1 0x301>;
|
||||
reg = <0x02000004 0x10>;
|
||||
clock-frequency = <32768>;
|
||||
cpu-offset = <0x40000>;
|
||||
};
|
||||
|
||||
timer@2000024 {
|
||||
compatible = "qcom,msm-dgt", "qcom,msm-timer";
|
||||
interrupts = <1 0 0x301>;
|
||||
reg = <0x02000024 0x10>,
|
||||
<0x02000034 0x4>;
|
||||
clock-frequency = <6750000>;
|
||||
cpu-offset = <0x40000>;
|
||||
};
|
||||
|
||||
serial@19c400000 {
|
||||
compatible = "qcom,msm-hsuart", "qcom,msm-uart";
|
||||
reg = <0x19c40000 0x1000>,
|
||||
|
||||
41
arch/arm/boot/dts/msm8960-cdp.dts
Normal file
41
arch/arm/boot/dts/msm8960-cdp.dts
Normal file
@ -0,0 +1,41 @@
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm MSM8960 CDP";
|
||||
compatible = "qcom,msm8960-cdp", "qcom,msm8960";
|
||||
interrupt-parent = <&intc>;
|
||||
|
||||
intc: interrupt-controller@2000000 {
|
||||
compatible = "qcom,msm-qgic2";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
reg = < 0x02000000 0x1000 >,
|
||||
< 0x02002000 0x1000 >;
|
||||
};
|
||||
|
||||
timer@200a004 {
|
||||
compatible = "qcom,msm-gpt", "qcom,msm-timer";
|
||||
interrupts = <1 2 0x301>;
|
||||
reg = <0x0200a004 0x10>;
|
||||
clock-frequency = <32768>;
|
||||
cpu-offset = <0x80000>;
|
||||
};
|
||||
|
||||
timer@200a024 {
|
||||
compatible = "qcom,msm-dgt", "qcom,msm-timer";
|
||||
interrupts = <1 1 0x301>;
|
||||
reg = <0x0200a024 0x10>,
|
||||
<0x0200a034 0x4>;
|
||||
clock-frequency = <6750000>;
|
||||
cpu-offset = <0x80000>;
|
||||
};
|
||||
|
||||
serial@19c400000 {
|
||||
compatible = "qcom,msm-hsuart", "qcom,msm-uart";
|
||||
reg = <0x16440000 0x1000>,
|
||||
<0x16400000 0x1000>;
|
||||
interrupts = <0 154 0x0>;
|
||||
};
|
||||
};
|
||||
@ -7,7 +7,7 @@
|
||||
*/
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "omap2.dtsi"
|
||||
/include/ "omap2420.dtsi"
|
||||
|
||||
/ {
|
||||
model = "TI OMAP2420 H4 board";
|
||||
|
||||
48
arch/arm/boot/dts/omap2420.dtsi
Normal file
48
arch/arm/boot/dts/omap2420.dtsi
Normal file
@ -0,0 +1,48 @@
|
||||
/*
|
||||
* Device Tree Source for OMAP2420 SoC
|
||||
*
|
||||
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
*/
|
||||
|
||||
/include/ "omap2.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "ti,omap2420", "ti,omap2";
|
||||
|
||||
ocp {
|
||||
omap2420_pmx: pinmux@48000030 {
|
||||
compatible = "ti,omap2420-padconf", "pinctrl-single";
|
||||
reg = <0x48000030 0x0113>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-single,register-width = <8>;
|
||||
pinctrl-single,function-mask = <0x3f>;
|
||||
};
|
||||
|
||||
mcbsp1: mcbsp@48074000 {
|
||||
compatible = "ti,omap2420-mcbsp";
|
||||
reg = <0x48074000 0xff>;
|
||||
reg-names = "mpu";
|
||||
interrupts = <59>, /* TX interrupt */
|
||||
<60>; /* RX interrupt */
|
||||
interrupt-names = "tx", "rx";
|
||||
interrupt-parent = <&intc>;
|
||||
ti,hwmods = "mcbsp1";
|
||||
};
|
||||
|
||||
mcbsp2: mcbsp@48076000 {
|
||||
compatible = "ti,omap2420-mcbsp";
|
||||
reg = <0x48076000 0xff>;
|
||||
reg-names = "mpu";
|
||||
interrupts = <62>, /* TX interrupt */
|
||||
<63>; /* RX interrupt */
|
||||
interrupt-names = "tx", "rx";
|
||||
interrupt-parent = <&intc>;
|
||||
ti,hwmods = "mcbsp2";
|
||||
};
|
||||
};
|
||||
};
|
||||
92
arch/arm/boot/dts/omap2430.dtsi
Normal file
92
arch/arm/boot/dts/omap2430.dtsi
Normal file
@ -0,0 +1,92 @@
|
||||
/*
|
||||
* Device Tree Source for OMAP243x SoC
|
||||
*
|
||||
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
*/
|
||||
|
||||
/include/ "omap2.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "ti,omap2430", "ti,omap2";
|
||||
|
||||
ocp {
|
||||
omap2430_pmx: pinmux@49002030 {
|
||||
compatible = "ti,omap2430-padconf", "pinctrl-single";
|
||||
reg = <0x49002030 0x0154>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-single,register-width = <8>;
|
||||
pinctrl-single,function-mask = <0x3f>;
|
||||
};
|
||||
|
||||
mcbsp1: mcbsp@48074000 {
|
||||
compatible = "ti,omap2430-mcbsp";
|
||||
reg = <0x48074000 0xff>;
|
||||
reg-names = "mpu";
|
||||
interrupts = <64>, /* OCP compliant interrupt */
|
||||
<59>, /* TX interrupt */
|
||||
<60>, /* RX interrupt */
|
||||
<61>; /* RX overflow interrupt */
|
||||
interrupt-names = "common", "tx", "rx", "rx_overflow";
|
||||
interrupt-parent = <&intc>;
|
||||
ti,buffer-size = <128>;
|
||||
ti,hwmods = "mcbsp1";
|
||||
};
|
||||
|
||||
mcbsp2: mcbsp@48076000 {
|
||||
compatible = "ti,omap2430-mcbsp";
|
||||
reg = <0x48076000 0xff>;
|
||||
reg-names = "mpu";
|
||||
interrupts = <16>, /* OCP compliant interrupt */
|
||||
<62>, /* TX interrupt */
|
||||
<63>; /* RX interrupt */
|
||||
interrupt-names = "common", "tx", "rx";
|
||||
interrupt-parent = <&intc>;
|
||||
ti,buffer-size = <128>;
|
||||
ti,hwmods = "mcbsp2";
|
||||
};
|
||||
|
||||
mcbsp3: mcbsp@4808c000 {
|
||||
compatible = "ti,omap2430-mcbsp";
|
||||
reg = <0x4808c000 0xff>;
|
||||
reg-names = "mpu";
|
||||
interrupts = <17>, /* OCP compliant interrupt */
|
||||
<89>, /* TX interrupt */
|
||||
<90>; /* RX interrupt */
|
||||
interrupt-names = "common", "tx", "rx";
|
||||
interrupt-parent = <&intc>;
|
||||
ti,buffer-size = <128>;
|
||||
ti,hwmods = "mcbsp3";
|
||||
};
|
||||
|
||||
mcbsp4: mcbsp@4808e000 {
|
||||
compatible = "ti,omap2430-mcbsp";
|
||||
reg = <0x4808e000 0xff>;
|
||||
reg-names = "mpu";
|
||||
interrupts = <18>, /* OCP compliant interrupt */
|
||||
<54>, /* TX interrupt */
|
||||
<55>; /* RX interrupt */
|
||||
interrupt-names = "common", "tx", "rx";
|
||||
interrupt-parent = <&intc>;
|
||||
ti,buffer-size = <128>;
|
||||
ti,hwmods = "mcbsp4";
|
||||
};
|
||||
|
||||
mcbsp5: mcbsp@48096000 {
|
||||
compatible = "ti,omap2430-mcbsp";
|
||||
reg = <0x48096000 0xff>;
|
||||
reg-names = "mpu";
|
||||
interrupts = <19>, /* OCP compliant interrupt */
|
||||
<81>, /* TX interrupt */
|
||||
<82>; /* RX interrupt */
|
||||
interrupt-names = "common", "tx", "rx";
|
||||
interrupt-parent = <&intc>;
|
||||
ti,buffer-size = <128>;
|
||||
ti,hwmods = "mcbsp5";
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -7,16 +7,44 @@
|
||||
*/
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "omap3.dtsi"
|
||||
/include/ "omap36xx.dtsi"
|
||||
|
||||
/ {
|
||||
model = "TI OMAP3 BeagleBoard";
|
||||
compatible = "ti,omap3-beagle", "ti,omap3";
|
||||
model = "TI OMAP3 BeagleBoard xM";
|
||||
compatible = "ti,omap3-beagle-xm, ti,omap3-beagle", "ti,omap3";
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x80000000 0x20000000>; /* 512 MB */
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pmu_stat {
|
||||
label = "beagleboard::pmu_stat";
|
||||
gpios = <&twl_gpio 19 0>; /* LEDB */
|
||||
};
|
||||
|
||||
heartbeat {
|
||||
label = "beagleboard::usr0";
|
||||
gpios = <&gpio5 22 0>; /* 150 -> D6 LED */
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
|
||||
mmc {
|
||||
label = "beagleboard::usr1";
|
||||
gpios = <&gpio5 21 0>; /* 149 -> D7 LED */
|
||||
linux,default-trigger = "mmc0";
|
||||
};
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "ti,omap-twl4030";
|
||||
ti,model = "omap3beagle";
|
||||
|
||||
ti,mcbsp = <&mcbsp2>;
|
||||
ti,codec = <&twl_audio>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
@ -27,11 +55,17 @@
|
||||
interrupts = <7>; /* SYS_NIRQ cascaded to intc */
|
||||
interrupt-parent = <&intc>;
|
||||
|
||||
vsim: regulator@10 {
|
||||
vsim: regulator-vsim {
|
||||
compatible = "ti,twl4030-vsim";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
};
|
||||
|
||||
twl_audio: audio {
|
||||
compatible = "ti,twl4030-audio";
|
||||
codec {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -67,3 +101,15 @@
|
||||
&mmc3 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&twl_gpio {
|
||||
ti,use-leds;
|
||||
/* pullups: BIT(1) */
|
||||
ti,pullups = <0x000002>;
|
||||
/*
|
||||
* pulldowns:
|
||||
* BIT(2), BIT(6), BIT(7), BIT(8), BIT(13)
|
||||
* BIT(15), BIT(16), BIT(17)
|
||||
*/
|
||||
ti,pulldowns = <0x03a1c4>;
|
||||
};
|
||||
@ -17,6 +17,15 @@
|
||||
device_type = "memory";
|
||||
reg = <0x80000000 0x10000000>; /* 256 MB */
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
ledb {
|
||||
label = "omap3evm::ledb";
|
||||
gpios = <&twl_gpio 19 0>; /* LEDB */
|
||||
linux,default-trigger = "default-on";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
@ -46,3 +55,7 @@
|
||||
reg = <0x5c>;
|
||||
};
|
||||
};
|
||||
|
||||
&twl_gpio {
|
||||
ti,use-leds;
|
||||
};
|
||||
|
||||
57
arch/arm/boot/dts/omap3-overo.dtsi
Normal file
57
arch/arm/boot/dts/omap3-overo.dtsi
Normal file
@ -0,0 +1,57 @@
|
||||
/*
|
||||
* Copyright (C) 2012 Florian Vaussard, EPFL Mobots group
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/*
|
||||
* The Gumstix Overo must be combined with an expansion board.
|
||||
*/
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "omap3.dtsi"
|
||||
|
||||
/ {
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
overo {
|
||||
label = "overo:blue:COM";
|
||||
gpios = <&twl_gpio 19 0>;
|
||||
linux,default-trigger = "mmc0";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
clock-frequency = <2600000>;
|
||||
|
||||
twl: twl@48 {
|
||||
reg = <0x48>;
|
||||
interrupts = <7>; /* SYS_NIRQ cascaded to intc */
|
||||
interrupt-parent = <&intc>;
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "twl4030.dtsi"
|
||||
|
||||
/* i2c2 pins are used for gpio */
|
||||
&i2c2 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* on board microSD slot */
|
||||
&mmc1 {
|
||||
vmmc-supply = <&vmmc1>;
|
||||
bus-width = <4>;
|
||||
};
|
||||
|
||||
/* optional on board WiFi */
|
||||
&mmc2 {
|
||||
bus-width = <4>;
|
||||
};
|
||||
|
||||
&twl_gpio {
|
||||
ti,use-leds;
|
||||
};
|
||||
35
arch/arm/boot/dts/omap3-tobi.dts
Normal file
35
arch/arm/boot/dts/omap3-tobi.dts
Normal file
@ -0,0 +1,35 @@
|
||||
/*
|
||||
* Copyright (C) 2012 Florian Vaussard, EPFL Mobots group
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Tobi expansion board is manufactured by Gumstix Inc.
|
||||
*/
|
||||
|
||||
/include/ "omap3-overo.dtsi"
|
||||
|
||||
/ {
|
||||
model = "TI OMAP3 Gumstix Overo on Tobi";
|
||||
compatible = "ti,omap3-tobi", "ti,omap3-overo", "ti,omap3";
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
heartbeat {
|
||||
label = "overo:red:gpio21";
|
||||
gpios = <&gpio1 21 0>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
&mmc3 {
|
||||
status = "disabled";
|
||||
};
|
||||
@ -17,7 +17,6 @@
|
||||
serial0 = &uart1;
|
||||
serial1 = &uart2;
|
||||
serial2 = &uart3;
|
||||
serial3 = &uart4;
|
||||
};
|
||||
|
||||
cpus {
|
||||
@ -69,6 +68,24 @@
|
||||
reg = <0x48200000 0x1000>;
|
||||
};
|
||||
|
||||
omap3_pmx_core: pinmux@48002030 {
|
||||
compatible = "ti,omap3-padconf", "pinctrl-single";
|
||||
reg = <0x48002030 0x05cc>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-single,register-width = <16>;
|
||||
pinctrl-single,function-mask = <0x7fff>;
|
||||
};
|
||||
|
||||
omap3_pmx_wkup: pinmux@0x48002a58 {
|
||||
compatible = "ti,omap3-padconf", "pinctrl-single";
|
||||
reg = <0x48002a58 0x5c>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-single,register-width = <16>;
|
||||
pinctrl-single,function-mask = <0x7fff>;
|
||||
};
|
||||
|
||||
gpio1: gpio@48310000 {
|
||||
compatible = "ti,omap3-gpio";
|
||||
ti,hwmods = "gpio1";
|
||||
@ -141,12 +158,6 @@
|
||||
clock-frequency = <48000000>;
|
||||
};
|
||||
|
||||
uart4: serial@49042000 {
|
||||
compatible = "ti,omap3-uart";
|
||||
ti,hwmods = "uart4";
|
||||
clock-frequency = <48000000>;
|
||||
};
|
||||
|
||||
i2c1: i2c@48070000 {
|
||||
compatible = "ti,omap3-i2c";
|
||||
#address-cells = <1>;
|
||||
@ -220,5 +231,74 @@
|
||||
compatible = "ti,omap3-wdt";
|
||||
ti,hwmods = "wd_timer2";
|
||||
};
|
||||
|
||||
mcbsp1: mcbsp@48074000 {
|
||||
compatible = "ti,omap3-mcbsp";
|
||||
reg = <0x48074000 0xff>;
|
||||
reg-names = "mpu";
|
||||
interrupts = <16>, /* OCP compliant interrupt */
|
||||
<59>, /* TX interrupt */
|
||||
<60>; /* RX interrupt */
|
||||
interrupt-names = "common", "tx", "rx";
|
||||
interrupt-parent = <&intc>;
|
||||
ti,buffer-size = <128>;
|
||||
ti,hwmods = "mcbsp1";
|
||||
};
|
||||
|
||||
mcbsp2: mcbsp@49022000 {
|
||||
compatible = "ti,omap3-mcbsp";
|
||||
reg = <0x49022000 0xff>,
|
||||
<0x49028000 0xff>;
|
||||
reg-names = "mpu", "sidetone";
|
||||
interrupts = <17>, /* OCP compliant interrupt */
|
||||
<62>, /* TX interrupt */
|
||||
<63>, /* RX interrupt */
|
||||
<4>; /* Sidetone */
|
||||
interrupt-names = "common", "tx", "rx", "sidetone";
|
||||
interrupt-parent = <&intc>;
|
||||
ti,buffer-size = <1280>;
|
||||
ti,hwmods = "mcbsp2";
|
||||
};
|
||||
|
||||
mcbsp3: mcbsp@49024000 {
|
||||
compatible = "ti,omap3-mcbsp";
|
||||
reg = <0x49024000 0xff>,
|
||||
<0x4902a000 0xff>;
|
||||
reg-names = "mpu", "sidetone";
|
||||
interrupts = <22>, /* OCP compliant interrupt */
|
||||
<89>, /* TX interrupt */
|
||||
<90>, /* RX interrupt */
|
||||
<5>; /* Sidetone */
|
||||
interrupt-names = "common", "tx", "rx", "sidetone";
|
||||
interrupt-parent = <&intc>;
|
||||
ti,buffer-size = <128>;
|
||||
ti,hwmods = "mcbsp3";
|
||||
};
|
||||
|
||||
mcbsp4: mcbsp@49026000 {
|
||||
compatible = "ti,omap3-mcbsp";
|
||||
reg = <0x49026000 0xff>;
|
||||
reg-names = "mpu";
|
||||
interrupts = <23>, /* OCP compliant interrupt */
|
||||
<54>, /* TX interrupt */
|
||||
<55>; /* RX interrupt */
|
||||
interrupt-names = "common", "tx", "rx";
|
||||
interrupt-parent = <&intc>;
|
||||
ti,buffer-size = <128>;
|
||||
ti,hwmods = "mcbsp4";
|
||||
};
|
||||
|
||||
mcbsp5: mcbsp@48096000 {
|
||||
compatible = "ti,omap3-mcbsp";
|
||||
reg = <0x48096000 0xff>;
|
||||
reg-names = "mpu";
|
||||
interrupts = <27>, /* OCP compliant interrupt */
|
||||
<81>, /* TX interrupt */
|
||||
<82>; /* RX interrupt */
|
||||
interrupt-names = "common", "tx", "rx";
|
||||
interrupt-parent = <&intc>;
|
||||
ti,buffer-size = <128>;
|
||||
ti,hwmods = "mcbsp5";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
25
arch/arm/boot/dts/omap36xx.dtsi
Normal file
25
arch/arm/boot/dts/omap36xx.dtsi
Normal file
@ -0,0 +1,25 @@
|
||||
/*
|
||||
* Device Tree Source for OMAP3 SoC
|
||||
*
|
||||
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
*/
|
||||
|
||||
/include/ "omap3.dtsi"
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
serial3 = &uart4;
|
||||
};
|
||||
|
||||
ocp {
|
||||
uart4: serial@49042000 {
|
||||
compatible = "ti,omap3-uart";
|
||||
ti,hwmods = "uart4";
|
||||
clock-frequency = <48000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -8,6 +8,7 @@
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "omap4.dtsi"
|
||||
/include/ "elpida_ecb240abacn.dtsi"
|
||||
|
||||
/ {
|
||||
model = "TI OMAP4 PandaBoard";
|
||||
@ -126,3 +127,13 @@
|
||||
ti,non-removable;
|
||||
bus-width = <4>;
|
||||
};
|
||||
|
||||
&emif1 {
|
||||
cs1-used;
|
||||
device-handle = <&elpida_ECB240ABACN>;
|
||||
};
|
||||
|
||||
&emif2 {
|
||||
cs1-used;
|
||||
device-handle = <&elpida_ECB240ABACN>;
|
||||
};
|
||||
|
||||
@ -8,6 +8,7 @@
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "omap4.dtsi"
|
||||
/include/ "elpida_ecb240abacn.dtsi"
|
||||
|
||||
/ {
|
||||
model = "TI OMAP4 SDP board";
|
||||
@ -18,7 +19,7 @@
|
||||
reg = <0x80000000 0x40000000>; /* 1 GB */
|
||||
};
|
||||
|
||||
vdd_eth: fixedregulator@0 {
|
||||
vdd_eth: fixedregulator-vdd-eth {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VDD_ETH";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
@ -28,7 +29,7 @@
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vbat: fixedregulator@2 {
|
||||
vbat: fixedregulator-vbat {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VBAT";
|
||||
regulator-min-microvolt = <3750000>;
|
||||
@ -115,6 +116,33 @@
|
||||
};
|
||||
};
|
||||
|
||||
&omap4_pmx_core {
|
||||
uart2_pins: pinmux_uart2_pins {
|
||||
pinctrl-single,pins = <
|
||||
0xd8 0x118 /* uart2_cts.uart2_cts INPUT_PULLUP | MODE0 */
|
||||
0xda 0 /* uart2_rts.uart2_rts OUTPUT | MODE0 */
|
||||
0xdc 0x118 /* uart2_rx.uart2_rx INPUT_PULLUP | MODE0 */
|
||||
0xde 0 /* uart2_tx.uart2_tx OUTPUT | MODE0 */
|
||||
>;
|
||||
};
|
||||
|
||||
uart3_pins: pinmux_uart3_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x100 0x118 /* uart3_cts_rctx.uart3_cts_rctx INPUT_PULLUP | MODE0 */
|
||||
0x102 0 /* uart3_rts_sd.uart3_rts_sd OUTPUT | MODE0 */
|
||||
0x104 0x100 /* uart3_rx_irrx.uart3_rx_irrx INPUT | MODE0 */
|
||||
0x106 0 /* uart3_tx_irtx.uart3_tx_irtx OUTPUT | MODE0 */
|
||||
>;
|
||||
};
|
||||
|
||||
uart4_pins: pinmux_uart4_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x11c 0x100 /* uart4_rx.uart4_rx INPUT | MODE0 */
|
||||
0x11e 0 /* uart4_tx.uart4_tx OUTPUT | MODE0 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
clock-frequency = <400000>;
|
||||
|
||||
@ -226,3 +254,98 @@
|
||||
bus-width = <4>;
|
||||
ti,non-removable;
|
||||
};
|
||||
|
||||
&emif1 {
|
||||
cs1-used;
|
||||
device-handle = <&elpida_ECB240ABACN>;
|
||||
};
|
||||
|
||||
&emif2 {
|
||||
cs1-used;
|
||||
device-handle = <&elpida_ECB240ABACN>;
|
||||
};
|
||||
|
||||
&keypad {
|
||||
keypad,num-rows = <8>;
|
||||
keypad,num-columns = <8>;
|
||||
linux,keymap = <0x00000012 /* KEY_E */
|
||||
0x00010013 /* KEY_R */
|
||||
0x00020014 /* KEY_T */
|
||||
0x00030066 /* KEY_HOME */
|
||||
0x0004003f /* KEY_F5 */
|
||||
0x000500f0 /* KEY_UNKNOWN */
|
||||
0x00060017 /* KEY_I */
|
||||
0x0007002a /* KEY_LEFTSHIFT */
|
||||
0x01000020 /* KEY_D*/
|
||||
0x01010021 /* KEY_F */
|
||||
0x01020022 /* KEY_G */
|
||||
0x010300e7 /* KEY_SEND */
|
||||
0x01040040 /* KEY_F6 */
|
||||
0x010500f0 /* KEY_UNKNOWN */
|
||||
0x01060025 /* KEY_K */
|
||||
0x0107001c /* KEY_ENTER */
|
||||
0x0200002d /* KEY_X */
|
||||
0x0201002e /* KEY_C */
|
||||
0x0202002f /* KEY_V */
|
||||
0x0203006b /* KEY_END */
|
||||
0x02040041 /* KEY_F7 */
|
||||
0x020500f0 /* KEY_UNKNOWN */
|
||||
0x02060034 /* KEY_DOT */
|
||||
0x0207003a /* KEY_CAPSLOCK */
|
||||
0x0300002c /* KEY_Z */
|
||||
0x0301004e /* KEY_KPLUS */
|
||||
0x03020030 /* KEY_B */
|
||||
0x0303003b /* KEY_F1 */
|
||||
0x03040042 /* KEY_F8 */
|
||||
0x030500f0 /* KEY_UNKNOWN */
|
||||
0x03060018 /* KEY_O */
|
||||
0x03070039 /* KEY_SPACE */
|
||||
0x04000011 /* KEY_W */
|
||||
0x04010015 /* KEY_Y */
|
||||
0x04020016 /* KEY_U */
|
||||
0x0403003c /* KEY_F2 */
|
||||
0x04040073 /* KEY_VOLUMEUP */
|
||||
0x040500f0 /* KEY_UNKNOWN */
|
||||
0x04060026 /* KEY_L */
|
||||
0x04070069 /* KEY_LEFT */
|
||||
0x0500001f /* KEY_S */
|
||||
0x05010023 /* KEY_H */
|
||||
0x05020024 /* KEY_J */
|
||||
0x0503003d /* KEY_F3 */
|
||||
0x05040043 /* KEY_F9 */
|
||||
0x05050072 /* KEY_VOLUMEDOWN */
|
||||
0x05060032 /* KEY_M */
|
||||
0x0507006a /* KEY_RIGHT */
|
||||
0x06000010 /* KEY_Q */
|
||||
0x0601001e /* KEY_A */
|
||||
0x06020031 /* KEY_N */
|
||||
0x0603009e /* KEY_BACK */
|
||||
0x0604000e /* KEY_BACKSPACE */
|
||||
0x060500f0 /* KEY_UNKNOWN */
|
||||
0x06060019 /* KEY_P */
|
||||
0x06070067 /* KEY_UP */
|
||||
0x07000094 /* KEY_PROG1 */
|
||||
0x07010095 /* KEY_PROG2 */
|
||||
0x070200ca /* KEY_PROG3 */
|
||||
0x070300cb /* KEY_PROG4 */
|
||||
0x0704003e /* KEY_F4 */
|
||||
0x070500f0 /* KEY_UNKNOWN */
|
||||
0x07060160 /* KEY_OK */
|
||||
0x0707006c>; /* KEY_DOWN */
|
||||
linux,input-no-autorepeat;
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart2_pins>;
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart3_pins>;
|
||||
};
|
||||
|
||||
&uart4 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart4_pins>;
|
||||
};
|
||||
|
||||
@ -30,12 +30,35 @@
|
||||
cpus {
|
||||
cpu@0 {
|
||||
compatible = "arm,cortex-a9";
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
cpu@1 {
|
||||
compatible = "arm,cortex-a9";
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
};
|
||||
|
||||
gic: interrupt-controller@48241000 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
reg = <0x48241000 0x1000>,
|
||||
<0x48240100 0x0100>;
|
||||
};
|
||||
|
||||
L2: l2-cache-controller@48242000 {
|
||||
compatible = "arm,pl310-cache";
|
||||
reg = <0x48242000 0x1000>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
};
|
||||
|
||||
local-timer@0x48240600 {
|
||||
compatible = "arm,cortex-a9-twd-timer";
|
||||
reg = <0x48240600 0x20>;
|
||||
interrupts = <1 13 0x304>;
|
||||
};
|
||||
|
||||
/*
|
||||
* The soc node represents the soc top level view. It is uses for IPs
|
||||
* that are not memory mapped in the MPU view or for the MPU itself.
|
||||
@ -61,30 +84,6 @@
|
||||
/*
|
||||
* XXX: Use a flat representation of the OMAP4 interconnect.
|
||||
* The real OMAP interconnect network is quite complex.
|
||||
*
|
||||
* MPU -+-- MPU_PRIVATE - GIC, L2
|
||||
* |
|
||||
* +----------------+----------+
|
||||
* | | |
|
||||
* + +- EMIF - DDR |
|
||||
* | | |
|
||||
* | + +--------+
|
||||
* | | |
|
||||
* | +- L4_ABE - AESS, MCBSP, TIMERs...
|
||||
* | |
|
||||
* +- L3_MAIN --+- L4_CORE - IPs...
|
||||
* |
|
||||
* +- L4_PER - IPs...
|
||||
* |
|
||||
* +- L4_CFG -+- L4_WKUP - IPs...
|
||||
* | |
|
||||
* | +- IPs...
|
||||
* +- IPU ----+
|
||||
* | |
|
||||
* +- DSP ----+
|
||||
* | |
|
||||
* +- DSS ----+
|
||||
*
|
||||
* Since that will not bring real advantage to represent that in DT for
|
||||
* the moment, just use a fake OCP bus entry to represent the whole bus
|
||||
* hierarchy.
|
||||
@ -96,16 +95,27 @@
|
||||
ranges;
|
||||
ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
|
||||
|
||||
gic: interrupt-controller@48241000 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
reg = <0x48241000 0x1000>,
|
||||
<0x48240100 0x0100>;
|
||||
omap4_pmx_core: pinmux@4a100040 {
|
||||
compatible = "ti,omap4-padconf", "pinctrl-single";
|
||||
reg = <0x4a100040 0x0196>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-single,register-width = <16>;
|
||||
pinctrl-single,function-mask = <0x7fff>;
|
||||
};
|
||||
omap4_pmx_wkup: pinmux@4a31e040 {
|
||||
compatible = "ti,omap4-padconf", "pinctrl-single";
|
||||
reg = <0x4a31e040 0x0038>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-single,register-width = <16>;
|
||||
pinctrl-single,function-mask = <0x7fff>;
|
||||
};
|
||||
|
||||
gpio1: gpio@4a310000 {
|
||||
compatible = "ti,omap4-gpio";
|
||||
reg = <0x4a310000 0x200>;
|
||||
interrupts = <0 29 0x4>;
|
||||
ti,hwmods = "gpio1";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
@ -115,6 +125,8 @@
|
||||
|
||||
gpio2: gpio@48055000 {
|
||||
compatible = "ti,omap4-gpio";
|
||||
reg = <0x48055000 0x200>;
|
||||
interrupts = <0 30 0x4>;
|
||||
ti,hwmods = "gpio2";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
@ -124,6 +136,8 @@
|
||||
|
||||
gpio3: gpio@48057000 {
|
||||
compatible = "ti,omap4-gpio";
|
||||
reg = <0x48057000 0x200>;
|
||||
interrupts = <0 31 0x4>;
|
||||
ti,hwmods = "gpio3";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
@ -133,6 +147,8 @@
|
||||
|
||||
gpio4: gpio@48059000 {
|
||||
compatible = "ti,omap4-gpio";
|
||||
reg = <0x48059000 0x200>;
|
||||
interrupts = <0 32 0x4>;
|
||||
ti,hwmods = "gpio4";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
@ -142,6 +158,8 @@
|
||||
|
||||
gpio5: gpio@4805b000 {
|
||||
compatible = "ti,omap4-gpio";
|
||||
reg = <0x4805b000 0x200>;
|
||||
interrupts = <0 33 0x4>;
|
||||
ti,hwmods = "gpio5";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
@ -151,6 +169,8 @@
|
||||
|
||||
gpio6: gpio@4805d000 {
|
||||
compatible = "ti,omap4-gpio";
|
||||
reg = <0x4805d000 0x200>;
|
||||
interrupts = <0 34 0x4>;
|
||||
ti,hwmods = "gpio6";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
@ -160,30 +180,40 @@
|
||||
|
||||
uart1: serial@4806a000 {
|
||||
compatible = "ti,omap4-uart";
|
||||
reg = <0x4806a000 0x100>;
|
||||
interrupts = <0 72 0x4>;
|
||||
ti,hwmods = "uart1";
|
||||
clock-frequency = <48000000>;
|
||||
};
|
||||
|
||||
uart2: serial@4806c000 {
|
||||
compatible = "ti,omap4-uart";
|
||||
reg = <0x4806c000 0x100>;
|
||||
interrupts = <0 73 0x4>;
|
||||
ti,hwmods = "uart2";
|
||||
clock-frequency = <48000000>;
|
||||
};
|
||||
|
||||
uart3: serial@48020000 {
|
||||
compatible = "ti,omap4-uart";
|
||||
reg = <0x48020000 0x100>;
|
||||
interrupts = <0 74 0x4>;
|
||||
ti,hwmods = "uart3";
|
||||
clock-frequency = <48000000>;
|
||||
};
|
||||
|
||||
uart4: serial@4806e000 {
|
||||
compatible = "ti,omap4-uart";
|
||||
reg = <0x4806e000 0x100>;
|
||||
interrupts = <0 70 0x4>;
|
||||
ti,hwmods = "uart4";
|
||||
clock-frequency = <48000000>;
|
||||
};
|
||||
|
||||
i2c1: i2c@48070000 {
|
||||
compatible = "ti,omap4-i2c";
|
||||
reg = <0x48070000 0x100>;
|
||||
interrupts = <0 56 0x4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
ti,hwmods = "i2c1";
|
||||
@ -191,6 +221,8 @@
|
||||
|
||||
i2c2: i2c@48072000 {
|
||||
compatible = "ti,omap4-i2c";
|
||||
reg = <0x48072000 0x100>;
|
||||
interrupts = <0 57 0x4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
ti,hwmods = "i2c2";
|
||||
@ -198,6 +230,8 @@
|
||||
|
||||
i2c3: i2c@48060000 {
|
||||
compatible = "ti,omap4-i2c";
|
||||
reg = <0x48060000 0x100>;
|
||||
interrupts = <0 61 0x4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
ti,hwmods = "i2c3";
|
||||
@ -205,6 +239,8 @@
|
||||
|
||||
i2c4: i2c@48350000 {
|
||||
compatible = "ti,omap4-i2c";
|
||||
reg = <0x48350000 0x100>;
|
||||
interrupts = <0 62 0x4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
ti,hwmods = "i2c4";
|
||||
@ -212,6 +248,8 @@
|
||||
|
||||
mcspi1: spi@48098000 {
|
||||
compatible = "ti,omap4-mcspi";
|
||||
reg = <0x48098000 0x200>;
|
||||
interrupts = <0 65 0x4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
ti,hwmods = "mcspi1";
|
||||
@ -220,6 +258,8 @@
|
||||
|
||||
mcspi2: spi@4809a000 {
|
||||
compatible = "ti,omap4-mcspi";
|
||||
reg = <0x4809a000 0x200>;
|
||||
interrupts = <0 66 0x4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
ti,hwmods = "mcspi2";
|
||||
@ -228,6 +268,8 @@
|
||||
|
||||
mcspi3: spi@480b8000 {
|
||||
compatible = "ti,omap4-mcspi";
|
||||
reg = <0x480b8000 0x200>;
|
||||
interrupts = <0 91 0x4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
ti,hwmods = "mcspi3";
|
||||
@ -236,6 +278,8 @@
|
||||
|
||||
mcspi4: spi@480ba000 {
|
||||
compatible = "ti,omap4-mcspi";
|
||||
reg = <0x480ba000 0x200>;
|
||||
interrupts = <0 48 0x4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
ti,hwmods = "mcspi4";
|
||||
@ -244,6 +288,8 @@
|
||||
|
||||
mmc1: mmc@4809c000 {
|
||||
compatible = "ti,omap4-hsmmc";
|
||||
reg = <0x4809c000 0x400>;
|
||||
interrupts = <0 83 0x4>;
|
||||
ti,hwmods = "mmc1";
|
||||
ti,dual-volt;
|
||||
ti,needs-special-reset;
|
||||
@ -251,30 +297,40 @@
|
||||
|
||||
mmc2: mmc@480b4000 {
|
||||
compatible = "ti,omap4-hsmmc";
|
||||
reg = <0x480b4000 0x400>;
|
||||
interrupts = <0 86 0x4>;
|
||||
ti,hwmods = "mmc2";
|
||||
ti,needs-special-reset;
|
||||
};
|
||||
|
||||
mmc3: mmc@480ad000 {
|
||||
compatible = "ti,omap4-hsmmc";
|
||||
reg = <0x480ad000 0x400>;
|
||||
interrupts = <0 94 0x4>;
|
||||
ti,hwmods = "mmc3";
|
||||
ti,needs-special-reset;
|
||||
};
|
||||
|
||||
mmc4: mmc@480d1000 {
|
||||
compatible = "ti,omap4-hsmmc";
|
||||
reg = <0x480d1000 0x400>;
|
||||
interrupts = <0 96 0x4>;
|
||||
ti,hwmods = "mmc4";
|
||||
ti,needs-special-reset;
|
||||
};
|
||||
|
||||
mmc5: mmc@480d5000 {
|
||||
compatible = "ti,omap4-hsmmc";
|
||||
reg = <0x480d5000 0x400>;
|
||||
interrupts = <0 59 0x4>;
|
||||
ti,hwmods = "mmc5";
|
||||
ti,needs-special-reset;
|
||||
};
|
||||
|
||||
wdt2: wdt@4a314000 {
|
||||
compatible = "ti,omap4-wdt", "ti,omap3-wdt";
|
||||
reg = <0x4a314000 0x80>;
|
||||
interrupts = <0 80 0x4>;
|
||||
ti,hwmods = "wd_timer2";
|
||||
};
|
||||
|
||||
@ -282,6 +338,7 @@
|
||||
compatible = "ti,omap4-mcpdm";
|
||||
reg = <0x40132000 0x7f>, /* MPU private access */
|
||||
<0x49032000 0x7f>; /* L3 Interconnect */
|
||||
reg-names = "mpu", "dma";
|
||||
interrupts = <0 112 0x4>;
|
||||
interrupt-parent = <&gic>;
|
||||
ti,hwmods = "mcpdm";
|
||||
@ -291,9 +348,87 @@
|
||||
compatible = "ti,omap4-dmic";
|
||||
reg = <0x4012e000 0x7f>, /* MPU private access */
|
||||
<0x4902e000 0x7f>; /* L3 Interconnect */
|
||||
reg-names = "mpu", "dma";
|
||||
interrupts = <0 114 0x4>;
|
||||
interrupt-parent = <&gic>;
|
||||
ti,hwmods = "dmic";
|
||||
};
|
||||
|
||||
mcbsp1: mcbsp@40122000 {
|
||||
compatible = "ti,omap4-mcbsp";
|
||||
reg = <0x40122000 0xff>, /* MPU private access */
|
||||
<0x49022000 0xff>; /* L3 Interconnect */
|
||||
reg-names = "mpu", "dma";
|
||||
interrupts = <0 17 0x4>;
|
||||
interrupt-names = "common";
|
||||
interrupt-parent = <&gic>;
|
||||
ti,buffer-size = <128>;
|
||||
ti,hwmods = "mcbsp1";
|
||||
};
|
||||
|
||||
mcbsp2: mcbsp@40124000 {
|
||||
compatible = "ti,omap4-mcbsp";
|
||||
reg = <0x40124000 0xff>, /* MPU private access */
|
||||
<0x49024000 0xff>; /* L3 Interconnect */
|
||||
reg-names = "mpu", "dma";
|
||||
interrupts = <0 22 0x4>;
|
||||
interrupt-names = "common";
|
||||
interrupt-parent = <&gic>;
|
||||
ti,buffer-size = <128>;
|
||||
ti,hwmods = "mcbsp2";
|
||||
};
|
||||
|
||||
mcbsp3: mcbsp@40126000 {
|
||||
compatible = "ti,omap4-mcbsp";
|
||||
reg = <0x40126000 0xff>, /* MPU private access */
|
||||
<0x49026000 0xff>; /* L3 Interconnect */
|
||||
reg-names = "mpu", "dma";
|
||||
interrupts = <0 23 0x4>;
|
||||
interrupt-names = "common";
|
||||
interrupt-parent = <&gic>;
|
||||
ti,buffer-size = <128>;
|
||||
ti,hwmods = "mcbsp3";
|
||||
};
|
||||
|
||||
mcbsp4: mcbsp@48096000 {
|
||||
compatible = "ti,omap4-mcbsp";
|
||||
reg = <0x48096000 0xff>; /* L4 Interconnect */
|
||||
reg-names = "mpu";
|
||||
interrupts = <0 16 0x4>;
|
||||
interrupt-names = "common";
|
||||
interrupt-parent = <&gic>;
|
||||
ti,buffer-size = <128>;
|
||||
ti,hwmods = "mcbsp4";
|
||||
};
|
||||
|
||||
keypad: keypad@4a31c000 {
|
||||
compatible = "ti,omap4-keypad";
|
||||
reg = <0x4a31c000 0x80>;
|
||||
interrupts = <0 120 0x4>;
|
||||
reg-names = "mpu";
|
||||
ti,hwmods = "kbd";
|
||||
};
|
||||
|
||||
emif1: emif@4c000000 {
|
||||
compatible = "ti,emif-4d";
|
||||
reg = <0x4c000000 0x100>;
|
||||
interrupts = <0 110 0x4>;
|
||||
ti,hwmods = "emif1";
|
||||
phy-type = <1>;
|
||||
hw-caps-read-idle-ctrl;
|
||||
hw-caps-ll-interface;
|
||||
hw-caps-temp-alert;
|
||||
};
|
||||
|
||||
emif2: emif@4d000000 {
|
||||
compatible = "ti,emif-4d";
|
||||
reg = <0x4d000000 0x100>;
|
||||
interrupts = <0 111 0x4>;
|
||||
ti,hwmods = "emif2";
|
||||
phy-type = <1>;
|
||||
hw-caps-read-idle-ctrl;
|
||||
hw-caps-ll-interface;
|
||||
hw-caps-temp-alert;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -17,4 +17,68 @@
|
||||
device_type = "memory";
|
||||
reg = <0x80000000 0x40000000>; /* 1 GB */
|
||||
};
|
||||
|
||||
vmmcsd_fixed: fixedregulator-mmcsd {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vmmcsd_fixed";
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
&mmc1 {
|
||||
vmmc-supply = <&vmmcsd_fixed>;
|
||||
bus-width = <4>;
|
||||
};
|
||||
|
||||
&mmc2 {
|
||||
vmmc-supply = <&vmmcsd_fixed>;
|
||||
bus-width = <8>;
|
||||
ti,non-removable;
|
||||
};
|
||||
|
||||
&mmc3 {
|
||||
bus-width = <4>;
|
||||
ti,non-removable;
|
||||
};
|
||||
|
||||
&mmc4 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mmc5 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
clock-frequency = <400000>;
|
||||
|
||||
/* Pressure Sensor */
|
||||
bmp085@77 {
|
||||
compatible = "bosch,bmp085";
|
||||
reg = <0x77>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
clock-frequency = <400000>;
|
||||
|
||||
/* Temperature Sensor */
|
||||
tmp102@48{
|
||||
compatible = "ti,tmp102";
|
||||
reg = <0x48>;
|
||||
};
|
||||
};
|
||||
|
||||
&keypad {
|
||||
keypad,num-rows = <8>;
|
||||
keypad,num-columns = <8>;
|
||||
linux,keymap = <0x02020073 /* VOLUP */
|
||||
0x02030072 /* VOLDOWM */
|
||||
0x020400e7 /* SEND */
|
||||
0x02050066 /* HOME */
|
||||
0x0206006b /* END */
|
||||
0x020700d9>; /* SEARCH */
|
||||
linux,input-no-autorepeat;
|
||||
};
|
||||
|
||||
@ -145,6 +145,41 @@
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
i2c1: i2c@48070000 {
|
||||
compatible = "ti,omap4-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
ti,hwmods = "i2c1";
|
||||
};
|
||||
|
||||
i2c2: i2c@48072000 {
|
||||
compatible = "ti,omap4-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
ti,hwmods = "i2c2";
|
||||
};
|
||||
|
||||
i2c3: i2c@48060000 {
|
||||
compatible = "ti,omap4-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
ti,hwmods = "i2c3";
|
||||
};
|
||||
|
||||
i2c4: i2c@4807A000 {
|
||||
compatible = "ti,omap4-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
ti,hwmods = "i2c4";
|
||||
};
|
||||
|
||||
i2c5: i2c@4807C000 {
|
||||
compatible = "ti,omap4-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
ti,hwmods = "i2c5";
|
||||
};
|
||||
|
||||
uart1: serial@4806a000 {
|
||||
compatible = "ti,omap4-uart";
|
||||
ti,hwmods = "uart1";
|
||||
@ -180,5 +215,97 @@
|
||||
ti,hwmods = "uart6";
|
||||
clock-frequency = <48000000>;
|
||||
};
|
||||
|
||||
mmc1: mmc@4809c000 {
|
||||
compatible = "ti,omap4-hsmmc";
|
||||
ti,hwmods = "mmc1";
|
||||
ti,dual-volt;
|
||||
ti,needs-special-reset;
|
||||
};
|
||||
|
||||
mmc2: mmc@480b4000 {
|
||||
compatible = "ti,omap4-hsmmc";
|
||||
ti,hwmods = "mmc2";
|
||||
ti,needs-special-reset;
|
||||
};
|
||||
|
||||
mmc3: mmc@480ad000 {
|
||||
compatible = "ti,omap4-hsmmc";
|
||||
ti,hwmods = "mmc3";
|
||||
ti,needs-special-reset;
|
||||
};
|
||||
|
||||
mmc4: mmc@480d1000 {
|
||||
compatible = "ti,omap4-hsmmc";
|
||||
ti,hwmods = "mmc4";
|
||||
ti,needs-special-reset;
|
||||
};
|
||||
|
||||
mmc5: mmc@480d5000 {
|
||||
compatible = "ti,omap4-hsmmc";
|
||||
ti,hwmods = "mmc5";
|
||||
ti,needs-special-reset;
|
||||
};
|
||||
|
||||
keypad: keypad@4ae1c000 {
|
||||
compatible = "ti,omap4-keypad";
|
||||
ti,hwmods = "kbd";
|
||||
};
|
||||
|
||||
mcpdm: mcpdm@40132000 {
|
||||
compatible = "ti,omap4-mcpdm";
|
||||
reg = <0x40132000 0x7f>, /* MPU private access */
|
||||
<0x49032000 0x7f>; /* L3 Interconnect */
|
||||
reg-names = "mpu", "dma";
|
||||
interrupts = <0 112 0x4>;
|
||||
interrupt-parent = <&gic>;
|
||||
ti,hwmods = "mcpdm";
|
||||
};
|
||||
|
||||
dmic: dmic@4012e000 {
|
||||
compatible = "ti,omap4-dmic";
|
||||
reg = <0x4012e000 0x7f>, /* MPU private access */
|
||||
<0x4902e000 0x7f>; /* L3 Interconnect */
|
||||
reg-names = "mpu", "dma";
|
||||
interrupts = <0 114 0x4>;
|
||||
interrupt-parent = <&gic>;
|
||||
ti,hwmods = "dmic";
|
||||
};
|
||||
|
||||
mcbsp1: mcbsp@40122000 {
|
||||
compatible = "ti,omap4-mcbsp";
|
||||
reg = <0x40122000 0xff>, /* MPU private access */
|
||||
<0x49022000 0xff>; /* L3 Interconnect */
|
||||
reg-names = "mpu", "dma";
|
||||
interrupts = <0 17 0x4>;
|
||||
interrupt-names = "common";
|
||||
interrupt-parent = <&gic>;
|
||||
ti,buffer-size = <128>;
|
||||
ti,hwmods = "mcbsp1";
|
||||
};
|
||||
|
||||
mcbsp2: mcbsp@40124000 {
|
||||
compatible = "ti,omap4-mcbsp";
|
||||
reg = <0x40124000 0xff>, /* MPU private access */
|
||||
<0x49024000 0xff>; /* L3 Interconnect */
|
||||
reg-names = "mpu", "dma";
|
||||
interrupts = <0 22 0x4>;
|
||||
interrupt-names = "common";
|
||||
interrupt-parent = <&gic>;
|
||||
ti,buffer-size = <128>;
|
||||
ti,hwmods = "mcbsp2";
|
||||
};
|
||||
|
||||
mcbsp3: mcbsp@40126000 {
|
||||
compatible = "ti,omap4-mcbsp";
|
||||
reg = <0x40126000 0xff>, /* MPU private access */
|
||||
<0x49026000 0xff>; /* L3 Interconnect */
|
||||
reg-names = "mpu", "dma";
|
||||
interrupts = <0 23 0x4>;
|
||||
interrupt-names = "common";
|
||||
interrupt-parent = <&gic>;
|
||||
ti,buffer-size = <128>;
|
||||
ti,hwmods = "mcbsp3";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -135,13 +135,11 @@
|
||||
ssp0: ssp@20084000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pl022,num-chipselects = <1>;
|
||||
num-cs = <1>;
|
||||
cs-gpios = <&gpio 3 5 0>;
|
||||
|
||||
eeprom: at25@0 {
|
||||
pl022,hierarchy = <0>;
|
||||
pl022,interface = <0>;
|
||||
pl022,slave-tx-disable = <0>;
|
||||
pl022,com-mode = <0>;
|
||||
pl022,rx-level-trig = <1>;
|
||||
pl022,tx-level-trig = <1>;
|
||||
|
||||
@ -1,424 +0,0 @@
|
||||
/dts-v1/;
|
||||
/ {
|
||||
model = "SiRF Prima2 eVB";
|
||||
compatible = "sirf,prima2-cb", "sirf,prima2";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupt-parent = <&intc>;
|
||||
|
||||
memory {
|
||||
reg = <0x00000000 0x20000000>;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "mem=512M real_root=/dev/mmcblk0p2 console=ttyS0 panel=1 bootsplash=true bpp=16 androidboot.console=ttyS1";
|
||||
linux,stdout-path = &uart1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
reg = <0x0>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-size = <32768>;
|
||||
i-cache-size = <32768>;
|
||||
/* from bootloader */
|
||||
timebase-frequency = <0>;
|
||||
bus-frequency = <0>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
axi {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x40000000 0x40000000 0x80000000>;
|
||||
|
||||
l2-cache-controller@80040000 {
|
||||
compatible = "arm,pl310-cache", "sirf,prima2-pl310-cache";
|
||||
reg = <0x80040000 0x1000>;
|
||||
interrupts = <59>;
|
||||
arm,tag-latency = <1 1 1>;
|
||||
arm,data-latency = <1 1 1>;
|
||||
arm,filter-ranges = <0 0x40000000>;
|
||||
};
|
||||
|
||||
intc: interrupt-controller@80020000 {
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-controller;
|
||||
compatible = "sirf,prima2-intc";
|
||||
reg = <0x80020000 0x1000>;
|
||||
};
|
||||
|
||||
sys-iobg {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x88000000 0x88000000 0x40000>;
|
||||
|
||||
clock-controller@88000000 {
|
||||
compatible = "sirf,prima2-clkc";
|
||||
reg = <0x88000000 0x1000>;
|
||||
interrupts = <3>;
|
||||
};
|
||||
|
||||
reset-controller@88010000 {
|
||||
compatible = "sirf,prima2-rstc";
|
||||
reg = <0x88010000 0x1000>;
|
||||
};
|
||||
|
||||
rsc-controller@88020000 {
|
||||
compatible = "sirf,prima2-rsc";
|
||||
reg = <0x88020000 0x1000>;
|
||||
};
|
||||
};
|
||||
|
||||
mem-iobg {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x90000000 0x90000000 0x10000>;
|
||||
|
||||
memory-controller@90000000 {
|
||||
compatible = "sirf,prima2-memc";
|
||||
reg = <0x90000000 0x10000>;
|
||||
interrupts = <27>;
|
||||
};
|
||||
};
|
||||
|
||||
disp-iobg {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x90010000 0x90010000 0x30000>;
|
||||
|
||||
display@90010000 {
|
||||
compatible = "sirf,prima2-lcd";
|
||||
reg = <0x90010000 0x20000>;
|
||||
interrupts = <30>;
|
||||
};
|
||||
|
||||
vpp@90020000 {
|
||||
compatible = "sirf,prima2-vpp";
|
||||
reg = <0x90020000 0x10000>;
|
||||
interrupts = <31>;
|
||||
};
|
||||
};
|
||||
|
||||
graphics-iobg {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x98000000 0x98000000 0x8000000>;
|
||||
|
||||
graphics@98000000 {
|
||||
compatible = "powervr,sgx531";
|
||||
reg = <0x98000000 0x8000000>;
|
||||
interrupts = <6>;
|
||||
};
|
||||
};
|
||||
|
||||
multimedia-iobg {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0xa0000000 0xa0000000 0x8000000>;
|
||||
|
||||
multimedia@a0000000 {
|
||||
compatible = "sirf,prima2-video-codec";
|
||||
reg = <0xa0000000 0x8000000>;
|
||||
interrupts = <5>;
|
||||
};
|
||||
};
|
||||
|
||||
dsp-iobg {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0xa8000000 0xa8000000 0x2000000>;
|
||||
|
||||
dspif@a8000000 {
|
||||
compatible = "sirf,prima2-dspif";
|
||||
reg = <0xa8000000 0x10000>;
|
||||
interrupts = <9>;
|
||||
};
|
||||
|
||||
gps@a8010000 {
|
||||
compatible = "sirf,prima2-gps";
|
||||
reg = <0xa8010000 0x10000>;
|
||||
interrupts = <7>;
|
||||
};
|
||||
|
||||
dsp@a9000000 {
|
||||
compatible = "sirf,prima2-dsp";
|
||||
reg = <0xa9000000 0x1000000>;
|
||||
interrupts = <8>;
|
||||
};
|
||||
};
|
||||
|
||||
peri-iobg {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0xb0000000 0xb0000000 0x180000>;
|
||||
|
||||
timer@b0020000 {
|
||||
compatible = "sirf,prima2-tick";
|
||||
reg = <0xb0020000 0x1000>;
|
||||
interrupts = <0>;
|
||||
};
|
||||
|
||||
nand@b0030000 {
|
||||
compatible = "sirf,prima2-nand";
|
||||
reg = <0xb0030000 0x10000>;
|
||||
interrupts = <41>;
|
||||
};
|
||||
|
||||
audio@b0040000 {
|
||||
compatible = "sirf,prima2-audio";
|
||||
reg = <0xb0040000 0x10000>;
|
||||
interrupts = <35>;
|
||||
};
|
||||
|
||||
uart0: uart@b0050000 {
|
||||
cell-index = <0>;
|
||||
compatible = "sirf,prima2-uart";
|
||||
reg = <0xb0050000 0x10000>;
|
||||
interrupts = <17>;
|
||||
};
|
||||
|
||||
uart1: uart@b0060000 {
|
||||
cell-index = <1>;
|
||||
compatible = "sirf,prima2-uart";
|
||||
reg = <0xb0060000 0x10000>;
|
||||
interrupts = <18>;
|
||||
};
|
||||
|
||||
uart2: uart@b0070000 {
|
||||
cell-index = <2>;
|
||||
compatible = "sirf,prima2-uart";
|
||||
reg = <0xb0070000 0x10000>;
|
||||
interrupts = <19>;
|
||||
};
|
||||
|
||||
usp0: usp@b0080000 {
|
||||
cell-index = <0>;
|
||||
compatible = "sirf,prima2-usp";
|
||||
reg = <0xb0080000 0x10000>;
|
||||
interrupts = <20>;
|
||||
};
|
||||
|
||||
usp1: usp@b0090000 {
|
||||
cell-index = <1>;
|
||||
compatible = "sirf,prima2-usp";
|
||||
reg = <0xb0090000 0x10000>;
|
||||
interrupts = <21>;
|
||||
};
|
||||
|
||||
usp2: usp@b00a0000 {
|
||||
cell-index = <2>;
|
||||
compatible = "sirf,prima2-usp";
|
||||
reg = <0xb00a0000 0x10000>;
|
||||
interrupts = <22>;
|
||||
};
|
||||
|
||||
dmac0: dma-controller@b00b0000 {
|
||||
cell-index = <0>;
|
||||
compatible = "sirf,prima2-dmac";
|
||||
reg = <0xb00b0000 0x10000>;
|
||||
interrupts = <12>;
|
||||
};
|
||||
|
||||
dmac1: dma-controller@b0160000 {
|
||||
cell-index = <1>;
|
||||
compatible = "sirf,prima2-dmac";
|
||||
reg = <0xb0160000 0x10000>;
|
||||
interrupts = <13>;
|
||||
};
|
||||
|
||||
vip@b00C0000 {
|
||||
compatible = "sirf,prima2-vip";
|
||||
reg = <0xb00C0000 0x10000>;
|
||||
};
|
||||
|
||||
spi0: spi@b00d0000 {
|
||||
cell-index = <0>;
|
||||
compatible = "sirf,prima2-spi";
|
||||
reg = <0xb00d0000 0x10000>;
|
||||
interrupts = <15>;
|
||||
};
|
||||
|
||||
spi1: spi@b0170000 {
|
||||
cell-index = <1>;
|
||||
compatible = "sirf,prima2-spi";
|
||||
reg = <0xb0170000 0x10000>;
|
||||
interrupts = <16>;
|
||||
};
|
||||
|
||||
i2c0: i2c@b00e0000 {
|
||||
cell-index = <0>;
|
||||
compatible = "sirf,prima2-i2c";
|
||||
reg = <0xb00e0000 0x10000>;
|
||||
interrupts = <24>;
|
||||
};
|
||||
|
||||
i2c1: i2c@b00f0000 {
|
||||
cell-index = <1>;
|
||||
compatible = "sirf,prima2-i2c";
|
||||
reg = <0xb00f0000 0x10000>;
|
||||
interrupts = <25>;
|
||||
};
|
||||
|
||||
tsc@b0110000 {
|
||||
compatible = "sirf,prima2-tsc";
|
||||
reg = <0xb0110000 0x10000>;
|
||||
interrupts = <33>;
|
||||
};
|
||||
|
||||
gpio: gpio-controller@b0120000 {
|
||||
#gpio-cells = <2>;
|
||||
#interrupt-cells = <2>;
|
||||
compatible = "sirf,prima2-gpio-pinmux";
|
||||
reg = <0xb0120000 0x10000>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
};
|
||||
|
||||
pwm@b0130000 {
|
||||
compatible = "sirf,prima2-pwm";
|
||||
reg = <0xb0130000 0x10000>;
|
||||
};
|
||||
|
||||
efusesys@b0140000 {
|
||||
compatible = "sirf,prima2-efuse";
|
||||
reg = <0xb0140000 0x10000>;
|
||||
};
|
||||
|
||||
pulsec@b0150000 {
|
||||
compatible = "sirf,prima2-pulsec";
|
||||
reg = <0xb0150000 0x10000>;
|
||||
interrupts = <48>;
|
||||
};
|
||||
|
||||
pci-iobg {
|
||||
compatible = "sirf,prima2-pciiobg", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x56000000 0x56000000 0x1b00000>;
|
||||
|
||||
sd0: sdhci@56000000 {
|
||||
cell-index = <0>;
|
||||
compatible = "sirf,prima2-sdhc";
|
||||
reg = <0x56000000 0x100000>;
|
||||
interrupts = <38>;
|
||||
};
|
||||
|
||||
sd1: sdhci@56100000 {
|
||||
cell-index = <1>;
|
||||
compatible = "sirf,prima2-sdhc";
|
||||
reg = <0x56100000 0x100000>;
|
||||
interrupts = <38>;
|
||||
};
|
||||
|
||||
sd2: sdhci@56200000 {
|
||||
cell-index = <2>;
|
||||
compatible = "sirf,prima2-sdhc";
|
||||
reg = <0x56200000 0x100000>;
|
||||
interrupts = <23>;
|
||||
};
|
||||
|
||||
sd3: sdhci@56300000 {
|
||||
cell-index = <3>;
|
||||
compatible = "sirf,prima2-sdhc";
|
||||
reg = <0x56300000 0x100000>;
|
||||
interrupts = <23>;
|
||||
};
|
||||
|
||||
sd4: sdhci@56400000 {
|
||||
cell-index = <4>;
|
||||
compatible = "sirf,prima2-sdhc";
|
||||
reg = <0x56400000 0x100000>;
|
||||
interrupts = <39>;
|
||||
};
|
||||
|
||||
sd5: sdhci@56500000 {
|
||||
cell-index = <5>;
|
||||
compatible = "sirf,prima2-sdhc";
|
||||
reg = <0x56500000 0x100000>;
|
||||
interrupts = <39>;
|
||||
};
|
||||
|
||||
pci-copy@57900000 {
|
||||
compatible = "sirf,prima2-pcicp";
|
||||
reg = <0x57900000 0x100000>;
|
||||
interrupts = <40>;
|
||||
};
|
||||
|
||||
rom-interface@57a00000 {
|
||||
compatible = "sirf,prima2-romif";
|
||||
reg = <0x57a00000 0x100000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
rtc-iobg {
|
||||
compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x80030000 0x10000>;
|
||||
|
||||
gpsrtc@1000 {
|
||||
compatible = "sirf,prima2-gpsrtc";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupts = <55 56 57>;
|
||||
};
|
||||
|
||||
sysrtc@2000 {
|
||||
compatible = "sirf,prima2-sysrtc";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupts = <52 53 54>;
|
||||
};
|
||||
|
||||
pwrc@3000 {
|
||||
compatible = "sirf,prima2-pwrc";
|
||||
reg = <0x3000 0x1000>;
|
||||
interrupts = <32>;
|
||||
};
|
||||
};
|
||||
|
||||
uus-iobg {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0xb8000000 0xb8000000 0x40000>;
|
||||
|
||||
usb0: usb@b00e0000 {
|
||||
compatible = "chipidea,ci13611a-prima2";
|
||||
reg = <0xb8000000 0x10000>;
|
||||
interrupts = <10>;
|
||||
};
|
||||
|
||||
usb1: usb@b00f0000 {
|
||||
compatible = "chipidea,ci13611a-prima2";
|
||||
reg = <0xb8010000 0x10000>;
|
||||
interrupts = <11>;
|
||||
};
|
||||
|
||||
sata@b00f0000 {
|
||||
compatible = "synopsys,dwc-ahsata";
|
||||
reg = <0xb8020000 0x10000>;
|
||||
interrupts = <37>;
|
||||
};
|
||||
|
||||
security@b00f0000 {
|
||||
compatible = "sirf,prima2-security";
|
||||
reg = <0xb8030000 0x10000>;
|
||||
interrupts = <42>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
37
arch/arm/boot/dts/prima2-evb.dts
Normal file
37
arch/arm/boot/dts/prima2-evb.dts
Normal file
@ -0,0 +1,37 @@
|
||||
/*
|
||||
* DTS file for CSR SiRFprimaII Evaluation Board
|
||||
*
|
||||
* Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
|
||||
*
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "prima2.dtsi"
|
||||
|
||||
/ {
|
||||
model = "CSR SiRFprimaII Evaluation Board";
|
||||
compatible = "sirf,prima2", "sirf,prima2-cb";
|
||||
|
||||
memory {
|
||||
reg = <0x00000000 0x20000000>;
|
||||
};
|
||||
|
||||
axi {
|
||||
peri-iobg {
|
||||
uart@b0060000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart1_pins_a>;
|
||||
};
|
||||
spi@b00d0000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi0_pins_a>;
|
||||
};
|
||||
spi@b0170000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi1_pins_a>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
640
arch/arm/boot/dts/prima2.dtsi
Normal file
640
arch/arm/boot/dts/prima2.dtsi
Normal file
@ -0,0 +1,640 @@
|
||||
/*
|
||||
* DTS file for CSR SiRFprimaII SoC
|
||||
*
|
||||
* Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
|
||||
*
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
|
||||
/include/ "skeleton.dtsi"
|
||||
/ {
|
||||
compatible = "sirf,prima2";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupt-parent = <&intc>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
reg = <0x0>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-size = <32768>;
|
||||
i-cache-size = <32768>;
|
||||
/* from bootloader */
|
||||
timebase-frequency = <0>;
|
||||
bus-frequency = <0>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
axi {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x40000000 0x40000000 0x80000000>;
|
||||
|
||||
l2-cache-controller@80040000 {
|
||||
compatible = "arm,pl310-cache", "sirf,prima2-pl310-cache";
|
||||
reg = <0x80040000 0x1000>;
|
||||
interrupts = <59>;
|
||||
arm,tag-latency = <1 1 1>;
|
||||
arm,data-latency = <1 1 1>;
|
||||
arm,filter-ranges = <0 0x40000000>;
|
||||
};
|
||||
|
||||
intc: interrupt-controller@80020000 {
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-controller;
|
||||
compatible = "sirf,prima2-intc";
|
||||
reg = <0x80020000 0x1000>;
|
||||
};
|
||||
|
||||
sys-iobg {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x88000000 0x88000000 0x40000>;
|
||||
|
||||
clock-controller@88000000 {
|
||||
compatible = "sirf,prima2-clkc";
|
||||
reg = <0x88000000 0x1000>;
|
||||
interrupts = <3>;
|
||||
};
|
||||
|
||||
reset-controller@88010000 {
|
||||
compatible = "sirf,prima2-rstc";
|
||||
reg = <0x88010000 0x1000>;
|
||||
};
|
||||
|
||||
rsc-controller@88020000 {
|
||||
compatible = "sirf,prima2-rsc";
|
||||
reg = <0x88020000 0x1000>;
|
||||
};
|
||||
};
|
||||
|
||||
mem-iobg {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x90000000 0x90000000 0x10000>;
|
||||
|
||||
memory-controller@90000000 {
|
||||
compatible = "sirf,prima2-memc";
|
||||
reg = <0x90000000 0x10000>;
|
||||
interrupts = <27>;
|
||||
};
|
||||
};
|
||||
|
||||
disp-iobg {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x90010000 0x90010000 0x30000>;
|
||||
|
||||
display@90010000 {
|
||||
compatible = "sirf,prima2-lcd";
|
||||
reg = <0x90010000 0x20000>;
|
||||
interrupts = <30>;
|
||||
};
|
||||
|
||||
vpp@90020000 {
|
||||
compatible = "sirf,prima2-vpp";
|
||||
reg = <0x90020000 0x10000>;
|
||||
interrupts = <31>;
|
||||
};
|
||||
};
|
||||
|
||||
graphics-iobg {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x98000000 0x98000000 0x8000000>;
|
||||
|
||||
graphics@98000000 {
|
||||
compatible = "powervr,sgx531";
|
||||
reg = <0x98000000 0x8000000>;
|
||||
interrupts = <6>;
|
||||
};
|
||||
};
|
||||
|
||||
multimedia-iobg {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0xa0000000 0xa0000000 0x8000000>;
|
||||
|
||||
multimedia@a0000000 {
|
||||
compatible = "sirf,prima2-video-codec";
|
||||
reg = <0xa0000000 0x8000000>;
|
||||
interrupts = <5>;
|
||||
};
|
||||
};
|
||||
|
||||
dsp-iobg {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0xa8000000 0xa8000000 0x2000000>;
|
||||
|
||||
dspif@a8000000 {
|
||||
compatible = "sirf,prima2-dspif";
|
||||
reg = <0xa8000000 0x10000>;
|
||||
interrupts = <9>;
|
||||
};
|
||||
|
||||
gps@a8010000 {
|
||||
compatible = "sirf,prima2-gps";
|
||||
reg = <0xa8010000 0x10000>;
|
||||
interrupts = <7>;
|
||||
};
|
||||
|
||||
dsp@a9000000 {
|
||||
compatible = "sirf,prima2-dsp";
|
||||
reg = <0xa9000000 0x1000000>;
|
||||
interrupts = <8>;
|
||||
};
|
||||
};
|
||||
|
||||
peri-iobg {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0xb0000000 0xb0000000 0x180000>;
|
||||
|
||||
timer@b0020000 {
|
||||
compatible = "sirf,prima2-tick";
|
||||
reg = <0xb0020000 0x1000>;
|
||||
interrupts = <0>;
|
||||
};
|
||||
|
||||
nand@b0030000 {
|
||||
compatible = "sirf,prima2-nand";
|
||||
reg = <0xb0030000 0x10000>;
|
||||
interrupts = <41>;
|
||||
};
|
||||
|
||||
audio@b0040000 {
|
||||
compatible = "sirf,prima2-audio";
|
||||
reg = <0xb0040000 0x10000>;
|
||||
interrupts = <35>;
|
||||
};
|
||||
|
||||
uart0: uart@b0050000 {
|
||||
cell-index = <0>;
|
||||
compatible = "sirf,prima2-uart";
|
||||
reg = <0xb0050000 0x10000>;
|
||||
interrupts = <17>;
|
||||
};
|
||||
|
||||
uart1: uart@b0060000 {
|
||||
cell-index = <1>;
|
||||
compatible = "sirf,prima2-uart";
|
||||
reg = <0xb0060000 0x10000>;
|
||||
interrupts = <18>;
|
||||
};
|
||||
|
||||
uart2: uart@b0070000 {
|
||||
cell-index = <2>;
|
||||
compatible = "sirf,prima2-uart";
|
||||
reg = <0xb0070000 0x10000>;
|
||||
interrupts = <19>;
|
||||
};
|
||||
|
||||
usp0: usp@b0080000 {
|
||||
cell-index = <0>;
|
||||
compatible = "sirf,prima2-usp";
|
||||
reg = <0xb0080000 0x10000>;
|
||||
interrupts = <20>;
|
||||
};
|
||||
|
||||
usp1: usp@b0090000 {
|
||||
cell-index = <1>;
|
||||
compatible = "sirf,prima2-usp";
|
||||
reg = <0xb0090000 0x10000>;
|
||||
interrupts = <21>;
|
||||
};
|
||||
|
||||
usp2: usp@b00a0000 {
|
||||
cell-index = <2>;
|
||||
compatible = "sirf,prima2-usp";
|
||||
reg = <0xb00a0000 0x10000>;
|
||||
interrupts = <22>;
|
||||
};
|
||||
|
||||
dmac0: dma-controller@b00b0000 {
|
||||
cell-index = <0>;
|
||||
compatible = "sirf,prima2-dmac";
|
||||
reg = <0xb00b0000 0x10000>;
|
||||
interrupts = <12>;
|
||||
};
|
||||
|
||||
dmac1: dma-controller@b0160000 {
|
||||
cell-index = <1>;
|
||||
compatible = "sirf,prima2-dmac";
|
||||
reg = <0xb0160000 0x10000>;
|
||||
interrupts = <13>;
|
||||
};
|
||||
|
||||
vip@b00C0000 {
|
||||
compatible = "sirf,prima2-vip";
|
||||
reg = <0xb00C0000 0x10000>;
|
||||
};
|
||||
|
||||
spi0: spi@b00d0000 {
|
||||
cell-index = <0>;
|
||||
compatible = "sirf,prima2-spi";
|
||||
reg = <0xb00d0000 0x10000>;
|
||||
interrupts = <15>;
|
||||
};
|
||||
|
||||
spi1: spi@b0170000 {
|
||||
cell-index = <1>;
|
||||
compatible = "sirf,prima2-spi";
|
||||
reg = <0xb0170000 0x10000>;
|
||||
interrupts = <16>;
|
||||
};
|
||||
|
||||
i2c0: i2c@b00e0000 {
|
||||
cell-index = <0>;
|
||||
compatible = "sirf,prima2-i2c";
|
||||
reg = <0xb00e0000 0x10000>;
|
||||
interrupts = <24>;
|
||||
};
|
||||
|
||||
i2c1: i2c@b00f0000 {
|
||||
cell-index = <1>;
|
||||
compatible = "sirf,prima2-i2c";
|
||||
reg = <0xb00f0000 0x10000>;
|
||||
interrupts = <25>;
|
||||
};
|
||||
|
||||
tsc@b0110000 {
|
||||
compatible = "sirf,prima2-tsc";
|
||||
reg = <0xb0110000 0x10000>;
|
||||
interrupts = <33>;
|
||||
};
|
||||
|
||||
gpio: pinctrl@b0120000 {
|
||||
#gpio-cells = <2>;
|
||||
#interrupt-cells = <2>;
|
||||
compatible = "sirf,prima2-pinctrl";
|
||||
reg = <0xb0120000 0x10000>;
|
||||
interrupts = <43 44 45 46 47>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
|
||||
lcd_16pins_a: lcd0@0 {
|
||||
lcd {
|
||||
sirf,pins = "lcd_16bitsgrp";
|
||||
sirf,function = "lcd_16bits";
|
||||
};
|
||||
};
|
||||
lcd_18pins_a: lcd0@1 {
|
||||
lcd {
|
||||
sirf,pins = "lcd_18bitsgrp";
|
||||
sirf,function = "lcd_18bits";
|
||||
};
|
||||
};
|
||||
lcd_24pins_a: lcd0@2 {
|
||||
lcd {
|
||||
sirf,pins = "lcd_24bitsgrp";
|
||||
sirf,function = "lcd_24bits";
|
||||
};
|
||||
};
|
||||
lcdrom_pins_a: lcdrom0@0 {
|
||||
lcd {
|
||||
sirf,pins = "lcdromgrp";
|
||||
sirf,function = "lcdrom";
|
||||
};
|
||||
};
|
||||
uart0_pins_a: uart0@0 {
|
||||
uart {
|
||||
sirf,pins = "uart0grp";
|
||||
sirf,function = "uart0";
|
||||
};
|
||||
};
|
||||
uart1_pins_a: uart1@0 {
|
||||
uart {
|
||||
sirf,pins = "uart1grp";
|
||||
sirf,function = "uart1";
|
||||
};
|
||||
};
|
||||
uart2_pins_a: uart2@0 {
|
||||
uart {
|
||||
sirf,pins = "uart2grp";
|
||||
sirf,function = "uart2";
|
||||
};
|
||||
};
|
||||
uart2_noflow_pins_a: uart2@1 {
|
||||
uart {
|
||||
sirf,pins = "uart2_nostreamctrlgrp";
|
||||
sirf,function = "uart2_nostreamctrl";
|
||||
};
|
||||
};
|
||||
spi0_pins_a: spi0@0 {
|
||||
spi {
|
||||
sirf,pins = "spi0grp";
|
||||
sirf,function = "spi0";
|
||||
};
|
||||
};
|
||||
spi1_pins_a: spi1@0 {
|
||||
spi {
|
||||
sirf,pins = "spi1grp";
|
||||
sirf,function = "spi1";
|
||||
};
|
||||
};
|
||||
i2c0_pins_a: i2c0@0 {
|
||||
i2c {
|
||||
sirf,pins = "i2c0grp";
|
||||
sirf,function = "i2c0";
|
||||
};
|
||||
};
|
||||
i2c1_pins_a: i2c1@0 {
|
||||
i2c {
|
||||
sirf,pins = "i2c1grp";
|
||||
sirf,function = "i2c1";
|
||||
};
|
||||
};
|
||||
pwm0_pins_a: pwm0@0 {
|
||||
pwm {
|
||||
sirf,pins = "pwm0grp";
|
||||
sirf,function = "pwm0";
|
||||
};
|
||||
};
|
||||
pwm1_pins_a: pwm1@0 {
|
||||
pwm {
|
||||
sirf,pins = "pwm1grp";
|
||||
sirf,function = "pwm1";
|
||||
};
|
||||
};
|
||||
pwm2_pins_a: pwm2@0 {
|
||||
pwm {
|
||||
sirf,pins = "pwm2grp";
|
||||
sirf,function = "pwm2";
|
||||
};
|
||||
};
|
||||
pwm3_pins_a: pwm3@0 {
|
||||
pwm {
|
||||
sirf,pins = "pwm3grp";
|
||||
sirf,function = "pwm3";
|
||||
};
|
||||
};
|
||||
gps_pins_a: gps@0 {
|
||||
gps {
|
||||
sirf,pins = "gpsgrp";
|
||||
sirf,function = "gps";
|
||||
};
|
||||
};
|
||||
vip_pins_a: vip@0 {
|
||||
vip {
|
||||
sirf,pins = "vipgrp";
|
||||
sirf,function = "vip";
|
||||
};
|
||||
};
|
||||
sdmmc0_pins_a: sdmmc0@0 {
|
||||
sdmmc0 {
|
||||
sirf,pins = "sdmmc0grp";
|
||||
sirf,function = "sdmmc0";
|
||||
};
|
||||
};
|
||||
sdmmc1_pins_a: sdmmc1@0 {
|
||||
sdmmc1 {
|
||||
sirf,pins = "sdmmc1grp";
|
||||
sirf,function = "sdmmc1";
|
||||
};
|
||||
};
|
||||
sdmmc2_pins_a: sdmmc2@0 {
|
||||
sdmmc2 {
|
||||
sirf,pins = "sdmmc2grp";
|
||||
sirf,function = "sdmmc2";
|
||||
};
|
||||
};
|
||||
sdmmc3_pins_a: sdmmc3@0 {
|
||||
sdmmc3 {
|
||||
sirf,pins = "sdmmc3grp";
|
||||
sirf,function = "sdmmc3";
|
||||
};
|
||||
};
|
||||
sdmmc4_pins_a: sdmmc4@0 {
|
||||
sdmmc4 {
|
||||
sirf,pins = "sdmmc4grp";
|
||||
sirf,function = "sdmmc4";
|
||||
};
|
||||
};
|
||||
sdmmc5_pins_a: sdmmc5@0 {
|
||||
sdmmc5 {
|
||||
sirf,pins = "sdmmc5grp";
|
||||
sirf,function = "sdmmc5";
|
||||
};
|
||||
};
|
||||
i2s_pins_a: i2s@0 {
|
||||
i2s {
|
||||
sirf,pins = "i2sgrp";
|
||||
sirf,function = "i2s";
|
||||
};
|
||||
};
|
||||
ac97_pins_a: ac97@0 {
|
||||
ac97 {
|
||||
sirf,pins = "ac97grp";
|
||||
sirf,function = "ac97";
|
||||
};
|
||||
};
|
||||
nand_pins_a: nand@0 {
|
||||
nand {
|
||||
sirf,pins = "nandgrp";
|
||||
sirf,function = "nand";
|
||||
};
|
||||
};
|
||||
usp0_pins_a: usp0@0 {
|
||||
usp0 {
|
||||
sirf,pins = "usp0grp";
|
||||
sirf,function = "usp0";
|
||||
};
|
||||
};
|
||||
usp1_pins_a: usp1@0 {
|
||||
usp1 {
|
||||
sirf,pins = "usp1grp";
|
||||
sirf,function = "usp1";
|
||||
};
|
||||
};
|
||||
usp2_pins_a: usp2@0 {
|
||||
usp2 {
|
||||
sirf,pins = "usp2grp";
|
||||
sirf,function = "usp2";
|
||||
};
|
||||
};
|
||||
usb0_utmi_drvbus_pins_a: usb0_utmi_drvbus@0 {
|
||||
usb0_utmi_drvbus {
|
||||
sirf,pins = "usb0_utmi_drvbusgrp";
|
||||
sirf,function = "usb0_utmi_drvbus";
|
||||
};
|
||||
};
|
||||
usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus@0 {
|
||||
usb1_utmi_drvbus {
|
||||
sirf,pins = "usb1_utmi_drvbusgrp";
|
||||
sirf,function = "usb1_utmi_drvbus";
|
||||
};
|
||||
};
|
||||
warm_rst_pins_a: warm_rst@0 {
|
||||
warm_rst {
|
||||
sirf,pins = "warm_rstgrp";
|
||||
sirf,function = "warm_rst";
|
||||
};
|
||||
};
|
||||
pulse_count_pins_a: pulse_count@0 {
|
||||
pulse_count {
|
||||
sirf,pins = "pulse_countgrp";
|
||||
sirf,function = "pulse_count";
|
||||
};
|
||||
};
|
||||
cko0_rst_pins_a: cko0_rst@0 {
|
||||
cko0_rst {
|
||||
sirf,pins = "cko0_rstgrp";
|
||||
sirf,function = "cko0_rst";
|
||||
};
|
||||
};
|
||||
cko1_rst_pins_a: cko1_rst@0 {
|
||||
cko1_rst {
|
||||
sirf,pins = "cko1_rstgrp";
|
||||
sirf,function = "cko1_rst";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pwm@b0130000 {
|
||||
compatible = "sirf,prima2-pwm";
|
||||
reg = <0xb0130000 0x10000>;
|
||||
};
|
||||
|
||||
efusesys@b0140000 {
|
||||
compatible = "sirf,prima2-efuse";
|
||||
reg = <0xb0140000 0x10000>;
|
||||
};
|
||||
|
||||
pulsec@b0150000 {
|
||||
compatible = "sirf,prima2-pulsec";
|
||||
reg = <0xb0150000 0x10000>;
|
||||
interrupts = <48>;
|
||||
};
|
||||
|
||||
pci-iobg {
|
||||
compatible = "sirf,prima2-pciiobg", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x56000000 0x56000000 0x1b00000>;
|
||||
|
||||
sd0: sdhci@56000000 {
|
||||
cell-index = <0>;
|
||||
compatible = "sirf,prima2-sdhc";
|
||||
reg = <0x56000000 0x100000>;
|
||||
interrupts = <38>;
|
||||
};
|
||||
|
||||
sd1: sdhci@56100000 {
|
||||
cell-index = <1>;
|
||||
compatible = "sirf,prima2-sdhc";
|
||||
reg = <0x56100000 0x100000>;
|
||||
interrupts = <38>;
|
||||
};
|
||||
|
||||
sd2: sdhci@56200000 {
|
||||
cell-index = <2>;
|
||||
compatible = "sirf,prima2-sdhc";
|
||||
reg = <0x56200000 0x100000>;
|
||||
interrupts = <23>;
|
||||
};
|
||||
|
||||
sd3: sdhci@56300000 {
|
||||
cell-index = <3>;
|
||||
compatible = "sirf,prima2-sdhc";
|
||||
reg = <0x56300000 0x100000>;
|
||||
interrupts = <23>;
|
||||
};
|
||||
|
||||
sd4: sdhci@56400000 {
|
||||
cell-index = <4>;
|
||||
compatible = "sirf,prima2-sdhc";
|
||||
reg = <0x56400000 0x100000>;
|
||||
interrupts = <39>;
|
||||
};
|
||||
|
||||
sd5: sdhci@56500000 {
|
||||
cell-index = <5>;
|
||||
compatible = "sirf,prima2-sdhc";
|
||||
reg = <0x56500000 0x100000>;
|
||||
interrupts = <39>;
|
||||
};
|
||||
|
||||
pci-copy@57900000 {
|
||||
compatible = "sirf,prima2-pcicp";
|
||||
reg = <0x57900000 0x100000>;
|
||||
interrupts = <40>;
|
||||
};
|
||||
|
||||
rom-interface@57a00000 {
|
||||
compatible = "sirf,prima2-romif";
|
||||
reg = <0x57a00000 0x100000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
rtc-iobg {
|
||||
compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x80030000 0x10000>;
|
||||
|
||||
gpsrtc@1000 {
|
||||
compatible = "sirf,prima2-gpsrtc";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupts = <55 56 57>;
|
||||
};
|
||||
|
||||
sysrtc@2000 {
|
||||
compatible = "sirf,prima2-sysrtc";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupts = <52 53 54>;
|
||||
};
|
||||
|
||||
pwrc@3000 {
|
||||
compatible = "sirf,prima2-pwrc";
|
||||
reg = <0x3000 0x1000>;
|
||||
interrupts = <32>;
|
||||
};
|
||||
};
|
||||
|
||||
uus-iobg {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0xb8000000 0xb8000000 0x40000>;
|
||||
|
||||
usb0: usb@b00e0000 {
|
||||
compatible = "chipidea,ci13611a-prima2";
|
||||
reg = <0xb8000000 0x10000>;
|
||||
interrupts = <10>;
|
||||
};
|
||||
|
||||
usb1: usb@b00f0000 {
|
||||
compatible = "chipidea,ci13611a-prima2";
|
||||
reg = <0xb8010000 0x10000>;
|
||||
interrupts = <11>;
|
||||
};
|
||||
|
||||
sata@b00f0000 {
|
||||
compatible = "synopsys,dwc-ahsata";
|
||||
reg = <0xb8020000 0x10000>;
|
||||
interrupts = <37>;
|
||||
};
|
||||
|
||||
security@b00f0000 {
|
||||
compatible = "sirf,prima2-security";
|
||||
reg = <0xb8030000 0x10000>;
|
||||
interrupts = <42>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
14
arch/arm/boot/dts/pxa27x.dtsi
Normal file
14
arch/arm/boot/dts/pxa27x.dtsi
Normal file
@ -0,0 +1,14 @@
|
||||
/* The pxa3xx skeleton simply augments the 2xx version */
|
||||
/include/ "pxa2xx.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell PXA27x familiy SoC";
|
||||
compatible = "marvell,pxa27x";
|
||||
|
||||
pxabus {
|
||||
pxairq: interrupt-controller@40d00000 {
|
||||
marvell,intc-priority;
|
||||
marvell,intc-nr-irqs = <34>;
|
||||
};
|
||||
};
|
||||
};
|
||||
132
arch/arm/boot/dts/pxa2xx.dtsi
Normal file
132
arch/arm/boot/dts/pxa2xx.dtsi
Normal file
@ -0,0 +1,132 @@
|
||||
/*
|
||||
* pxa2xx.dtsi - Device Tree Include file for Marvell PXA2xx family SoC
|
||||
*
|
||||
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
|
||||
*
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
|
||||
/include/ "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell PXA2xx family SoC";
|
||||
compatible = "marvell,pxa2xx";
|
||||
interrupt-parent = <&pxairq>;
|
||||
|
||||
aliases {
|
||||
serial0 = &ffuart;
|
||||
serial1 = &btuart;
|
||||
serial2 = &stuart;
|
||||
serial3 = &hwuart;
|
||||
i2c0 = &pwri2c;
|
||||
i2c1 = &pxai2c1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
cpu@0 {
|
||||
compatible = "arm,xscale";
|
||||
};
|
||||
};
|
||||
|
||||
pxabus {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
pxairq: interrupt-controller@40d00000 {
|
||||
#interrupt-cells = <1>;
|
||||
compatible = "marvell,pxa-intc";
|
||||
interrupt-controller;
|
||||
interrupt-parent;
|
||||
marvell,intc-nr-irqs = <32>;
|
||||
reg = <0x40d00000 0xd0>;
|
||||
};
|
||||
|
||||
gpio: gpio@40e00000 {
|
||||
compatible = "mrvl,pxa-gpio";
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x1>;
|
||||
reg = <0x40e00000 0x10000>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <0x2>;
|
||||
interrupts = <10>;
|
||||
interrupt-names = "gpio_mux";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <0x2>;
|
||||
ranges;
|
||||
|
||||
gcb0: gpio@40e00000 {
|
||||
reg = <0x40e00000 0x4>;
|
||||
};
|
||||
|
||||
gcb1: gpio@40e00004 {
|
||||
reg = <0x40e00004 0x4>;
|
||||
};
|
||||
|
||||
gcb2: gpio@40e00008 {
|
||||
reg = <0x40e00008 0x4>;
|
||||
};
|
||||
gcb3: gpio@40e0000c {
|
||||
reg = <0x40e0000c 0x4>;
|
||||
};
|
||||
};
|
||||
|
||||
ffuart: uart@40100000 {
|
||||
compatible = "mrvl,pxa-uart";
|
||||
reg = <0x40100000 0x30>;
|
||||
interrupts = <22>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
btuart: uart@40200000 {
|
||||
compatible = "mrvl,pxa-uart";
|
||||
reg = <0x40200000 0x30>;
|
||||
interrupts = <21>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
stuart: uart@40700000 {
|
||||
compatible = "mrvl,pxa-uart";
|
||||
reg = <0x40700000 0x30>;
|
||||
interrupts = <20>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
hwuart: uart@41100000 {
|
||||
compatible = "mrvl,pxa-uart";
|
||||
reg = <0x41100000 0x30>;
|
||||
interrupts = <7>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pxai2c1: i2c@40301680 {
|
||||
compatible = "mrvl,pxa-i2c";
|
||||
reg = <0x40301680 0x30>;
|
||||
interrupts = <18>;
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb0: ohci@4c000000 {
|
||||
compatible = "mrvl,pxa-ohci";
|
||||
reg = <0x4c000000 0x10000>;
|
||||
interrupts = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mmc0: mmc@41100000 {
|
||||
compatible = "mrvl,pxa-mmc";
|
||||
reg = <0x41100000 0x1000>;
|
||||
interrupts = <23>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
rtc@40900000 {
|
||||
compatible = "marvell,pxa-rtc";
|
||||
reg = <0x40900000 0x3c>;
|
||||
interrupts = <30 31>;
|
||||
};
|
||||
};
|
||||
};
|
||||
32
arch/arm/boot/dts/pxa3xx.dtsi
Normal file
32
arch/arm/boot/dts/pxa3xx.dtsi
Normal file
@ -0,0 +1,32 @@
|
||||
/* The pxa3xx skeleton simply augments the 2xx version */
|
||||
/include/ "pxa2xx.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell PXA3xx familiy SoC";
|
||||
compatible = "marvell,pxa3xx";
|
||||
|
||||
pxabus {
|
||||
pwri2c: i2c@40f500c0 {
|
||||
compatible = "mrvl,pwri2c";
|
||||
reg = <0x40f500c0 0x30>;
|
||||
interrupts = <6>;
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
nand0: nand@43100000 {
|
||||
compatible = "marvell,pxa3xx-nand";
|
||||
reg = <0x43100000 90>;
|
||||
interrupts = <45>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pxairq: interrupt-controller@40d00000 {
|
||||
marvell,intc-priority;
|
||||
marvell,intc-nr-irqs = <56>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -25,6 +25,11 @@
|
||||
interrupt-parent = <&intc>;
|
||||
ranges;
|
||||
|
||||
L2: l2-cache {
|
||||
compatible = "marvell,tauros2-cache";
|
||||
marvell,tauros2-cache-features = <0x3>;
|
||||
};
|
||||
|
||||
axi@d4200000 { /* AXI */
|
||||
compatible = "mrvl,axi-bus", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
|
||||
58
arch/arm/boot/dts/tegra20-medcom-wide.dts
Normal file
58
arch/arm/boot/dts/tegra20-medcom-wide.dts
Normal file
@ -0,0 +1,58 @@
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "tegra20-tamonten.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Avionic Design Medcom-Wide board";
|
||||
compatible = "ad,medcom-wide", "ad,tamonten", "nvidia,tegra20";
|
||||
|
||||
i2c@7000c000 {
|
||||
wm8903: wm8903@1a {
|
||||
compatible = "wlf,wm8903";
|
||||
reg = <0x1a>;
|
||||
interrupt-parent = <&gpio>;
|
||||
interrupts = <187 0x04>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
micdet-cfg = <0>;
|
||||
micdet-delay = <100>;
|
||||
gpio-cfg = <0xffffffff
|
||||
0xffffffff
|
||||
0
|
||||
0xffffffff
|
||||
0xffffffff>;
|
||||
};
|
||||
};
|
||||
|
||||
backlight {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&pwm 0 5000000>;
|
||||
|
||||
brightness-levels = <0 4 8 16 32 64 128 255>;
|
||||
default-brightness-level = <6>;
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "ad,tegra-audio-wm8903-medcom-wide",
|
||||
"nvidia,tegra-audio-wm8903";
|
||||
nvidia,model = "Avionic Design Medcom-Wide";
|
||||
|
||||
nvidia,audio-routing =
|
||||
"Headphone Jack", "HPOUTR",
|
||||
"Headphone Jack", "HPOUTL",
|
||||
"Int Spk", "ROP",
|
||||
"Int Spk", "RON",
|
||||
"Int Spk", "LOP",
|
||||
"Int Spk", "LON",
|
||||
"Mic Jack", "MICBIAS",
|
||||
"IN1L", "Mic Jack";
|
||||
|
||||
nvidia,i2s-controller = <&tegra_i2s1>;
|
||||
nvidia,audio-codec = <&wm8903>;
|
||||
|
||||
nvidia,spkr-en-gpios = <&wm8903 2 0>;
|
||||
nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
|
||||
};
|
||||
};
|
||||
@ -272,12 +272,170 @@
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
pmic: tps6586x@34 {
|
||||
compatible = "ti,tps6586x";
|
||||
reg = <0x34>;
|
||||
interrupts = <0 86 0x4>;
|
||||
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
|
||||
sys-supply = <&p5valw_reg>;
|
||||
vin-sm0-supply = <&sys_reg>;
|
||||
vin-sm1-supply = <&sys_reg>;
|
||||
vin-sm2-supply = <&sys_reg>;
|
||||
vinldo01-supply = <&sm2_reg>;
|
||||
vinldo23-supply = <&sm2_reg>;
|
||||
vinldo4-supply = <&sm2_reg>;
|
||||
vinldo678-supply = <&sm2_reg>;
|
||||
vinldo9-supply = <&sm2_reg>;
|
||||
|
||||
regulators {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
sys_reg: regulator@0 {
|
||||
reg = <0>;
|
||||
regulator-compatible = "sys";
|
||||
regulator-name = "vdd_sys";
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@1 {
|
||||
reg = <1>;
|
||||
regulator-compatible = "sm0";
|
||||
regulator-name = "+1.2vs_sm0,vdd_core";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@2 {
|
||||
reg = <2>;
|
||||
regulator-compatible = "sm1";
|
||||
regulator-name = "+1.0vs_sm1,vdd_cpu";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
sm2_reg: regulator@3 {
|
||||
reg = <3>;
|
||||
regulator-compatible = "sm2";
|
||||
regulator-name = "+3.7vs_sm2,vin_ldo*";
|
||||
regulator-min-microvolt = <3700000>;
|
||||
regulator-max-microvolt = <3700000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
/* LDO0 is not connected to anything */
|
||||
|
||||
regulator@5 {
|
||||
reg = <5>;
|
||||
regulator-compatible = "ldo1";
|
||||
regulator-name = "+1.1vs_ldo1,avdd_pll*";
|
||||
regulator-min-microvolt = <1100000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@6 {
|
||||
reg = <6>;
|
||||
regulator-compatible = "ldo2";
|
||||
regulator-name = "+1.2vs_ldo2,vdd_rtc";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
};
|
||||
|
||||
regulator@7 {
|
||||
reg = <7>;
|
||||
regulator-compatible = "ldo3";
|
||||
regulator-name = "+3.3vs_ldo3,avdd_usb*";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@8 {
|
||||
reg = <8>;
|
||||
regulator-compatible = "ldo4";
|
||||
regulator-name = "+1.8vs_ldo4,avdd_osc,vddio_sys";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@9 {
|
||||
reg = <9>;
|
||||
regulator-compatible = "ldo5";
|
||||
regulator-name = "+2.85vs_ldo5,vcore_mmc";
|
||||
regulator-min-microvolt = <2850000>;
|
||||
regulator-max-microvolt = <2850000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@10 {
|
||||
reg = <10>;
|
||||
regulator-compatible = "ldo6";
|
||||
/*
|
||||
* Research indicates this should be
|
||||
* 1.8v; other boards that use this
|
||||
* rail for the same purpose need it
|
||||
* set to 1.8v. The schematic signal
|
||||
* name is incorrect; perhaps copied
|
||||
* from an incorrect NVIDIA reference.
|
||||
*/
|
||||
regulator-name = "+2.85vs_ldo6,avdd_vdac";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
regulator@11 {
|
||||
reg = <11>;
|
||||
regulator-compatible = "ldo7";
|
||||
regulator-name = "+3.3vs_ldo7,avdd_hdmi";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
regulator@12 {
|
||||
reg = <12>;
|
||||
regulator-compatible = "ldo8";
|
||||
regulator-name = "+1.8vs_ldo8,avdd_hdmi_pll";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
regulator@13 {
|
||||
reg = <13>;
|
||||
regulator-compatible = "ldo9";
|
||||
regulator-name = "+2.85vs_ldo9,vdd_ddr_rx";
|
||||
regulator-min-microvolt = <2850000>;
|
||||
regulator-max-microvolt = <2850000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@14 {
|
||||
reg = <14>;
|
||||
regulator-compatible = "ldo_rtc";
|
||||
regulator-name = "+3.3vs_rtc";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
adt7461@4c {
|
||||
compatible = "adi,adt7461";
|
||||
reg = <0x4c>;
|
||||
};
|
||||
};
|
||||
|
||||
pmc {
|
||||
nvidia,invert-interrupt;
|
||||
};
|
||||
|
||||
usb@c5000000 {
|
||||
status = "okay";
|
||||
};
|
||||
@ -325,6 +483,21 @@
|
||||
};
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
p5valw_reg: regulator@0 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <0>;
|
||||
regulator-name = "+5valw";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "nvidia,tegra-audio-alc5632-paz00",
|
||||
"nvidia,tegra-audio-alc5632";
|
||||
|
||||
50
arch/arm/boot/dts/tegra20-plutux.dts
Normal file
50
arch/arm/boot/dts/tegra20-plutux.dts
Normal file
@ -0,0 +1,50 @@
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "tegra20-tamonten.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Avionic Design Plutux board";
|
||||
compatible = "ad,plutux", "ad,tamonten", "nvidia,tegra20";
|
||||
|
||||
i2c@7000c000 {
|
||||
wm8903: wm8903@1a {
|
||||
compatible = "wlf,wm8903";
|
||||
reg = <0x1a>;
|
||||
interrupt-parent = <&gpio>;
|
||||
interrupts = <187 0x04>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
micdet-cfg = <0>;
|
||||
micdet-delay = <100>;
|
||||
gpio-cfg = <0xffffffff
|
||||
0xffffffff
|
||||
0
|
||||
0xffffffff
|
||||
0xffffffff>;
|
||||
};
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "ad,tegra-audio-plutux",
|
||||
"nvidia,tegra-audio-wm8903";
|
||||
nvidia,model = "Avionic Design Plutux";
|
||||
|
||||
nvidia,audio-routing =
|
||||
"Headphone Jack", "HPOUTR",
|
||||
"Headphone Jack", "HPOUTL",
|
||||
"Int Spk", "ROP",
|
||||
"Int Spk", "RON",
|
||||
"Int Spk", "LOP",
|
||||
"Int Spk", "LON",
|
||||
"Mic Jack", "MICBIAS",
|
||||
"IN1L", "Mic Jack";
|
||||
|
||||
nvidia,i2s-controller = <&tegra_i2s1>;
|
||||
nvidia,audio-codec = <&wm8903>;
|
||||
|
||||
nvidia,spkr-en-gpios = <&wm8903 2 0>;
|
||||
nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
|
||||
};
|
||||
};
|
||||
@ -374,6 +374,154 @@
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
pmic: tps6586x@34 {
|
||||
compatible = "ti,tps6586x";
|
||||
reg = <0x34>;
|
||||
interrupts = <0 86 0x4>;
|
||||
|
||||
ti,system-power-controller;
|
||||
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
|
||||
sys-supply = <&vdd_5v0_reg>;
|
||||
vin-sm0-supply = <&sys_reg>;
|
||||
vin-sm1-supply = <&sys_reg>;
|
||||
vin-sm2-supply = <&sys_reg>;
|
||||
vinldo01-supply = <&sm2_reg>;
|
||||
vinldo23-supply = <&sm2_reg>;
|
||||
vinldo4-supply = <&sm2_reg>;
|
||||
vinldo678-supply = <&sm2_reg>;
|
||||
vinldo9-supply = <&sm2_reg>;
|
||||
|
||||
regulators {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
sys_reg: regulator@0 {
|
||||
reg = <0>;
|
||||
regulator-compatible = "sys";
|
||||
regulator-name = "vdd_sys";
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@1 {
|
||||
reg = <1>;
|
||||
regulator-compatible = "sm0";
|
||||
regulator-name = "vdd_sm0,vdd_core";
|
||||
regulator-min-microvolt = <1300000>;
|
||||
regulator-max-microvolt = <1300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@2 {
|
||||
reg = <2>;
|
||||
regulator-compatible = "sm1";
|
||||
regulator-name = "vdd_sm1,vdd_cpu";
|
||||
regulator-min-microvolt = <1125000>;
|
||||
regulator-max-microvolt = <1125000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
sm2_reg: regulator@3 {
|
||||
reg = <3>;
|
||||
regulator-compatible = "sm2";
|
||||
regulator-name = "vdd_sm2,vin_ldo*";
|
||||
regulator-min-microvolt = <3700000>;
|
||||
regulator-max-microvolt = <3700000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
/* LDO0 is not connected to anything */
|
||||
|
||||
regulator@5 {
|
||||
reg = <5>;
|
||||
regulator-compatible = "ldo1";
|
||||
regulator-name = "vdd_ldo1,avdd_pll*";
|
||||
regulator-min-microvolt = <1100000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@6 {
|
||||
reg = <6>;
|
||||
regulator-compatible = "ldo2";
|
||||
regulator-name = "vdd_ldo2,vdd_rtc";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
};
|
||||
|
||||
regulator@7 {
|
||||
reg = <7>;
|
||||
regulator-compatible = "ldo3";
|
||||
regulator-name = "vdd_ldo3,avdd_usb*";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@8 {
|
||||
reg = <8>;
|
||||
regulator-compatible = "ldo4";
|
||||
regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@9 {
|
||||
reg = <9>;
|
||||
regulator-compatible = "ldo5";
|
||||
regulator-name = "vdd_ldo5,vcore_mmc";
|
||||
regulator-min-microvolt = <2850000>;
|
||||
regulator-max-microvolt = <2850000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@10 {
|
||||
reg = <10>;
|
||||
regulator-compatible = "ldo6";
|
||||
regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
regulator@11 {
|
||||
reg = <11>;
|
||||
regulator-compatible = "ldo7";
|
||||
regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
regulator@12 {
|
||||
reg = <12>;
|
||||
regulator-compatible = "ldo8";
|
||||
regulator-name = "vdd_ldo8,avdd_hdmi_pll";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
regulator@13 {
|
||||
reg = <13>;
|
||||
regulator-compatible = "ldo9";
|
||||
regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
|
||||
regulator-min-microvolt = <2850000>;
|
||||
regulator-max-microvolt = <2850000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@14 {
|
||||
reg = <14>;
|
||||
regulator-compatible = "ldo_rtc";
|
||||
regulator-name = "vdd_rtc_out,vdd_cell";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
temperature-sensor@4c {
|
||||
compatible = "nct1008";
|
||||
reg = <0x4c>;
|
||||
@ -387,6 +535,10 @@
|
||||
};
|
||||
};
|
||||
|
||||
pmc {
|
||||
nvidia,invert-interrupt;
|
||||
};
|
||||
|
||||
memory-controller@0x7000f400 {
|
||||
emc-table@190000 {
|
||||
reg = <190000>;
|
||||
@ -473,6 +625,40 @@
|
||||
};
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
vdd_5v0_reg: regulator@0 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <0>;
|
||||
regulator-name = "vdd_5v0";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@1 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <1>;
|
||||
regulator-name = "vdd_1v5";
|
||||
regulator-min-microvolt = <1500000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
gpio = <&pmic 0 0>;
|
||||
};
|
||||
|
||||
regulator@2 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <2>;
|
||||
regulator-name = "vdd_1v2";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
gpio = <&pmic 1 0>;
|
||||
enable-active-high;
|
||||
};
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "nvidia,tegra-audio-wm8903-seaboard",
|
||||
"nvidia,tegra-audio-wm8903";
|
||||
|
||||
449
arch/arm/boot/dts/tegra20-tamonten.dtsi
Normal file
449
arch/arm/boot/dts/tegra20-tamonten.dtsi
Normal file
@ -0,0 +1,449 @@
|
||||
/include/ "tegra20.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Avionic Design Tamonten SOM";
|
||||
compatible = "ad,tamonten", "nvidia,tegra20";
|
||||
|
||||
memory {
|
||||
reg = <0x00000000 0x20000000>;
|
||||
};
|
||||
|
||||
pinmux {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&state_default>;
|
||||
|
||||
state_default: pinmux {
|
||||
ata {
|
||||
nvidia,pins = "ata";
|
||||
nvidia,function = "ide";
|
||||
};
|
||||
atb {
|
||||
nvidia,pins = "atb", "gma", "gme";
|
||||
nvidia,function = "sdio4";
|
||||
};
|
||||
atc {
|
||||
nvidia,pins = "atc";
|
||||
nvidia,function = "nand";
|
||||
};
|
||||
atd {
|
||||
nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu",
|
||||
"spia", "spib", "spic";
|
||||
nvidia,function = "gmi";
|
||||
};
|
||||
cdev1 {
|
||||
nvidia,pins = "cdev1";
|
||||
nvidia,function = "plla_out";
|
||||
};
|
||||
cdev2 {
|
||||
nvidia,pins = "cdev2";
|
||||
nvidia,function = "pllp_out4";
|
||||
};
|
||||
crtp {
|
||||
nvidia,pins = "crtp";
|
||||
nvidia,function = "crt";
|
||||
};
|
||||
csus {
|
||||
nvidia,pins = "csus";
|
||||
nvidia,function = "vi_sensor_clk";
|
||||
};
|
||||
dap1 {
|
||||
nvidia,pins = "dap1";
|
||||
nvidia,function = "dap1";
|
||||
};
|
||||
dap2 {
|
||||
nvidia,pins = "dap2";
|
||||
nvidia,function = "dap2";
|
||||
};
|
||||
dap3 {
|
||||
nvidia,pins = "dap3";
|
||||
nvidia,function = "dap3";
|
||||
};
|
||||
dap4 {
|
||||
nvidia,pins = "dap4";
|
||||
nvidia,function = "dap4";
|
||||
};
|
||||
ddc {
|
||||
nvidia,pins = "ddc";
|
||||
nvidia,function = "i2c2";
|
||||
};
|
||||
dta {
|
||||
nvidia,pins = "dta", "dtd";
|
||||
nvidia,function = "sdio2";
|
||||
};
|
||||
dtb {
|
||||
nvidia,pins = "dtb", "dtc", "dte";
|
||||
nvidia,function = "rsvd1";
|
||||
};
|
||||
dtf {
|
||||
nvidia,pins = "dtf";
|
||||
nvidia,function = "i2c3";
|
||||
};
|
||||
gmc {
|
||||
nvidia,pins = "gmc";
|
||||
nvidia,function = "uartd";
|
||||
};
|
||||
gpu7 {
|
||||
nvidia,pins = "gpu7";
|
||||
nvidia,function = "rtck";
|
||||
};
|
||||
gpv {
|
||||
nvidia,pins = "gpv", "slxa", "slxk";
|
||||
nvidia,function = "pcie";
|
||||
};
|
||||
hdint {
|
||||
nvidia,pins = "hdint", "pta";
|
||||
nvidia,function = "hdmi";
|
||||
};
|
||||
i2cp {
|
||||
nvidia,pins = "i2cp";
|
||||
nvidia,function = "i2cp";
|
||||
};
|
||||
irrx {
|
||||
nvidia,pins = "irrx", "irtx";
|
||||
nvidia,function = "uarta";
|
||||
};
|
||||
kbca {
|
||||
nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
|
||||
"kbce", "kbcf";
|
||||
nvidia,function = "kbc";
|
||||
};
|
||||
lcsn {
|
||||
nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
|
||||
"ld3", "ld4", "ld5", "ld6", "ld7",
|
||||
"ld8", "ld9", "ld10", "ld11", "ld12",
|
||||
"ld13", "ld14", "ld15", "ld16", "ld17",
|
||||
"ldc", "ldi", "lhp0", "lhp1", "lhp2",
|
||||
"lhs", "lm0", "lm1", "lpp", "lpw0",
|
||||
"lpw1", "lpw2", "lsc0", "lsc1", "lsck",
|
||||
"lsda", "lsdi", "lspi", "lvp0", "lvp1",
|
||||
"lvs";
|
||||
nvidia,function = "displaya";
|
||||
};
|
||||
owc {
|
||||
nvidia,pins = "owc", "spdi", "spdo", "uac";
|
||||
nvidia,function = "rsvd2";
|
||||
};
|
||||
pmc {
|
||||
nvidia,pins = "pmc";
|
||||
nvidia,function = "pwr_on";
|
||||
};
|
||||
rm {
|
||||
nvidia,pins = "rm";
|
||||
nvidia,function = "i2c1";
|
||||
};
|
||||
sdb {
|
||||
nvidia,pins = "sdb", "sdc", "sdd";
|
||||
nvidia,function = "pwm";
|
||||
};
|
||||
sdio1 {
|
||||
nvidia,pins = "sdio1";
|
||||
nvidia,function = "sdio1";
|
||||
};
|
||||
slxc {
|
||||
nvidia,pins = "slxc", "slxd";
|
||||
nvidia,function = "spdif";
|
||||
};
|
||||
spid {
|
||||
nvidia,pins = "spid", "spie", "spif";
|
||||
nvidia,function = "spi1";
|
||||
};
|
||||
spig {
|
||||
nvidia,pins = "spig", "spih";
|
||||
nvidia,function = "spi2_alt";
|
||||
};
|
||||
uaa {
|
||||
nvidia,pins = "uaa", "uab", "uda";
|
||||
nvidia,function = "ulpi";
|
||||
};
|
||||
uad {
|
||||
nvidia,pins = "uad";
|
||||
nvidia,function = "irda";
|
||||
};
|
||||
uca {
|
||||
nvidia,pins = "uca", "ucb";
|
||||
nvidia,function = "uartc";
|
||||
};
|
||||
conf_ata {
|
||||
nvidia,pins = "ata", "atb", "atc", "atd", "ate",
|
||||
"cdev1", "cdev2", "dap1", "dtb", "gma",
|
||||
"gmb", "gmc", "gmd", "gme", "gpu7",
|
||||
"gpv", "i2cp", "pta", "rm", "slxa",
|
||||
"slxk", "spia", "spib", "uac";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
conf_ck32 {
|
||||
nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
|
||||
"pmcc", "pmcd", "pmce", "xm2c", "xm2d";
|
||||
nvidia,pull = <0>;
|
||||
};
|
||||
conf_csus {
|
||||
nvidia,pins = "csus", "spid", "spif";
|
||||
nvidia,pull = <1>;
|
||||
nvidia,tristate = <1>;
|
||||
};
|
||||
conf_crtp {
|
||||
nvidia,pins = "crtp", "dap2", "dap3", "dap4",
|
||||
"dtc", "dte", "dtf", "gpu", "sdio1",
|
||||
"slxc", "slxd", "spdi", "spdo", "spig",
|
||||
"uda";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <1>;
|
||||
};
|
||||
conf_ddc {
|
||||
nvidia,pins = "ddc", "dta", "dtd", "kbca",
|
||||
"kbcb", "kbcc", "kbcd", "kbce", "kbcf",
|
||||
"sdc";
|
||||
nvidia,pull = <2>;
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
conf_hdint {
|
||||
nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
|
||||
"lpw1", "lsc1", "lsck", "lsda", "lsdi",
|
||||
"lvp0", "owc", "sdb";
|
||||
nvidia,tristate = <1>;
|
||||
};
|
||||
conf_irrx {
|
||||
nvidia,pins = "irrx", "irtx", "sdd", "spic",
|
||||
"spie", "spih", "uaa", "uab", "uad",
|
||||
"uca", "ucb";
|
||||
nvidia,pull = <2>;
|
||||
nvidia,tristate = <1>;
|
||||
};
|
||||
conf_lc {
|
||||
nvidia,pins = "lc", "ls";
|
||||
nvidia,pull = <2>;
|
||||
};
|
||||
conf_ld0 {
|
||||
nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
|
||||
"ld5", "ld6", "ld7", "ld8", "ld9",
|
||||
"ld10", "ld11", "ld12", "ld13", "ld14",
|
||||
"ld15", "ld16", "ld17", "ldi", "lhp0",
|
||||
"lhp1", "lhp2", "lhs", "lm0", "lpp",
|
||||
"lpw0", "lpw2", "lsc0", "lspi", "lvp1",
|
||||
"lvs", "pmc";
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
conf_ld17_0 {
|
||||
nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
|
||||
"ld23_22";
|
||||
nvidia,pull = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
i2s@70002800 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
serial@70006300 {
|
||||
clock-frequency = <216000000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2c@7000c000 {
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2c@7000d000 {
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
|
||||
pmic: tps6586x@34 {
|
||||
compatible = "ti,tps6586x";
|
||||
reg = <0x34>;
|
||||
interrupts = <0 86 0x4>;
|
||||
|
||||
ti,system-power-controller;
|
||||
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
|
||||
sys-supply = <&vdd_5v0_reg>;
|
||||
vin-sm0-supply = <&sys_reg>;
|
||||
vin-sm1-supply = <&sys_reg>;
|
||||
vin-sm2-supply = <&sys_reg>;
|
||||
vinldo01-supply = <&sm2_reg>;
|
||||
vinldo23-supply = <&sm2_reg>;
|
||||
vinldo4-supply = <&sm2_reg>;
|
||||
vinldo678-supply = <&sm2_reg>;
|
||||
vinldo9-supply = <&sm2_reg>;
|
||||
|
||||
regulators {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
sys_reg: regulator@0 {
|
||||
reg = <0>;
|
||||
regulator-compatible = "sys";
|
||||
regulator-name = "vdd_sys";
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@1 {
|
||||
reg = <1>;
|
||||
regulator-compatible = "sm0";
|
||||
regulator-name = "vdd_sys_sm0,vdd_core";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@2 {
|
||||
reg = <2>;
|
||||
regulator-compatible = "sm1";
|
||||
regulator-name = "vdd_sys_sm1,vdd_cpu";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
sm2_reg: regulator@3 {
|
||||
reg = <3>;
|
||||
regulator-compatible = "sm2";
|
||||
regulator-name = "vdd_sys_sm2,vin_ldo*";
|
||||
regulator-min-microvolt = <3700000>;
|
||||
regulator-max-microvolt = <3700000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@4 {
|
||||
reg = <4>;
|
||||
regulator-compatible = "ldo0";
|
||||
regulator-name = "vdd_ldo0,vddio_pex_clk";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
regulator@5 {
|
||||
reg = <5>;
|
||||
regulator-compatible = "ldo1";
|
||||
regulator-name = "vdd_ldo1,avdd_pll*";
|
||||
regulator-min-microvolt = <1100000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@6 {
|
||||
reg = <6>;
|
||||
regulator-compatible = "ldo2";
|
||||
regulator-name = "vdd_ldo2,vdd_rtc";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
};
|
||||
|
||||
regulator@7 {
|
||||
reg = <7>;
|
||||
regulator-compatible = "ldo3";
|
||||
regulator-name = "vdd_ldo3,avdd_usb*";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@8 {
|
||||
reg = <8>;
|
||||
regulator-compatible = "ldo4";
|
||||
regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@9 {
|
||||
reg = <9>;
|
||||
regulator-compatible = "ldo5";
|
||||
regulator-name = "vdd_ldo5,vcore_mmc";
|
||||
regulator-min-microvolt = <2850000>;
|
||||
regulator-max-microvolt = <2850000>;
|
||||
};
|
||||
|
||||
regulator@10 {
|
||||
reg = <10>;
|
||||
regulator-compatible = "ldo6";
|
||||
regulator-name = "vdd_ldo6,avdd_vdac";
|
||||
/*
|
||||
* According to the Tegra 2 Automotive
|
||||
* DataSheet, a typical value for this
|
||||
* would be 2.8V, but the PMIC only
|
||||
* supports 2.85V.
|
||||
*/
|
||||
regulator-min-microvolt = <2850000>;
|
||||
regulator-max-microvolt = <2850000>;
|
||||
};
|
||||
|
||||
regulator@11 {
|
||||
reg = <11>;
|
||||
regulator-compatible = "ldo7";
|
||||
regulator-name = "vdd_ldo7,avdd_hdmi";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
regulator@12 {
|
||||
reg = <12>;
|
||||
regulator-compatible = "ldo8";
|
||||
regulator-name = "vdd_ldo8,avdd_hdmi_pll";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
regulator@13 {
|
||||
reg = <13>;
|
||||
regulator-compatible = "ldo9";
|
||||
regulator-name = "vdd_ldo9,vdd_ddr_rx,avdd_cam";
|
||||
/*
|
||||
* According to the Tegra 2 Automotive
|
||||
* DataSheet, a typical value for this
|
||||
* would be 2.8V, but the PMIC only
|
||||
* supports 2.85V.
|
||||
*/
|
||||
regulator-min-microvolt = <2850000>;
|
||||
regulator-max-microvolt = <2850000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@14 {
|
||||
reg = <14>;
|
||||
regulator-compatible = "ldo_rtc";
|
||||
regulator-name = "vdd_rtc_out";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pmc {
|
||||
nvidia,invert-interrupt;
|
||||
};
|
||||
|
||||
usb@c5008000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
sdhci@c8000600 {
|
||||
cd-gpios = <&gpio 58 0>; /* gpio PH2 */
|
||||
wp-gpios = <&gpio 59 0>; /* gpio PH3 */
|
||||
bus-width = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
vdd_5v0_reg: regulator@0 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <0>;
|
||||
regulator-name = "vdd_5v0";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
53
arch/arm/boot/dts/tegra20-tec.dts
Normal file
53
arch/arm/boot/dts/tegra20-tec.dts
Normal file
@ -0,0 +1,53 @@
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "tegra20-tamonten.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Avionic Design Tamonten Evaluation Carrier";
|
||||
compatible = "ad,tec", "ad,tamonten", "nvidia,tegra20";
|
||||
|
||||
i2c@7000c000 {
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
|
||||
wm8903: wm8903@1a {
|
||||
compatible = "wlf,wm8903";
|
||||
reg = <0x1a>;
|
||||
interrupt-parent = <&gpio>;
|
||||
interrupts = <187 0x04>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
micdet-cfg = <0>;
|
||||
micdet-delay = <100>;
|
||||
gpio-cfg = <0xffffffff
|
||||
0xffffffff
|
||||
0
|
||||
0xffffffff
|
||||
0xffffffff>;
|
||||
};
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "ad,tegra-audio-wm8903-tec",
|
||||
"nvidia,tegra-audio-wm8903";
|
||||
nvidia,model = "Avionic Design TEC";
|
||||
|
||||
nvidia,audio-routing =
|
||||
"Headphone Jack", "HPOUTR",
|
||||
"Headphone Jack", "HPOUTL",
|
||||
"Int Spk", "ROP",
|
||||
"Int Spk", "RON",
|
||||
"Int Spk", "LOP",
|
||||
"Int Spk", "LON",
|
||||
"Mic Jack", "MICBIAS",
|
||||
"IN1L", "Mic Jack";
|
||||
|
||||
nvidia,i2s-controller = <&tegra_i2s1>;
|
||||
nvidia,audio-codec = <&wm8903>;
|
||||
|
||||
nvidia,spkr-en-gpios = <&wm8903 2 0>;
|
||||
nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
|
||||
};
|
||||
};
|
||||
@ -289,6 +289,158 @@
|
||||
i2c@7000d000 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
pmic: tps6586x@34 {
|
||||
compatible = "ti,tps6586x";
|
||||
reg = <0x34>;
|
||||
interrupts = <0 86 0x4>;
|
||||
|
||||
ti,system-power-controller;
|
||||
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
|
||||
sys-supply = <&vdd_5v0_reg>;
|
||||
vin-sm0-supply = <&sys_reg>;
|
||||
vin-sm1-supply = <&sys_reg>;
|
||||
vin-sm2-supply = <&sys_reg>;
|
||||
vinldo01-supply = <&sm2_reg>;
|
||||
vinldo23-supply = <&sm2_reg>;
|
||||
vinldo4-supply = <&sm2_reg>;
|
||||
vinldo678-supply = <&sm2_reg>;
|
||||
vinldo9-supply = <&sm2_reg>;
|
||||
|
||||
regulators {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
sys_reg: regulator@0 {
|
||||
reg = <0>;
|
||||
regulator-compatible = "sys";
|
||||
regulator-name = "vdd_sys";
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@1 {
|
||||
reg = <1>;
|
||||
regulator-compatible = "sm0";
|
||||
regulator-name = "vdd_sm0,vdd_core";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@2 {
|
||||
reg = <2>;
|
||||
regulator-compatible = "sm1";
|
||||
regulator-name = "vdd_sm1,vdd_cpu";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
sm2_reg: regulator@3 {
|
||||
reg = <3>;
|
||||
regulator-compatible = "sm2";
|
||||
regulator-name = "vdd_sm2,vin_ldo*";
|
||||
regulator-min-microvolt = <3700000>;
|
||||
regulator-max-microvolt = <3700000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
/* LDO0 is not connected to anything */
|
||||
|
||||
regulator@5 {
|
||||
reg = <5>;
|
||||
regulator-compatible = "ldo1";
|
||||
regulator-name = "vdd_ldo1,avdd_pll*";
|
||||
regulator-min-microvolt = <1100000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@6 {
|
||||
reg = <6>;
|
||||
regulator-compatible = "ldo2";
|
||||
regulator-name = "vdd_ldo2,vdd_rtc";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
};
|
||||
|
||||
regulator@7 {
|
||||
reg = <7>;
|
||||
regulator-compatible = "ldo3";
|
||||
regulator-name = "vdd_ldo3,avdd_usb*";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@8 {
|
||||
reg = <8>;
|
||||
regulator-compatible = "ldo4";
|
||||
regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@9 {
|
||||
reg = <9>;
|
||||
regulator-compatible = "ldo5";
|
||||
regulator-name = "vdd_ldo5,vcore_mmc";
|
||||
regulator-min-microvolt = <2850000>;
|
||||
regulator-max-microvolt = <2850000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@10 {
|
||||
reg = <10>;
|
||||
regulator-compatible = "ldo6";
|
||||
regulator-name = "vdd_ldo6,avdd_vdac";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
regulator@11 {
|
||||
reg = <11>;
|
||||
regulator-compatible = "ldo7";
|
||||
regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
regulator@12 {
|
||||
reg = <12>;
|
||||
regulator-compatible = "ldo8";
|
||||
regulator-name = "vdd_ldo8,avdd_hdmi_pll";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
regulator@13 {
|
||||
reg = <13>;
|
||||
regulator-compatible = "ldo9";
|
||||
regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
|
||||
regulator-min-microvolt = <2850000>;
|
||||
regulator-max-microvolt = <2850000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@14 {
|
||||
reg = <14>;
|
||||
regulator-compatible = "ldo_rtc";
|
||||
regulator-name = "vdd_rtc_out,vdd_cell";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pmc {
|
||||
nvidia,invert-interrupt;
|
||||
};
|
||||
|
||||
usb@c5000000 {
|
||||
@ -317,6 +469,60 @@
|
||||
bus-width = <8>;
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
vdd_5v0_reg: regulator@0 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <0>;
|
||||
regulator-name = "vdd_5v0";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@1 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <1>;
|
||||
regulator-name = "vdd_1v5";
|
||||
regulator-min-microvolt = <1500000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
gpio = <&pmic 0 0>;
|
||||
};
|
||||
|
||||
regulator@2 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <2>;
|
||||
regulator-name = "vdd_1v2";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
gpio = <&pmic 1 0>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
regulator@3 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <3>;
|
||||
regulator-name = "vdd_pnl";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
gpio = <&gpio 22 0>; /* gpio PC6 */
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
regulator@4 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <4>;
|
||||
regulator-name = "vdd_bl";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
gpio = <&gpio 176 0>; /* gpio PW0 */
|
||||
enable-active-high;
|
||||
};
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "nvidia,tegra-audio-wm8903-ventana",
|
||||
"nvidia,tegra-audio-wm8903";
|
||||
|
||||
@ -261,6 +261,286 @@
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
max8907@3c {
|
||||
compatible = "maxim,max8907";
|
||||
reg = <0x3c>;
|
||||
interrupts = <0 86 0x4>;
|
||||
|
||||
maxim,system-power-controller;
|
||||
|
||||
mbatt-supply = <&usb0_vbus_reg>;
|
||||
in-v1-supply = <&mbatt_reg>;
|
||||
in-v2-supply = <&mbatt_reg>;
|
||||
in-v3-supply = <&mbatt_reg>;
|
||||
in1-supply = <&mbatt_reg>;
|
||||
in2-supply = <&nvvdd_sv3_reg>;
|
||||
in3-supply = <&mbatt_reg>;
|
||||
in4-supply = <&mbatt_reg>;
|
||||
in5-supply = <&mbatt_reg>;
|
||||
in6-supply = <&mbatt_reg>;
|
||||
in7-supply = <&mbatt_reg>;
|
||||
in8-supply = <&mbatt_reg>;
|
||||
in9-supply = <&mbatt_reg>;
|
||||
in10-supply = <&mbatt_reg>;
|
||||
in11-supply = <&mbatt_reg>;
|
||||
in12-supply = <&mbatt_reg>;
|
||||
in13-supply = <&mbatt_reg>;
|
||||
in14-supply = <&mbatt_reg>;
|
||||
in15-supply = <&mbatt_reg>;
|
||||
in16-supply = <&mbatt_reg>;
|
||||
in17-supply = <&nvvdd_sv3_reg>;
|
||||
in18-supply = <&nvvdd_sv3_reg>;
|
||||
in19-supply = <&mbatt_reg>;
|
||||
in20-supply = <&mbatt_reg>;
|
||||
|
||||
regulators {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mbatt_reg: regulator@0 {
|
||||
reg = <0>;
|
||||
regulator-compatible = "mbatt";
|
||||
regulator-name = "vbat_pmu";
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@1 {
|
||||
reg = <1>;
|
||||
regulator-compatible = "sd1";
|
||||
regulator-name = "nvvdd_sv1,vdd_cpu_pmu";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@2 {
|
||||
reg = <2>;
|
||||
regulator-compatible = "sd2";
|
||||
regulator-name = "nvvdd_sv2,vdd_core";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
nvvdd_sv3_reg: regulator@3 {
|
||||
reg = <3>;
|
||||
regulator-compatible = "sd3";
|
||||
regulator-name = "nvvdd_sv3";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@4 {
|
||||
reg = <4>;
|
||||
regulator-compatible = "ldo1";
|
||||
regulator-name = "nvvdd_ldo1,vddio_rx_ddr,vcore_acc";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@5 {
|
||||
reg = <5>;
|
||||
regulator-compatible = "ldo2";
|
||||
regulator-name = "nvvdd_ldo2,avdd_pll*";
|
||||
regulator-min-microvolt = <1100000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@6 {
|
||||
reg = <6>;
|
||||
regulator-compatible = "ldo3";
|
||||
regulator-name = "nvvdd_ldo3,vcom_1v8b";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@7 {
|
||||
reg = <7>;
|
||||
regulator-compatible = "ldo4";
|
||||
regulator-name = "nvvdd_ldo4,avdd_usb*";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@8 {
|
||||
reg = <8>;
|
||||
regulator-compatible = "ldo5";
|
||||
regulator-name = "nvvdd_ldo5,vcore_mmc,avdd_lcd1,vddio_1wire";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@9 {
|
||||
reg = <9>;
|
||||
regulator-compatible = "ldo6";
|
||||
regulator-name = "nvvdd_ldo6,avdd_hdmi_pll";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
regulator@10 {
|
||||
reg = <10>;
|
||||
regulator-compatible = "ldo7";
|
||||
regulator-name = "nvvdd_ldo7,avddio_audio";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@11 {
|
||||
reg = <11>;
|
||||
regulator-compatible = "ldo8";
|
||||
regulator-name = "nvvdd_ldo8,vcom_3v0,vcore_cmps";
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
};
|
||||
|
||||
regulator@12 {
|
||||
reg = <12>;
|
||||
regulator-compatible = "ldo9";
|
||||
regulator-name = "nvvdd_ldo9,avdd_cam*";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
};
|
||||
|
||||
regulator@13 {
|
||||
reg = <13>;
|
||||
regulator-compatible = "ldo10";
|
||||
regulator-name = "nvvdd_ldo10,avdd_usb_ic_3v0";
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@14 {
|
||||
reg = <14>;
|
||||
regulator-compatible = "ldo11";
|
||||
regulator-name = "nvvdd_ldo11,vddio_pex_clk,vcom_33,avdd_hdmi";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
regulator@15 {
|
||||
reg = <15>;
|
||||
regulator-compatible = "ldo12";
|
||||
regulator-name = "nvvdd_ldo12,vddio_sdio";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@16 {
|
||||
reg = <16>;
|
||||
regulator-compatible = "ldo13";
|
||||
regulator-name = "nvvdd_ldo13,vcore_phtn,vdd_af";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
};
|
||||
|
||||
regulator@17 {
|
||||
reg = <17>;
|
||||
regulator-compatible = "ldo14";
|
||||
regulator-name = "nvvdd_ldo14,avdd_vdac";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
};
|
||||
|
||||
regulator@18 {
|
||||
reg = <18>;
|
||||
regulator-compatible = "ldo15";
|
||||
regulator-name = "nvvdd_ldo15,vcore_temp,vddio_hdcp";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
regulator@19 {
|
||||
reg = <19>;
|
||||
regulator-compatible = "ldo16";
|
||||
regulator-name = "nvvdd_ldo16,vdd_dbrtr";
|
||||
regulator-min-microvolt = <1300000>;
|
||||
regulator-max-microvolt = <1300000>;
|
||||
};
|
||||
|
||||
regulator@20 {
|
||||
reg = <20>;
|
||||
regulator-compatible = "ldo17";
|
||||
regulator-name = "nvvdd_ldo17,vddio_mipi";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
};
|
||||
|
||||
regulator@21 {
|
||||
reg = <21>;
|
||||
regulator-compatible = "ldo18";
|
||||
regulator-name = "nvvdd_ldo18,vddio_vi,vcore_cam*";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
regulator@22 {
|
||||
reg = <22>;
|
||||
regulator-compatible = "ldo19";
|
||||
regulator-name = "nvvdd_ldo19,avdd_lcd2,vddio_lx";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
};
|
||||
|
||||
regulator@23 {
|
||||
reg = <23>;
|
||||
regulator-compatible = "ldo20";
|
||||
regulator-name = "nvvdd_ldo20,vddio_ddr_1v2,vddio_hsic,vcom_1v2";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@24 {
|
||||
reg = <24>;
|
||||
regulator-compatible = "out5v";
|
||||
regulator-name = "usb0_vbus_reg";
|
||||
};
|
||||
|
||||
regulator@25 {
|
||||
reg = <25>;
|
||||
regulator-compatible = "out33v";
|
||||
regulator-name = "pmu_out3v3";
|
||||
};
|
||||
|
||||
regulator@26 {
|
||||
reg = <26>;
|
||||
regulator-compatible = "bbat";
|
||||
regulator-name = "pmu_bbat";
|
||||
regulator-min-microvolt = <2400000>;
|
||||
regulator-max-microvolt = <2400000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@27 {
|
||||
reg = <27>;
|
||||
regulator-compatible = "sdby";
|
||||
regulator-name = "vdd_aon";
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@28 {
|
||||
reg = <28>;
|
||||
regulator-compatible = "vrtc";
|
||||
regulator-name = "vrtc,pmu_vccadc";
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pmc {
|
||||
nvidia,invert-interrupt;
|
||||
};
|
||||
|
||||
usb@c5000000 {
|
||||
@ -284,6 +564,21 @@
|
||||
bus-width = <8>;
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
usb0_vbus_reg: regulator {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <0>;
|
||||
regulator-name = "usb0_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "nvidia,tegra-audio-wm8753-whistler",
|
||||
"nvidia,tegra-audio-wm8753";
|
||||
|
||||
@ -123,7 +123,7 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm {
|
||||
pwm: pwm {
|
||||
compatible = "nvidia,tegra20-pwm";
|
||||
reg = <0x7000a000 0x100>;
|
||||
#pwm-cells = <2>;
|
||||
|
||||
87
arch/arm/boot/dts/tegra30-cardhu-a02.dts
Normal file
87
arch/arm/boot/dts/tegra30-cardhu-a02.dts
Normal file
@ -0,0 +1,87 @@
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "tegra30-cardhu.dtsi"
|
||||
|
||||
/* This dts file support the cardhu A02 version of board */
|
||||
|
||||
/ {
|
||||
model = "NVIDIA Tegra30 Cardhu A02 evaluation board";
|
||||
compatible = "nvidia,cardhu-a02", "nvidia,cardhu", "nvidia,tegra30";
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ddr_reg: regulator@100 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <100>;
|
||||
regulator-name = "vdd_ddr";
|
||||
regulator-min-microvolt = <1500000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
enable-active-high;
|
||||
gpio = <&pmic 6 0>;
|
||||
};
|
||||
|
||||
sys_3v3_reg: regulator@101 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <101>;
|
||||
regulator-name = "sys_3v3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
enable-active-high;
|
||||
gpio = <&pmic 7 0>;
|
||||
};
|
||||
|
||||
usb1_vbus_reg: regulator@102 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <102>;
|
||||
regulator-name = "usb1_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
gpio = <&gpio 68 0>; /* GPIO PI4 */
|
||||
gpio-open-drain;
|
||||
vin-supply = <&vdd_5v0_reg>;
|
||||
};
|
||||
|
||||
usb3_vbus_reg: regulator@103 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <103>;
|
||||
regulator-name = "usb3_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
gpio = <&gpio 63 0>; /* GPIO PH7 */
|
||||
gpio-open-drain;
|
||||
vin-supply = <&vdd_5v0_reg>;
|
||||
};
|
||||
|
||||
vdd_5v0_reg: regulator@104 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <104>;
|
||||
regulator-name = "5v0";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
gpio = <&pmic 2 0>;
|
||||
};
|
||||
|
||||
vdd_bl_reg: regulator@105 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <105>;
|
||||
regulator-name = "vdd_bl";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
enable-active-high;
|
||||
gpio = <&gpio 83 0>; /* GPIO PK3 */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
98
arch/arm/boot/dts/tegra30-cardhu-a04.dts
Normal file
98
arch/arm/boot/dts/tegra30-cardhu-a04.dts
Normal file
@ -0,0 +1,98 @@
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "tegra30-cardhu.dtsi"
|
||||
|
||||
/* This dts file support the cardhu A04 and later versions of board */
|
||||
|
||||
/ {
|
||||
model = "NVIDIA Tegra30 Cardhu A04 (A05, A06, A07) evaluation board";
|
||||
compatible = "nvidia,cardhu-a04", "nvidia,cardhu", "nvidia,tegra30";
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ddr_reg: regulator@100 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "ddr";
|
||||
reg = <100>;
|
||||
regulator-min-microvolt = <1500000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
enable-active-high;
|
||||
gpio = <&pmic 7 0>;
|
||||
};
|
||||
|
||||
sys_3v3_reg: regulator@101 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <101>;
|
||||
regulator-name = "sys_3v3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
enable-active-high;
|
||||
gpio = <&pmic 6 0>;
|
||||
};
|
||||
|
||||
usb1_vbus_reg: regulator@102 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <102>;
|
||||
regulator-name = "usb1_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
gpio = <&gpio 238 0>; /* GPIO PDD6 */
|
||||
gpio-open-drain;
|
||||
vin-supply = <&vdd_5v0_reg>;
|
||||
};
|
||||
|
||||
usb3_vbus_reg: regulator@103 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <103>;
|
||||
regulator-name = "usb3_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
gpio = <&gpio 236 0>; /* GPIO PDD4 */
|
||||
gpio-open-drain;
|
||||
vin-supply = <&vdd_5v0_reg>;
|
||||
};
|
||||
|
||||
vdd_5v0_reg: regulator@104 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <104>;
|
||||
regulator-name = "5v0";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
gpio = <&pmic 8 0>;
|
||||
};
|
||||
|
||||
vdd_bl_reg: regulator@105 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <105>;
|
||||
regulator-name = "vdd_bl";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
enable-active-high;
|
||||
gpio = <&gpio 234 0>; /* GPIO PDD2 */
|
||||
};
|
||||
|
||||
vdd_bl2_reg: regulator@106 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <106>;
|
||||
regulator-name = "vdd_bl2";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
enable-active-high;
|
||||
gpio = <&gpio 232 0>; /* GPIO PDD0 */
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -1,171 +0,0 @@
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "tegra30.dtsi"
|
||||
|
||||
/ {
|
||||
model = "NVIDIA Tegra30 Cardhu evaluation board";
|
||||
compatible = "nvidia,cardhu", "nvidia,tegra30";
|
||||
|
||||
memory {
|
||||
reg = <0x80000000 0x40000000>;
|
||||
};
|
||||
|
||||
pinmux {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&state_default>;
|
||||
|
||||
state_default: pinmux {
|
||||
sdmmc1_clk_pz0 {
|
||||
nvidia,pins = "sdmmc1_clk_pz0";
|
||||
nvidia,function = "sdmmc1";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
sdmmc1_cmd_pz1 {
|
||||
nvidia,pins = "sdmmc1_cmd_pz1",
|
||||
"sdmmc1_dat0_py7",
|
||||
"sdmmc1_dat1_py6",
|
||||
"sdmmc1_dat2_py5",
|
||||
"sdmmc1_dat3_py4";
|
||||
nvidia,function = "sdmmc1";
|
||||
nvidia,pull = <2>;
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
sdmmc4_clk_pcc4 {
|
||||
nvidia,pins = "sdmmc4_clk_pcc4",
|
||||
"sdmmc4_rst_n_pcc3";
|
||||
nvidia,function = "sdmmc4";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
sdmmc4_dat0_paa0 {
|
||||
nvidia,pins = "sdmmc4_dat0_paa0",
|
||||
"sdmmc4_dat1_paa1",
|
||||
"sdmmc4_dat2_paa2",
|
||||
"sdmmc4_dat3_paa3",
|
||||
"sdmmc4_dat4_paa4",
|
||||
"sdmmc4_dat5_paa5",
|
||||
"sdmmc4_dat6_paa6",
|
||||
"sdmmc4_dat7_paa7";
|
||||
nvidia,function = "sdmmc4";
|
||||
nvidia,pull = <2>;
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
dap2_fs_pa2 {
|
||||
nvidia,pins = "dap2_fs_pa2",
|
||||
"dap2_sclk_pa3",
|
||||
"dap2_din_pa4",
|
||||
"dap2_dout_pa5";
|
||||
nvidia,function = "i2s1";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
serial@70006000 {
|
||||
status = "okay";
|
||||
clock-frequency = <408000000>;
|
||||
};
|
||||
|
||||
i2c@7000c000 {
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
i2c@7000c400 {
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
i2c@7000c500 {
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
|
||||
/* ALS and Proximity sensor */
|
||||
isl29028@44 {
|
||||
compatible = "isil,isl29028";
|
||||
reg = <0x44>;
|
||||
interrupt-parent = <&gpio>;
|
||||
interrupts = <88 0x04>; /*gpio PL0 */
|
||||
};
|
||||
};
|
||||
|
||||
i2c@7000c700 {
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
i2c@7000d000 {
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
|
||||
wm8903: wm8903@1a {
|
||||
compatible = "wlf,wm8903";
|
||||
reg = <0x1a>;
|
||||
interrupt-parent = <&gpio>;
|
||||
interrupts = <179 0x04>; /* gpio PW3 */
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
micdet-cfg = <0>;
|
||||
micdet-delay = <100>;
|
||||
gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
|
||||
};
|
||||
|
||||
tps62361 {
|
||||
compatible = "ti,tps62361";
|
||||
reg = <0x60>;
|
||||
|
||||
regulator-name = "tps62361-vout";
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
ti,vsel0-state-high;
|
||||
ti,vsel1-state-high;
|
||||
};
|
||||
};
|
||||
|
||||
ahub {
|
||||
i2s@70080400 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
sdhci@78000000 {
|
||||
status = "okay";
|
||||
cd-gpios = <&gpio 69 0>; /* gpio PI5 */
|
||||
wp-gpios = <&gpio 155 0>; /* gpio PT3 */
|
||||
power-gpios = <&gpio 31 0>; /* gpio PD7 */
|
||||
bus-width = <4>;
|
||||
};
|
||||
|
||||
sdhci@78000600 {
|
||||
status = "okay";
|
||||
bus-width = <8>;
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "nvidia,tegra-audio-wm8903-cardhu",
|
||||
"nvidia,tegra-audio-wm8903";
|
||||
nvidia,model = "NVIDIA Tegra Cardhu";
|
||||
|
||||
nvidia,audio-routing =
|
||||
"Headphone Jack", "HPOUTR",
|
||||
"Headphone Jack", "HPOUTL",
|
||||
"Int Spk", "ROP",
|
||||
"Int Spk", "RON",
|
||||
"Int Spk", "LOP",
|
||||
"Int Spk", "LON",
|
||||
"Mic Jack", "MICBIAS",
|
||||
"IN1L", "Mic Jack";
|
||||
|
||||
nvidia,i2s-controller = <&tegra_i2s1>;
|
||||
nvidia,audio-codec = <&wm8903>;
|
||||
|
||||
nvidia,spkr-en-gpios = <&wm8903 2 0>;
|
||||
nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
|
||||
};
|
||||
};
|
||||
475
arch/arm/boot/dts/tegra30-cardhu.dtsi
Normal file
475
arch/arm/boot/dts/tegra30-cardhu.dtsi
Normal file
@ -0,0 +1,475 @@
|
||||
/include/ "tegra30.dtsi"
|
||||
|
||||
/**
|
||||
* This file contains common DT entry for all fab version of Cardhu.
|
||||
* There is multiple fab version of Cardhu starting from A01 to A07.
|
||||
* Cardhu fab version A01 and A03 are not supported. Cardhu fab version
|
||||
* A02 will have different sets of GPIOs for fixed regulator compare to
|
||||
* Cardhu fab version A04. The Cardhu fab version A05, A06, A07 are
|
||||
* compatible with fab version A04. Based on Cardhu fab version, the
|
||||
* related dts file need to be chosen like for Cardhu fab version A02,
|
||||
* use tegra30-cardhu-a02.dts, Cardhu fab version A04 and later, use
|
||||
* tegra30-cardhu-a04.dts.
|
||||
* The identification of board is done in two ways, by looking the sticker
|
||||
* on PCB and by reading board id eeprom.
|
||||
* The stciker will have number like 600-81291-1000-002 C.3. In this 4th
|
||||
* number is the fab version like here it is 002 and hence fab version A02.
|
||||
* The (downstream internal) U-Boot of Cardhu display the board-id as
|
||||
* follows:
|
||||
* BoardID: 0C5B, SKU: 0A01, Fab: 02, Rev: 45.00
|
||||
* In this Fab version is 02 i.e. A02.
|
||||
* The BoardID I2C eeprom is interfaced through i2c5 (pwr_i2c address 0x56).
|
||||
* The location 0x8 of this eeprom contains the Fab version. It is 1 byte
|
||||
* wide.
|
||||
*/
|
||||
|
||||
/ {
|
||||
model = "NVIDIA Tegra30 Cardhu evaluation board";
|
||||
compatible = "nvidia,cardhu", "nvidia,tegra30";
|
||||
|
||||
memory {
|
||||
reg = <0x80000000 0x40000000>;
|
||||
};
|
||||
|
||||
pinmux {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&state_default>;
|
||||
|
||||
state_default: pinmux {
|
||||
sdmmc1_clk_pz0 {
|
||||
nvidia,pins = "sdmmc1_clk_pz0";
|
||||
nvidia,function = "sdmmc1";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
sdmmc1_cmd_pz1 {
|
||||
nvidia,pins = "sdmmc1_cmd_pz1",
|
||||
"sdmmc1_dat0_py7",
|
||||
"sdmmc1_dat1_py6",
|
||||
"sdmmc1_dat2_py5",
|
||||
"sdmmc1_dat3_py4";
|
||||
nvidia,function = "sdmmc1";
|
||||
nvidia,pull = <2>;
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
sdmmc4_clk_pcc4 {
|
||||
nvidia,pins = "sdmmc4_clk_pcc4",
|
||||
"sdmmc4_rst_n_pcc3";
|
||||
nvidia,function = "sdmmc4";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
sdmmc4_dat0_paa0 {
|
||||
nvidia,pins = "sdmmc4_dat0_paa0",
|
||||
"sdmmc4_dat1_paa1",
|
||||
"sdmmc4_dat2_paa2",
|
||||
"sdmmc4_dat3_paa3",
|
||||
"sdmmc4_dat4_paa4",
|
||||
"sdmmc4_dat5_paa5",
|
||||
"sdmmc4_dat6_paa6",
|
||||
"sdmmc4_dat7_paa7";
|
||||
nvidia,function = "sdmmc4";
|
||||
nvidia,pull = <2>;
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
dap2_fs_pa2 {
|
||||
nvidia,pins = "dap2_fs_pa2",
|
||||
"dap2_sclk_pa3",
|
||||
"dap2_din_pa4",
|
||||
"dap2_dout_pa5";
|
||||
nvidia,function = "i2s1";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
serial@70006000 {
|
||||
status = "okay";
|
||||
clock-frequency = <408000000>;
|
||||
};
|
||||
|
||||
i2c@7000c000 {
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
i2c@7000c400 {
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
i2c@7000c500 {
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
|
||||
/* ALS and Proximity sensor */
|
||||
isl29028@44 {
|
||||
compatible = "isil,isl29028";
|
||||
reg = <0x44>;
|
||||
interrupt-parent = <&gpio>;
|
||||
interrupts = <88 0x04>; /*gpio PL0 */
|
||||
};
|
||||
};
|
||||
|
||||
i2c@7000c700 {
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
i2c@7000d000 {
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
|
||||
wm8903: wm8903@1a {
|
||||
compatible = "wlf,wm8903";
|
||||
reg = <0x1a>;
|
||||
interrupt-parent = <&gpio>;
|
||||
interrupts = <179 0x04>; /* gpio PW3 */
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
micdet-cfg = <0>;
|
||||
micdet-delay = <100>;
|
||||
gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
|
||||
};
|
||||
|
||||
tps62361 {
|
||||
compatible = "ti,tps62361";
|
||||
reg = <0x60>;
|
||||
|
||||
regulator-name = "tps62361-vout";
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
ti,vsel0-state-high;
|
||||
ti,vsel1-state-high;
|
||||
};
|
||||
|
||||
pmic: tps65911@2d {
|
||||
compatible = "ti,tps65911";
|
||||
reg = <0x2d>;
|
||||
|
||||
interrupts = <0 86 0x4>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
|
||||
ti,system-power-controller;
|
||||
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
|
||||
vcc1-supply = <&vdd_ac_bat_reg>;
|
||||
vcc2-supply = <&vdd_ac_bat_reg>;
|
||||
vcc3-supply = <&vio_reg>;
|
||||
vcc4-supply = <&vdd_5v0_reg>;
|
||||
vcc5-supply = <&vdd_ac_bat_reg>;
|
||||
vcc6-supply = <&vdd2_reg>;
|
||||
vcc7-supply = <&vdd_ac_bat_reg>;
|
||||
vccio-supply = <&vdd_ac_bat_reg>;
|
||||
|
||||
regulators {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
vdd1_reg: regulator@0 {
|
||||
reg = <0>;
|
||||
regulator-compatible = "vdd1";
|
||||
regulator-name = "vddio_ddr_1v2";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdd2_reg: regulator@1 {
|
||||
reg = <1>;
|
||||
regulator-compatible = "vdd2";
|
||||
regulator-name = "vdd_1v5_gen";
|
||||
regulator-min-microvolt = <1500000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vddctrl_reg: regulator@2 {
|
||||
reg = <2>;
|
||||
regulator-compatible = "vddctrl";
|
||||
regulator-name = "vdd_cpu,vdd_sys";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vio_reg: regulator@3 {
|
||||
reg = <3>;
|
||||
regulator-compatible = "vio";
|
||||
regulator-name = "vdd_1v8_gen";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo1_reg: regulator@4 {
|
||||
reg = <4>;
|
||||
regulator-compatible = "ldo1";
|
||||
regulator-name = "vdd_pexa,vdd_pexb";
|
||||
regulator-min-microvolt = <1050000>;
|
||||
regulator-max-microvolt = <1050000>;
|
||||
};
|
||||
|
||||
ldo2_reg: regulator@5 {
|
||||
reg = <5>;
|
||||
regulator-compatible = "ldo2";
|
||||
regulator-name = "vdd_sata,avdd_plle";
|
||||
regulator-min-microvolt = <1050000>;
|
||||
regulator-max-microvolt = <1050000>;
|
||||
};
|
||||
|
||||
/* LDO3 is not connected to anything */
|
||||
|
||||
ldo4_reg: regulator@7 {
|
||||
reg = <7>;
|
||||
regulator-compatible = "ldo4";
|
||||
regulator-name = "vdd_rtc";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo5_reg: regulator@8 {
|
||||
reg = <8>;
|
||||
regulator-compatible = "ldo5";
|
||||
regulator-name = "vddio_sdmmc,avdd_vdac";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo6_reg: regulator@9 {
|
||||
reg = <9>;
|
||||
regulator-compatible = "ldo6";
|
||||
regulator-name = "avdd_dsi_csi,pwrdet_mipi";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
};
|
||||
|
||||
ldo7_reg: regulator@10 {
|
||||
reg = <10>;
|
||||
regulator-compatible = "ldo7";
|
||||
regulator-name = "vdd_pllm,x,u,a_p_c_s";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo8_reg: regulator@11 {
|
||||
reg = <11>;
|
||||
regulator-compatible = "ldo8";
|
||||
regulator-name = "vdd_ddr_hs";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ahub {
|
||||
i2s@70080400 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
pmc {
|
||||
status = "okay";
|
||||
nvidia,invert-interrupt;
|
||||
};
|
||||
|
||||
sdhci@78000000 {
|
||||
status = "okay";
|
||||
cd-gpios = <&gpio 69 0>; /* gpio PI5 */
|
||||
wp-gpios = <&gpio 155 0>; /* gpio PT3 */
|
||||
power-gpios = <&gpio 31 0>; /* gpio PD7 */
|
||||
bus-width = <4>;
|
||||
};
|
||||
|
||||
sdhci@78000600 {
|
||||
status = "okay";
|
||||
bus-width = <8>;
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
vdd_ac_bat_reg: regulator@0 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <0>;
|
||||
regulator-name = "vdd_ac_bat";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
cam_1v8_reg: regulator@1 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <1>;
|
||||
regulator-name = "cam_1v8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
enable-active-high;
|
||||
gpio = <&gpio 220 0>; /* gpio PBB4 */
|
||||
vin-supply = <&vio_reg>;
|
||||
};
|
||||
|
||||
cp_5v_reg: regulator@2 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <2>;
|
||||
regulator-name = "cp_5v";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
enable-active-high;
|
||||
gpio = <&pmic 0 0>; /* PMIC TPS65911 GPIO0 */
|
||||
};
|
||||
|
||||
emmc_3v3_reg: regulator@3 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <3>;
|
||||
regulator-name = "emmc_3v3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
enable-active-high;
|
||||
gpio = <&gpio 25 0>; /* gpio PD1 */
|
||||
vin-supply = <&sys_3v3_reg>;
|
||||
};
|
||||
|
||||
modem_3v3_reg: regulator@4 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <4>;
|
||||
regulator-name = "modem_3v3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
enable-active-high;
|
||||
gpio = <&gpio 30 0>; /* gpio PD6 */
|
||||
};
|
||||
|
||||
pex_hvdd_3v3_reg: regulator@5 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <5>;
|
||||
regulator-name = "pex_hvdd_3v3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
enable-active-high;
|
||||
gpio = <&gpio 95 0>; /* gpio PL7 */
|
||||
vin-supply = <&sys_3v3_reg>;
|
||||
};
|
||||
|
||||
vdd_cam1_ldo_reg: regulator@6 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <6>;
|
||||
regulator-name = "vdd_cam1_ldo";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
enable-active-high;
|
||||
gpio = <&gpio 142 0>; /* gpio PR6 */
|
||||
vin-supply = <&sys_3v3_reg>;
|
||||
};
|
||||
|
||||
vdd_cam2_ldo_reg: regulator@7 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <7>;
|
||||
regulator-name = "vdd_cam2_ldo";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
enable-active-high;
|
||||
gpio = <&gpio 143 0>; /* gpio PR7 */
|
||||
vin-supply = <&sys_3v3_reg>;
|
||||
};
|
||||
|
||||
vdd_cam3_ldo_reg: regulator@8 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <8>;
|
||||
regulator-name = "vdd_cam3_ldo";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
enable-active-high;
|
||||
gpio = <&gpio 144 0>; /* gpio PS0 */
|
||||
vin-supply = <&sys_3v3_reg>;
|
||||
};
|
||||
|
||||
vdd_com_reg: regulator@9 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <9>;
|
||||
regulator-name = "vdd_com";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
enable-active-high;
|
||||
gpio = <&gpio 24 0>; /* gpio PD0 */
|
||||
vin-supply = <&sys_3v3_reg>;
|
||||
};
|
||||
|
||||
vdd_fuse_3v3_reg: regulator@10 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <10>;
|
||||
regulator-name = "vdd_fuse_3v3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
enable-active-high;
|
||||
gpio = <&gpio 94 0>; /* gpio PL6 */
|
||||
vin-supply = <&sys_3v3_reg>;
|
||||
};
|
||||
|
||||
vdd_pnl1_reg: regulator@11 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <11>;
|
||||
regulator-name = "vdd_pnl1";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
enable-active-high;
|
||||
gpio = <&gpio 92 0>; /* gpio PL4 */
|
||||
vin-supply = <&sys_3v3_reg>;
|
||||
};
|
||||
|
||||
vdd_vid_reg: regulator@12 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <12>;
|
||||
regulator-name = "vddio_vid";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
gpio = <&gpio 152 0>; /* GPIO PT0 */
|
||||
gpio-open-drain;
|
||||
vin-supply = <&vdd_5v0_reg>;
|
||||
};
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "nvidia,tegra-audio-wm8903-cardhu",
|
||||
"nvidia,tegra-audio-wm8903";
|
||||
nvidia,model = "NVIDIA Tegra Cardhu";
|
||||
|
||||
nvidia,audio-routing =
|
||||
"Headphone Jack", "HPOUTR",
|
||||
"Headphone Jack", "HPOUTL",
|
||||
"Int Spk", "ROP",
|
||||
"Int Spk", "RON",
|
||||
"Int Spk", "LOP",
|
||||
"Int Spk", "LON",
|
||||
"Mic Jack", "MICBIAS",
|
||||
"IN1L", "Mic Jack";
|
||||
|
||||
nvidia,i2s-controller = <&tegra_i2s1>;
|
||||
nvidia,audio-codec = <&wm8903>;
|
||||
|
||||
nvidia,spkr-en-gpios = <&wm8903 2 0>;
|
||||
nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
|
||||
};
|
||||
};
|
||||
@ -117,7 +117,7 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm {
|
||||
pwm: pwm {
|
||||
compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
|
||||
reg = <0x7000a000 0x100>;
|
||||
#pwm-cells = <2>;
|
||||
|
||||
56
arch/arm/boot/dts/tps65217.dtsi
Normal file
56
arch/arm/boot/dts/tps65217.dtsi
Normal file
@ -0,0 +1,56 @@
|
||||
/*
|
||||
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Integrated Power Management Chip
|
||||
* http://www.ti.com/lit/ds/symlink/tps65217.pdf
|
||||
*/
|
||||
|
||||
&tps {
|
||||
compatible = "ti,tps65217";
|
||||
|
||||
regulators {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
dcdc1_reg: regulator@0 {
|
||||
reg = <0>;
|
||||
regulator-compatible = "dcdc1";
|
||||
};
|
||||
|
||||
dcdc2_reg: regulator@1 {
|
||||
reg = <1>;
|
||||
regulator-compatible = "dcdc2";
|
||||
};
|
||||
|
||||
dcdc3_reg: regulator@2 {
|
||||
reg = <2>;
|
||||
regulator-compatible = "dcdc3";
|
||||
};
|
||||
|
||||
ldo1_reg: regulator@3 {
|
||||
reg = <3>;
|
||||
regulator-compatible = "ldo1";
|
||||
};
|
||||
|
||||
ldo2_reg: regulator@4 {
|
||||
reg = <4>;
|
||||
regulator-compatible = "ldo2";
|
||||
};
|
||||
|
||||
ldo3_reg: regulator@5 {
|
||||
reg = <5>;
|
||||
regulator-compatible = "ldo3";
|
||||
};
|
||||
|
||||
ldo4_reg: regulator@6 {
|
||||
reg = <6>;
|
||||
regulator-compatible = "ldo4";
|
||||
};
|
||||
};
|
||||
};
|
||||
86
arch/arm/boot/dts/tps65910.dtsi
Normal file
86
arch/arm/boot/dts/tps65910.dtsi
Normal file
@ -0,0 +1,86 @@
|
||||
/*
|
||||
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Integrated Power Management Chip
|
||||
* http://www.ti.com/lit/ds/symlink/tps65910.pdf
|
||||
*/
|
||||
|
||||
&tps {
|
||||
compatible = "ti,tps65910";
|
||||
|
||||
regulators {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
vrtc_reg: regulator@0 {
|
||||
reg = <0>;
|
||||
regulator-compatible = "vrtc";
|
||||
};
|
||||
|
||||
vio_reg: regulator@1 {
|
||||
reg = <1>;
|
||||
regulator-compatible = "vio";
|
||||
};
|
||||
|
||||
vdd1_reg: regulator@2 {
|
||||
reg = <2>;
|
||||
regulator-compatible = "vdd1";
|
||||
};
|
||||
|
||||
vdd2_reg: regulator@3 {
|
||||
reg = <3>;
|
||||
regulator-compatible = "vdd2";
|
||||
};
|
||||
|
||||
vdd3_reg: regulator@4 {
|
||||
reg = <4>;
|
||||
regulator-compatible = "vdd3";
|
||||
};
|
||||
|
||||
vdig1_reg: regulator@5 {
|
||||
reg = <5>;
|
||||
regulator-compatible = "vdig1";
|
||||
};
|
||||
|
||||
vdig2_reg: regulator@6 {
|
||||
reg = <6>;
|
||||
regulator-compatible = "vdig2";
|
||||
};
|
||||
|
||||
vpll_reg: regulator@7 {
|
||||
reg = <7>;
|
||||
regulator-compatible = "vpll";
|
||||
};
|
||||
|
||||
vdac_reg: regulator@8 {
|
||||
reg = <8>;
|
||||
regulator-compatible = "vdac";
|
||||
};
|
||||
|
||||
vaux1_reg: regulator@9 {
|
||||
reg = <9>;
|
||||
regulator-compatible = "vaux1";
|
||||
};
|
||||
|
||||
vaux2_reg: regulator@10 {
|
||||
reg = <10>;
|
||||
regulator-compatible = "vaux2";
|
||||
};
|
||||
|
||||
vaux33_reg: regulator@11 {
|
||||
reg = <11>;
|
||||
regulator-compatible = "vaux33";
|
||||
};
|
||||
|
||||
vmmc_reg: regulator@12 {
|
||||
reg = <12>;
|
||||
regulator-compatible = "vmmc";
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -19,19 +19,19 @@
|
||||
interrupts = <11>;
|
||||
};
|
||||
|
||||
vdac: regulator@0 {
|
||||
vdac: regulator-vdac {
|
||||
compatible = "ti,twl4030-vdac";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
vpll2: regulator@1 {
|
||||
vpll2: regulator-vpll2 {
|
||||
compatible = "ti,twl4030-vpll2";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
vmmc1: regulator@2 {
|
||||
vmmc1: regulator-vmmc1 {
|
||||
compatible = "ti,twl4030-vmmc1";
|
||||
regulator-min-microvolt = <1850000>;
|
||||
regulator-max-microvolt = <3150000>;
|
||||
|
||||
@ -20,70 +20,70 @@
|
||||
interrupts = <11>;
|
||||
};
|
||||
|
||||
vaux1: regulator@0 {
|
||||
vaux1: regulator-vaux1 {
|
||||
compatible = "ti,twl6030-vaux1";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
};
|
||||
|
||||
vaux2: regulator@1 {
|
||||
vaux2: regulator-vaux2 {
|
||||
compatible = "ti,twl6030-vaux2";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
};
|
||||
|
||||
vaux3: regulator@2 {
|
||||
vaux3: regulator-vaux3 {
|
||||
compatible = "ti,twl6030-vaux3";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
};
|
||||
|
||||
vmmc: regulator@3 {
|
||||
vmmc: regulator-vmmc {
|
||||
compatible = "ti,twl6030-vmmc";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
};
|
||||
|
||||
vpp: regulator@4 {
|
||||
vpp: regulator-vpp {
|
||||
compatible = "ti,twl6030-vpp";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <2500000>;
|
||||
};
|
||||
|
||||
vusim: regulator@5 {
|
||||
vusim: regulator-vusim {
|
||||
compatible = "ti,twl6030-vusim";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <2900000>;
|
||||
};
|
||||
|
||||
vdac: regulator@6 {
|
||||
vdac: regulator-vdac {
|
||||
compatible = "ti,twl6030-vdac";
|
||||
};
|
||||
|
||||
vana: regulator@7 {
|
||||
vana: regulator-vana {
|
||||
compatible = "ti,twl6030-vana";
|
||||
};
|
||||
|
||||
vcxio: regulator@8 {
|
||||
vcxio: regulator-vcxio {
|
||||
compatible = "ti,twl6030-vcxio";
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vusb: regulator@9 {
|
||||
vusb: regulator-vusb {
|
||||
compatible = "ti,twl6030-vusb";
|
||||
};
|
||||
|
||||
v1v8: regulator@10 {
|
||||
v1v8: regulator-v1v8 {
|
||||
compatible = "ti,twl6030-v1v8";
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
v2v1: regulator@11 {
|
||||
v2v1: regulator-v2v1 {
|
||||
compatible = "ti,twl6030-v2v1";
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
clk32kg: regulator@12 {
|
||||
clk32kg: regulator-clk32kg {
|
||||
compatible = "ti,twl6030-clk32kg";
|
||||
};
|
||||
};
|
||||
|
||||
@ -32,9 +32,7 @@ CONFIG_MACH_VPR200=y
|
||||
CONFIG_MACH_IMX51_DT=y
|
||||
CONFIG_MACH_MX51_3DS=y
|
||||
CONFIG_MACH_EUKREA_CPUIMX51SD=y
|
||||
CONFIG_MACH_MX51_EFIKAMX=y
|
||||
CONFIG_MACH_MX51_EFIKASB=y
|
||||
CONFIG_MACH_IMX53_DT=y
|
||||
CONFIG_SOC_IMX53=y
|
||||
CONFIG_SOC_IMX6Q=y
|
||||
CONFIG_MXC_PWM=y
|
||||
CONFIG_SMP=y
|
||||
|
||||
@ -23,12 +23,6 @@ CONFIG_BLK_DEV_INTEGRITY=y
|
||||
# CONFIG_IOSCHED_CFQ is not set
|
||||
CONFIG_ARCH_MXS=y
|
||||
CONFIG_MACH_MXS_DT=y
|
||||
CONFIG_MACH_MX23EVK=y
|
||||
CONFIG_MACH_MX28EVK=y
|
||||
CONFIG_MACH_STMP378X_DEVB=y
|
||||
CONFIG_MACH_TX28=y
|
||||
CONFIG_MACH_M28EVK=y
|
||||
CONFIG_MACH_APX4DEVKIT=y
|
||||
# CONFIG_ARM_THUMB is not set
|
||||
CONFIG_NO_HZ=y
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
|
||||
@ -123,6 +123,7 @@ CONFIG_HW_RANDOM=y
|
||||
CONFIG_I2C_CHARDEV=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_SPI_OMAP24XX=y
|
||||
CONFIG_PINCTRL_SINGLE=y
|
||||
CONFIG_DEBUG_GPIO=y
|
||||
CONFIG_GPIO_SYSFS=y
|
||||
CONFIG_GPIO_TWL4030=y
|
||||
|
||||
@ -8,4 +8,7 @@
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
extern void __init tauros2_init(void);
|
||||
#define CACHE_TAUROS2_PREFETCH_ON (1 << 0)
|
||||
#define CACHE_TAUROS2_LINEFILL_BURST8 (1 << 1)
|
||||
|
||||
extern void __init tauros2_init(unsigned int features);
|
||||
|
||||
@ -279,7 +279,7 @@ void __init dove_init(void)
|
||||
printk(KERN_INFO "TCLK = %dMHz\n", (get_tclk() + 499999) / 1000000);
|
||||
|
||||
#ifdef CONFIG_CACHE_TAUROS2
|
||||
tauros2_init();
|
||||
tauros2_init(0);
|
||||
#endif
|
||||
dove_setup_cpu_mbus();
|
||||
|
||||
|
||||
@ -101,13 +101,8 @@ config SOC_IMX51
|
||||
select SOC_IMX5
|
||||
select ARCH_MX5
|
||||
select ARCH_MX51
|
||||
|
||||
config SOC_IMX53
|
||||
bool
|
||||
select SOC_IMX5
|
||||
select ARCH_MX5
|
||||
select ARCH_MX53
|
||||
select HAVE_CAN_FLEXCAN if CAN
|
||||
select PINCTRL
|
||||
select PINCTRL_IMX51
|
||||
|
||||
if ARCH_IMX_V4_V5
|
||||
|
||||
@ -561,7 +556,6 @@ config MACH_BUG
|
||||
config MACH_IMX31_DT
|
||||
bool "Support i.MX31 platforms from device tree"
|
||||
select SOC_IMX31
|
||||
select USE_OF
|
||||
help
|
||||
Include support for Freescale i.MX31 based platforms
|
||||
using the device tree for discovery.
|
||||
@ -737,95 +731,19 @@ config MACH_EUKREA_MBIMXSD51_BASEBOARD
|
||||
|
||||
endchoice
|
||||
|
||||
config MX51_EFIKA_COMMON
|
||||
bool
|
||||
select SOC_IMX51
|
||||
select IMX_HAVE_PLATFORM_IMX_UART
|
||||
select IMX_HAVE_PLATFORM_MXC_EHCI
|
||||
select IMX_HAVE_PLATFORM_PATA_IMX
|
||||
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
|
||||
select IMX_HAVE_PLATFORM_SPI_IMX
|
||||
select MXC_ULPI if USB_ULPI
|
||||
comment "Device tree only"
|
||||
|
||||
config SOC_IMX53
|
||||
bool "i.MX53 support"
|
||||
select SOC_IMX5
|
||||
select ARCH_MX5
|
||||
select ARCH_MX53
|
||||
select HAVE_CAN_FLEXCAN if CAN
|
||||
select PINCTRL
|
||||
select PINCTRL_IMX53
|
||||
|
||||
config MACH_MX51_EFIKAMX
|
||||
bool "Support MX51 Genesi Efika MX nettop"
|
||||
select LEDS_GPIO_REGISTER
|
||||
select MX51_EFIKA_COMMON
|
||||
help
|
||||
Include support for Genesi Efika MX nettop. This includes specific
|
||||
configurations for the board and its peripherals.
|
||||
|
||||
config MACH_MX51_EFIKASB
|
||||
bool "Support MX51 Genesi Efika Smartbook"
|
||||
select LEDS_GPIO_REGISTER
|
||||
select MX51_EFIKA_COMMON
|
||||
help
|
||||
Include support for Genesi Efika Smartbook. This includes specific
|
||||
configurations for the board and its peripherals.
|
||||
|
||||
comment "i.MX53 machines:"
|
||||
|
||||
config MACH_IMX53_DT
|
||||
bool "Support i.MX53 platforms from device tree"
|
||||
select SOC_IMX53
|
||||
select MACH_MX53_ARD
|
||||
select MACH_MX53_EVK
|
||||
select MACH_MX53_LOCO
|
||||
select MACH_MX53_SMD
|
||||
help
|
||||
Include support for Freescale i.MX53 based platforms
|
||||
using the device tree for discovery
|
||||
|
||||
config MACH_MX53_EVK
|
||||
bool "Support MX53 EVK platforms"
|
||||
select SOC_IMX53
|
||||
select IMX_HAVE_PLATFORM_IMX2_WDT
|
||||
select IMX_HAVE_PLATFORM_IMX_UART
|
||||
select IMX_HAVE_PLATFORM_IMX_I2C
|
||||
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
|
||||
select IMX_HAVE_PLATFORM_SPI_IMX
|
||||
select LEDS_GPIO_REGISTER
|
||||
help
|
||||
Include support for MX53 EVK platform. This includes specific
|
||||
configurations for the board and its peripherals.
|
||||
|
||||
config MACH_MX53_SMD
|
||||
bool "Support MX53 SMD platforms"
|
||||
select SOC_IMX53
|
||||
select IMX_HAVE_PLATFORM_IMX2_WDT
|
||||
select IMX_HAVE_PLATFORM_IMX_I2C
|
||||
select IMX_HAVE_PLATFORM_IMX_UART
|
||||
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
|
||||
help
|
||||
Include support for MX53 SMD platform. This includes specific
|
||||
configurations for the board and its peripherals.
|
||||
|
||||
config MACH_MX53_LOCO
|
||||
bool "Support MX53 LOCO platforms"
|
||||
select SOC_IMX53
|
||||
select IMX_HAVE_PLATFORM_IMX2_WDT
|
||||
select IMX_HAVE_PLATFORM_IMX_I2C
|
||||
select IMX_HAVE_PLATFORM_IMX_UART
|
||||
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
|
||||
select IMX_HAVE_PLATFORM_GPIO_KEYS
|
||||
select LEDS_GPIO_REGISTER
|
||||
help
|
||||
Include support for MX53 LOCO platform. This includes specific
|
||||
configurations for the board and its peripherals.
|
||||
|
||||
config MACH_MX53_ARD
|
||||
bool "Support MX53 ARD platforms"
|
||||
select SOC_IMX53
|
||||
select IMX_HAVE_PLATFORM_IMX2_WDT
|
||||
select IMX_HAVE_PLATFORM_IMX_I2C
|
||||
select IMX_HAVE_PLATFORM_IMX_UART
|
||||
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
|
||||
select IMX_HAVE_PLATFORM_GPIO_KEYS
|
||||
help
|
||||
Include support for MX53 ARD platform. This includes specific
|
||||
configurations for the board and its peripherals.
|
||||
|
||||
comment "i.MX6 family:"
|
||||
This enables support for Freescale i.MX53 processor.
|
||||
|
||||
config SOC_IMX6Q
|
||||
bool "i.MX6 Quad support"
|
||||
|
||||
@ -83,16 +83,9 @@ endif
|
||||
# i.MX5 based machines
|
||||
obj-$(CONFIG_MACH_MX51_BABBAGE) += mach-mx51_babbage.o
|
||||
obj-$(CONFIG_MACH_MX51_3DS) += mach-mx51_3ds.o
|
||||
obj-$(CONFIG_MACH_MX53_EVK) += mach-mx53_evk.o
|
||||
obj-$(CONFIG_MACH_MX53_SMD) += mach-mx53_smd.o
|
||||
obj-$(CONFIG_MACH_MX53_LOCO) += mach-mx53_loco.o
|
||||
obj-$(CONFIG_MACH_MX53_ARD) += mach-mx53_ard.o
|
||||
obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += mach-cpuimx51sd.o
|
||||
obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd51-baseboard.o
|
||||
obj-$(CONFIG_MX51_EFIKA_COMMON) += mx51_efika.o
|
||||
obj-$(CONFIG_MACH_MX51_EFIKAMX) += mach-mx51_efikamx.o
|
||||
obj-$(CONFIG_MACH_MX51_EFIKASB) += mach-mx51_efikasb.o
|
||||
obj-$(CONFIG_MACH_MX50_RDP) += mach-mx50_rdp.o
|
||||
|
||||
obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o
|
||||
obj-$(CONFIG_MACH_IMX53_DT) += imx53-dt.o
|
||||
obj-$(CONFIG_SOC_IMX53) += mach-imx53.o
|
||||
|
||||
@ -39,8 +39,12 @@ params_phys-$(CONFIG_SOC_IMX6Q) := 0x10000100
|
||||
initrd_phys-$(CONFIG_SOC_IMX6Q) := 0x10800000
|
||||
|
||||
dtb-$(CONFIG_MACH_IMX51_DT) += imx51-babbage.dtb
|
||||
dtb-$(CONFIG_MACH_IMX53_DT) += imx53-ard.dtb imx53-evk.dtb \
|
||||
imx53-qsb.dtb imx53-smd.dtb
|
||||
|
||||
dtb-$(CONFIG_SOC_IMX53) += imx53-ard.dtb \
|
||||
imx53-evk.dtb \
|
||||
imx53-qsb.dtb \
|
||||
imx53-smd.dtb \
|
||||
|
||||
dtb-$(CONFIG_SOC_IMX6Q) += imx6q-arm2.dtb \
|
||||
imx6q-sabrelite.dtb \
|
||||
imx6q-sabresd.dtb \
|
||||
|
||||
@ -157,6 +157,7 @@ enum mx6q_clks {
|
||||
};
|
||||
|
||||
static struct clk *clk[clk_max];
|
||||
static struct clk_onecell_data clk_data;
|
||||
|
||||
static enum mx6q_clks const clks_init_on[] __initconst = {
|
||||
mmdc_ch0_axi, rom,
|
||||
@ -394,52 +395,24 @@ int __init mx6q_clocks_init(void)
|
||||
pr_err("i.MX6q clk %d: register failed with %ld\n",
|
||||
i, PTR_ERR(clk[i]));
|
||||
|
||||
clk_data.clks = clk;
|
||||
clk_data.clk_num = ARRAY_SIZE(clk);
|
||||
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
|
||||
|
||||
clk_register_clkdev(clk[gpt_ipg], "ipg", "imx-gpt.0");
|
||||
clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
|
||||
clk_register_clkdev(clk[twd], NULL, "smp_twd");
|
||||
clk_register_clkdev(clk[apbh_dma], NULL, "110000.dma-apbh");
|
||||
clk_register_clkdev(clk[per1_bch], "per1_bch", "112000.gpmi-nand");
|
||||
clk_register_clkdev(clk[gpmi_bch_apb], "gpmi_bch_apb", "112000.gpmi-nand");
|
||||
clk_register_clkdev(clk[gpmi_bch], "gpmi_bch", "112000.gpmi-nand");
|
||||
clk_register_clkdev(clk[gpmi_apb], "gpmi_apb", "112000.gpmi-nand");
|
||||
clk_register_clkdev(clk[gpmi_io], "gpmi_io", "112000.gpmi-nand");
|
||||
clk_register_clkdev(clk[usboh3], NULL, "2184000.usb");
|
||||
clk_register_clkdev(clk[usboh3], NULL, "2184200.usb");
|
||||
clk_register_clkdev(clk[usboh3], NULL, "2184400.usb");
|
||||
clk_register_clkdev(clk[usboh3], NULL, "2184600.usb");
|
||||
clk_register_clkdev(clk[usbphy1], NULL, "20c9000.usbphy");
|
||||
clk_register_clkdev(clk[usbphy2], NULL, "20ca000.usbphy");
|
||||
clk_register_clkdev(clk[uart_serial], "per", "2020000.serial");
|
||||
clk_register_clkdev(clk[uart_ipg], "ipg", "2020000.serial");
|
||||
clk_register_clkdev(clk[uart_serial], "per", "21e8000.serial");
|
||||
clk_register_clkdev(clk[uart_ipg], "ipg", "21e8000.serial");
|
||||
clk_register_clkdev(clk[uart_serial], "per", "21ec000.serial");
|
||||
clk_register_clkdev(clk[uart_ipg], "ipg", "21ec000.serial");
|
||||
clk_register_clkdev(clk[uart_serial], "per", "21f0000.serial");
|
||||
clk_register_clkdev(clk[uart_ipg], "ipg", "21f0000.serial");
|
||||
clk_register_clkdev(clk[uart_serial], "per", "21f4000.serial");
|
||||
clk_register_clkdev(clk[uart_ipg], "ipg", "21f4000.serial");
|
||||
clk_register_clkdev(clk[enet], NULL, "2188000.ethernet");
|
||||
clk_register_clkdev(clk[usdhc1], NULL, "2190000.usdhc");
|
||||
clk_register_clkdev(clk[usdhc2], NULL, "2194000.usdhc");
|
||||
clk_register_clkdev(clk[usdhc3], NULL, "2198000.usdhc");
|
||||
clk_register_clkdev(clk[usdhc4], NULL, "219c000.usdhc");
|
||||
clk_register_clkdev(clk[i2c1], NULL, "21a0000.i2c");
|
||||
clk_register_clkdev(clk[i2c2], NULL, "21a4000.i2c");
|
||||
clk_register_clkdev(clk[i2c3], NULL, "21a8000.i2c");
|
||||
clk_register_clkdev(clk[ecspi1], NULL, "2008000.ecspi");
|
||||
clk_register_clkdev(clk[ecspi2], NULL, "200c000.ecspi");
|
||||
clk_register_clkdev(clk[ecspi3], NULL, "2010000.ecspi");
|
||||
clk_register_clkdev(clk[ecspi4], NULL, "2014000.ecspi");
|
||||
clk_register_clkdev(clk[ecspi5], NULL, "2018000.ecspi");
|
||||
clk_register_clkdev(clk[sdma], NULL, "20ec000.sdma");
|
||||
clk_register_clkdev(clk[dummy], NULL, "20bc000.wdog");
|
||||
clk_register_clkdev(clk[dummy], NULL, "20c0000.wdog");
|
||||
clk_register_clkdev(clk[ssi1_ipg], NULL, "2028000.ssi");
|
||||
clk_register_clkdev(clk[cko1_sel], "cko1_sel", NULL);
|
||||
clk_register_clkdev(clk[ahb], "ahb", NULL);
|
||||
clk_register_clkdev(clk[cko1], "cko1", NULL);
|
||||
|
||||
/*
|
||||
* The gpmi needs 100MHz frequency in the EDO/Sync mode,
|
||||
* We can not get the 100MHz from the pll2_pfd0_352m.
|
||||
* So choose pll2_pfd2_396m as enfc_sel's parent.
|
||||
*/
|
||||
clk_set_parent(clk[enfc_sel], clk[pll2_pfd2_396m]);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
|
||||
clk_prepare_enable(clk[clks_init_on[i]]);
|
||||
|
||||
|
||||
@ -1,48 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2010 Yong Shen. <Yong.Shen@linaro.org>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it under
|
||||
* the terms of the GNU General Public License version 2 as published by the
|
||||
* Free Software Foundation.
|
||||
*/
|
||||
#include <mach/mx53.h>
|
||||
#include <mach/devices-common.h>
|
||||
|
||||
extern const struct imx_fec_data imx53_fec_data;
|
||||
#define imx53_add_fec(pdata) \
|
||||
imx_add_fec(&imx53_fec_data, pdata)
|
||||
|
||||
extern const struct imx_imx_uart_1irq_data imx53_imx_uart_data[];
|
||||
#define imx53_add_imx_uart(id, pdata) \
|
||||
imx_add_imx_uart_1irq(&imx53_imx_uart_data[id], pdata)
|
||||
|
||||
|
||||
extern const struct imx_imx_i2c_data imx53_imx_i2c_data[];
|
||||
#define imx53_add_imx_i2c(id, pdata) \
|
||||
imx_add_imx_i2c(&imx53_imx_i2c_data[id], pdata)
|
||||
|
||||
extern const struct imx_sdhci_esdhc_imx_data imx53_sdhci_esdhc_imx_data[];
|
||||
#define imx53_add_sdhci_esdhc_imx(id, pdata) \
|
||||
imx_add_sdhci_esdhc_imx(&imx53_sdhci_esdhc_imx_data[id], pdata)
|
||||
|
||||
extern const struct imx_spi_imx_data imx53_ecspi_data[];
|
||||
#define imx53_add_ecspi(id, pdata) \
|
||||
imx_add_spi_imx(&imx53_ecspi_data[id], pdata)
|
||||
|
||||
extern const struct imx_imx2_wdt_data imx53_imx2_wdt_data[];
|
||||
#define imx53_add_imx2_wdt(id) \
|
||||
imx_add_imx2_wdt(&imx53_imx2_wdt_data[id])
|
||||
|
||||
extern const struct imx_imx_ssi_data imx53_imx_ssi_data[];
|
||||
#define imx53_add_imx_ssi(id, pdata) \
|
||||
imx_add_imx_ssi(&imx53_imx_ssi_data[id], pdata)
|
||||
|
||||
extern const struct imx_imx_keypad_data imx53_imx_keypad_data;
|
||||
#define imx53_add_imx_keypad(pdata) \
|
||||
imx_add_imx_keypad(&imx53_imx_keypad_data, pdata)
|
||||
|
||||
extern const struct imx_pata_imx_data imx53_pata_imx_data;
|
||||
#define imx53_add_pata_imx() \
|
||||
imx_add_pata_imx(&imx53_pata_imx_data)
|
||||
|
||||
extern struct platform_device *__init imx53_add_ahci_imx(void);
|
||||
@ -1,10 +0,0 @@
|
||||
#ifndef _EFIKA_H
|
||||
#define _EFIKA_H
|
||||
|
||||
#define EFIKA_WLAN_EN IMX_GPIO_NR(2, 16)
|
||||
#define EFIKA_WLAN_RESET IMX_GPIO_NR(2, 10)
|
||||
#define EFIKA_USB_PHY_RESET IMX_GPIO_NR(2, 9)
|
||||
|
||||
void __init efika_board_common_init(void);
|
||||
|
||||
#endif
|
||||
@ -13,7 +13,6 @@
|
||||
#include <linux/irq.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/pinctrl/machine.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/time.h>
|
||||
#include <mach/common.h>
|
||||
@ -44,27 +43,8 @@ static const struct of_dev_auxdata imx51_auxdata_lookup[] __initconst = {
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static const struct of_device_id imx51_iomuxc_of_match[] __initconst = {
|
||||
{ .compatible = "fsl,imx51-iomuxc-babbage", .data = imx51_babbage_common_init, },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static void __init imx51_dt_init(void)
|
||||
{
|
||||
struct device_node *node;
|
||||
const struct of_device_id *of_id;
|
||||
void (*func)(void);
|
||||
|
||||
pinctrl_provide_dummies();
|
||||
|
||||
node = of_find_matching_node(NULL, imx51_iomuxc_of_match);
|
||||
if (node) {
|
||||
of_id = of_match_node(imx51_iomuxc_of_match, node);
|
||||
func = of_id->data;
|
||||
func();
|
||||
of_node_put(node);
|
||||
}
|
||||
|
||||
of_platform_populate(NULL, of_default_bus_match_table,
|
||||
imx51_auxdata_lookup, NULL);
|
||||
}
|
||||
@ -79,7 +59,6 @@ static struct sys_timer imx51_timer = {
|
||||
};
|
||||
|
||||
static const char *imx51_dt_board_compat[] __initdata = {
|
||||
"fsl,imx51-babbage",
|
||||
"fsl,imx51",
|
||||
NULL
|
||||
};
|
||||
|
||||
@ -17,7 +17,6 @@
|
||||
#include <linux/irq.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/pinctrl/machine.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/time.h>
|
||||
#include <mach/common.h>
|
||||
@ -51,14 +50,6 @@ static const struct of_dev_auxdata imx53_auxdata_lookup[] __initconst = {
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static const struct of_device_id imx53_iomuxc_of_match[] __initconst = {
|
||||
{ .compatible = "fsl,imx53-iomuxc-ard", .data = imx53_ard_common_init, },
|
||||
{ .compatible = "fsl,imx53-iomuxc-evk", .data = imx53_evk_common_init, },
|
||||
{ .compatible = "fsl,imx53-iomuxc-qsb", .data = imx53_qsb_common_init, },
|
||||
{ .compatible = "fsl,imx53-iomuxc-smd", .data = imx53_smd_common_init, },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static void __init imx53_qsb_init(void)
|
||||
{
|
||||
struct clk *clk;
|
||||
@ -74,20 +65,6 @@ static void __init imx53_qsb_init(void)
|
||||
|
||||
static void __init imx53_dt_init(void)
|
||||
{
|
||||
struct device_node *node;
|
||||
const struct of_device_id *of_id;
|
||||
void (*func)(void);
|
||||
|
||||
pinctrl_provide_dummies();
|
||||
|
||||
node = of_find_matching_node(NULL, imx53_iomuxc_of_match);
|
||||
if (node) {
|
||||
of_id = of_match_node(imx53_iomuxc_of_match, node);
|
||||
func = of_id->data;
|
||||
func();
|
||||
of_node_put(node);
|
||||
}
|
||||
|
||||
if (of_machine_is_compatible("fsl,imx53-qsb"))
|
||||
imx53_qsb_init();
|
||||
|
||||
@ -105,10 +82,6 @@ static struct sys_timer imx53_timer = {
|
||||
};
|
||||
|
||||
static const char *imx53_dt_board_compat[] __initdata = {
|
||||
"fsl,imx53-ard",
|
||||
"fsl,imx53-evk",
|
||||
"fsl,imx53-qsb",
|
||||
"fsl,imx53-smd",
|
||||
"fsl,imx53",
|
||||
NULL
|
||||
};
|
||||
@ -22,7 +22,6 @@
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/pinctrl/machine.h>
|
||||
#include <linux/phy.h>
|
||||
#include <linux/micrel_phy.h>
|
||||
#include <linux/mfd/anatop.h>
|
||||
@ -100,7 +99,6 @@ static void __init imx6q_sabrelite_cko1_setup(void)
|
||||
clk_set_parent(cko1_sel, ahb);
|
||||
rate = clk_round_rate(cko1, 16000000);
|
||||
clk_set_rate(cko1, rate);
|
||||
clk_register_clkdev(cko1, NULL, "0-000a");
|
||||
put_clk:
|
||||
if (!IS_ERR(cko1_sel))
|
||||
clk_put(cko1_sel);
|
||||
@ -159,12 +157,6 @@ static void __init imx6q_usb_init(void)
|
||||
|
||||
static void __init imx6q_init_machine(void)
|
||||
{
|
||||
/*
|
||||
* This should be removed when all imx6q boards have pinctrl
|
||||
* states for devices defined in device tree.
|
||||
*/
|
||||
pinctrl_provide_dummies();
|
||||
|
||||
if (of_machine_is_compatible("fsl,imx6q-sabrelite"))
|
||||
imx6q_sabrelite_init();
|
||||
|
||||
@ -218,9 +210,6 @@ static struct sys_timer imx6q_timer = {
|
||||
};
|
||||
|
||||
static const char *imx6q_dt_compat[] __initdata = {
|
||||
"fsl,imx6q-arm2",
|
||||
"fsl,imx6q-sabrelite",
|
||||
"fsl,imx6q-sabresd",
|
||||
"fsl,imx6q",
|
||||
NULL,
|
||||
};
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user