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ARM: DRA7: Provide proper IO map table
DRA7 uses OMAP5 IO table at the moment. This is purely spurious since
the OMAP5 and DRA7 register maps are different in many aspects.
AM57xx/DRA7 TRM Reference: http://www.ti.com/lit/ug/spruhz6/spruhz6.pdf
NOTE: Most of the drivers are already doing ioremap, so, there should'nt
be any functional improvement involved here, other than making the
initial iotable more accurate.
Fixes: a3a9384a11 ("ARM: DRA7: Reuse io tables and add a new .init_early")
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
Nishanth Menon
Tony Lindgren
parent
d1dabab284
commit
ea827ad5ff
@ -297,7 +297,7 @@ static const char *const dra74x_boards_compat[] __initconst = {
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DT_MACHINE_START(DRA74X_DT, "Generic DRA74X (Flattened Device Tree)")
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.reserve = omap_reserve,
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.smp = smp_ops(omap4_smp_ops),
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.map_io = omap5_map_io,
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.map_io = dra7xx_map_io,
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.init_early = dra7xx_init_early,
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.init_late = dra7xx_init_late,
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.init_irq = omap_gic_of_init,
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@ -316,7 +316,7 @@ static const char *const dra72x_boards_compat[] __initconst = {
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DT_MACHINE_START(DRA72X_DT, "Generic DRA72X (Flattened Device Tree)")
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.reserve = omap_reserve,
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.map_io = omap5_map_io,
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.map_io = dra7xx_map_io,
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.init_early = dra7xx_init_early,
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.init_late = dra7xx_init_late,
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.init_irq = omap_gic_of_init,
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@ -198,6 +198,7 @@ void __init omap3_map_io(void);
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void __init am33xx_map_io(void);
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void __init omap4_map_io(void);
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void __init omap5_map_io(void);
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void __init dra7xx_map_io(void);
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void __init ti81xx_map_io(void);
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/**
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@ -236,7 +236,7 @@ static struct map_desc omap44xx_io_desc[] __initdata = {
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};
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#endif
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#if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
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#ifdef CONFIG_SOC_OMAP5
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static struct map_desc omap54xx_io_desc[] __initdata = {
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{
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.virtual = L3_54XX_VIRT,
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@ -265,6 +265,53 @@ static struct map_desc omap54xx_io_desc[] __initdata = {
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};
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#endif
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#ifdef CONFIG_SOC_DRA7XX
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static struct map_desc dra7xx_io_desc[] __initdata = {
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{
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.virtual = L4_CFG_MPU_DRA7XX_VIRT,
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.pfn = __phys_to_pfn(L4_CFG_MPU_DRA7XX_PHYS),
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.length = L4_CFG_MPU_DRA7XX_SIZE,
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.type = MT_DEVICE,
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},
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{
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.virtual = L3_MAIN_SN_DRA7XX_VIRT,
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.pfn = __phys_to_pfn(L3_MAIN_SN_DRA7XX_PHYS),
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.length = L3_MAIN_SN_DRA7XX_SIZE,
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.type = MT_DEVICE,
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},
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{
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.virtual = L4_PER1_DRA7XX_VIRT,
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.pfn = __phys_to_pfn(L4_PER1_DRA7XX_PHYS),
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.length = L4_PER1_DRA7XX_SIZE,
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.type = MT_DEVICE,
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},
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{
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.virtual = L4_PER2_DRA7XX_VIRT,
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.pfn = __phys_to_pfn(L4_PER2_DRA7XX_PHYS),
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.length = L4_PER2_DRA7XX_SIZE,
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.type = MT_DEVICE,
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},
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{
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.virtual = L4_PER3_DRA7XX_VIRT,
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.pfn = __phys_to_pfn(L4_PER3_DRA7XX_PHYS),
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.length = L4_PER3_DRA7XX_SIZE,
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.type = MT_DEVICE,
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},
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{
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.virtual = L4_CFG_DRA7XX_VIRT,
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.pfn = __phys_to_pfn(L4_CFG_DRA7XX_PHYS),
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.length = L4_CFG_DRA7XX_SIZE,
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.type = MT_DEVICE,
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},
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{
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.virtual = L4_WKUP_DRA7XX_VIRT,
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.pfn = __phys_to_pfn(L4_WKUP_DRA7XX_PHYS),
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.length = L4_WKUP_DRA7XX_SIZE,
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.type = MT_DEVICE,
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},
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};
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#endif
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#ifdef CONFIG_SOC_OMAP2420
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void __init omap242x_map_io(void)
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{
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@ -309,12 +356,19 @@ void __init omap4_map_io(void)
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}
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#endif
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#if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
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#ifdef CONFIG_SOC_OMAP5
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void __init omap5_map_io(void)
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{
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iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
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}
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#endif
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#ifdef CONFIG_SOC_DRA7XX
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void __init dra7xx_map_io(void)
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{
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iotable_init(dra7xx_io_desc, ARRAY_SIZE(dra7xx_io_desc));
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}
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#endif
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/*
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* omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
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*
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@ -194,3 +194,66 @@
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#define L4_PER_54XX_PHYS L4_PER_54XX_BASE /* 0x48000000 --> 0xfa000000 */
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#define L4_PER_54XX_VIRT (L4_PER_54XX_PHYS + OMAP2_L4_IO_OFFSET)
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#define L4_PER_54XX_SIZE SZ_4M
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/*
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* ----------------------------------------------------------------------------
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* DRA7xx specific IO mapping
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* ----------------------------------------------------------------------------
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*/
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/*
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* L3_MAIN_SN_DRA7XX_PHYS 0x44000000 --> 0xf8000000
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* The overall space is 24MiB (0x4400_0000<->0x457F_FFFF), but mapping
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* everything is just inefficient, since, there are too many address holes.
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*/
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#define L3_MAIN_SN_DRA7XX_PHYS L3_MAIN_SN_DRA7XX_BASE
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#define L3_MAIN_SN_DRA7XX_VIRT (L3_MAIN_SN_DRA7XX_PHYS + OMAP4_L3_IO_OFFSET)
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#define L3_MAIN_SN_DRA7XX_SIZE SZ_1M
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/*
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* L4_PER1_DRA7XX_PHYS (0x4800_000<>0x480D_2FFF) -> 0.82MiB (alloc 1MiB)
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* (0x48000000<->0x48100000) <=> (0xFA000000<->0xFA100000)
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*/
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#define L4_PER1_DRA7XX_PHYS L4_PER1_DRA7XX_BASE
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#define L4_PER1_DRA7XX_VIRT (L4_PER1_DRA7XX_PHYS + OMAP2_L4_IO_OFFSET)
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#define L4_PER1_DRA7XX_SIZE SZ_1M
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/*
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* L4_CFG_MPU_DRA7XX_PHYS (0x48210000<>0x482A_F2FF) -> 0.62MiB (alloc 1MiB)
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* (0x48210000<->0x48310000) <=> (0xFA210000<->0xFA310000)
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* NOTE: This is a bit of an orphan memory map sitting isolated in TRM
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*/
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#define L4_CFG_MPU_DRA7XX_PHYS L4_CFG_MPU_DRA7XX_BASE
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#define L4_CFG_MPU_DRA7XX_VIRT (L4_CFG_MPU_DRA7XX_PHYS + OMAP2_L4_IO_OFFSET)
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#define L4_CFG_MPU_DRA7XX_SIZE SZ_1M
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/*
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* L4_PER2_DRA7XX_PHYS (0x4840_0000<>0x4848_8FFF) -> .53MiB (alloc 1MiB)
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* (0x48400000<->0x48500000) <=> (0xFA400000<->0xFA500000)
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*/
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#define L4_PER2_DRA7XX_PHYS L4_PER2_DRA7XX_BASE
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#define L4_PER2_DRA7XX_VIRT (L4_PER2_DRA7XX_PHYS + OMAP2_L4_IO_OFFSET)
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#define L4_PER2_DRA7XX_SIZE SZ_1M
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/*
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* L4_PER3_DRA7XX_PHYS (0x4880_0000<>0x489E_0FFF) -> 1.87MiB (alloc 2MiB)
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* (0x48800000<->0x48A00000) <=> (0xFA800000<->0xFAA00000)
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*/
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#define L4_PER3_DRA7XX_PHYS L4_PER3_DRA7XX_BASE
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#define L4_PER3_DRA7XX_VIRT (L4_PER3_DRA7XX_PHYS + OMAP2_L4_IO_OFFSET)
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#define L4_PER3_DRA7XX_SIZE SZ_2M
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/*
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* L4_CFG_DRA7XX_PHYS (0x4A00_0000<>0x4A22_BFFF) ->2.17MiB (alloc 3MiB)?
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* (0x4A000000<->0x4A300000) <=> (0xFC000000<->0xFC300000)
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*/
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#define L4_CFG_DRA7XX_PHYS L4_CFG_DRA7XX_BASE
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#define L4_CFG_DRA7XX_VIRT (L4_CFG_DRA7XX_PHYS + OMAP2_L4_IO_OFFSET)
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#define L4_CFG_DRA7XX_SIZE (SZ_1M + SZ_2M)
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/*
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* L4_WKUP_DRA7XX_PHYS (0x4AE0_0000<>0x4AE3_EFFF) -> .24 mb (alloc 1MiB)?
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* (0x4AE00000<->4AF00000) <=> (0xFCE00000<->0xFCF00000)
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*/
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#define L4_WKUP_DRA7XX_PHYS L4_WKUP_DRA7XX_BASE
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#define L4_WKUP_DRA7XX_VIRT (L4_WKUP_DRA7XX_PHYS + OMAP2_L4_IO_OFFSET)
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#define L4_WKUP_DRA7XX_SIZE SZ_1M
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@ -30,6 +30,14 @@
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#define OMAP54XX_CTRL_BASE 0x4a002800
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#define OMAP54XX_SAR_RAM_BASE 0x4ae26000
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/* DRA7 specific base addresses */
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#define L3_MAIN_SN_DRA7XX_BASE 0x44000000
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#define L4_PER1_DRA7XX_BASE 0x48000000
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#define L4_CFG_MPU_DRA7XX_BASE 0x48210000
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#define L4_PER2_DRA7XX_BASE 0x48400000
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#define L4_PER3_DRA7XX_BASE 0x48800000
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#define L4_CFG_DRA7XX_BASE 0x4A000000
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#define L4_WKUP_DRA7XX_BASE 0x4ae00000
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#define DRA7XX_CM_CORE_AON_BASE 0x4a005000
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#define DRA7XX_CTRL_BASE 0x4a003400
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#define DRA7XX_TAP_BASE 0x4ae0c000
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