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drm/radeon: remove generic rptr/wptr functions (v2)
Fill in asic family specific versions rather than using the generic version. This lets us handle asic specific differences more easily. In this case, we disable sw swapping of the rtpr writeback value on r6xx+ since the hw does it for us. Fixes bogus rptr readback on BE systems. v2: remove missed cpu_to_le32(), add comments Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher
parent
e308b1d375
commit
ea31bf697d
@ -4015,15 +4015,43 @@ static int cik_cp_gfx_resume(struct radeon_device *rdev)
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return 0;
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}
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u32 cik_compute_ring_get_rptr(struct radeon_device *rdev,
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struct radeon_ring *ring)
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u32 cik_gfx_get_rptr(struct radeon_device *rdev,
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struct radeon_ring *ring)
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{
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u32 rptr;
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if (rdev->wb.enabled)
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rptr = rdev->wb.wb[ring->rptr_offs/4];
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else
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rptr = RREG32(CP_RB0_RPTR);
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return rptr;
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}
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u32 cik_gfx_get_wptr(struct radeon_device *rdev,
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struct radeon_ring *ring)
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{
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u32 wptr;
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wptr = RREG32(CP_RB0_WPTR);
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return wptr;
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}
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void cik_gfx_set_wptr(struct radeon_device *rdev,
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struct radeon_ring *ring)
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{
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WREG32(CP_RB0_WPTR, ring->wptr);
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(void)RREG32(CP_RB0_WPTR);
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}
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u32 cik_compute_get_rptr(struct radeon_device *rdev,
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struct radeon_ring *ring)
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{
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u32 rptr;
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if (rdev->wb.enabled) {
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rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]);
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rptr = rdev->wb.wb[ring->rptr_offs/4];
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} else {
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mutex_lock(&rdev->srbm_mutex);
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cik_srbm_select(rdev, ring->me, ring->pipe, ring->queue, 0);
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@ -4035,13 +4063,14 @@ u32 cik_compute_ring_get_rptr(struct radeon_device *rdev,
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return rptr;
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}
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u32 cik_compute_ring_get_wptr(struct radeon_device *rdev,
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struct radeon_ring *ring)
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u32 cik_compute_get_wptr(struct radeon_device *rdev,
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struct radeon_ring *ring)
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{
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u32 wptr;
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if (rdev->wb.enabled) {
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wptr = le32_to_cpu(rdev->wb.wb[ring->wptr_offs/4]);
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/* XXX check if swapping is necessary on BE */
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wptr = rdev->wb.wb[ring->wptr_offs/4];
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} else {
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mutex_lock(&rdev->srbm_mutex);
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cik_srbm_select(rdev, ring->me, ring->pipe, ring->queue, 0);
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@ -4053,10 +4082,11 @@ u32 cik_compute_ring_get_wptr(struct radeon_device *rdev,
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return wptr;
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}
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void cik_compute_ring_set_wptr(struct radeon_device *rdev,
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struct radeon_ring *ring)
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void cik_compute_set_wptr(struct radeon_device *rdev,
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struct radeon_ring *ring)
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{
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rdev->wb.wb[ring->wptr_offs/4] = cpu_to_le32(ring->wptr);
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/* XXX check if swapping is necessary on BE */
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rdev->wb.wb[ring->wptr_offs/4] = ring->wptr;
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WDOORBELL32(ring->doorbell_index, ring->wptr);
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}
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@ -7606,7 +7636,6 @@ static int cik_startup(struct radeon_device *rdev)
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ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
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r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
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CP_RB0_RPTR, CP_RB0_WPTR,
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PACKET3(PACKET3_NOP, 0x3FFF));
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if (r)
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return r;
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@ -7615,7 +7644,6 @@ static int cik_startup(struct radeon_device *rdev)
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/* type-2 packets are deprecated on MEC, use type-3 instead */
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ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
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r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP1_RPTR_OFFSET,
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CP_HQD_PQ_RPTR, CP_HQD_PQ_WPTR,
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PACKET3(PACKET3_NOP, 0x3FFF));
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if (r)
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return r;
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@ -7627,7 +7655,6 @@ static int cik_startup(struct radeon_device *rdev)
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/* type-2 packets are deprecated on MEC, use type-3 instead */
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ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
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r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP2_RPTR_OFFSET,
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CP_HQD_PQ_RPTR, CP_HQD_PQ_WPTR,
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PACKET3(PACKET3_NOP, 0x3FFF));
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if (r)
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return r;
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@ -7639,16 +7666,12 @@ static int cik_startup(struct radeon_device *rdev)
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ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
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r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
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SDMA0_GFX_RB_RPTR + SDMA0_REGISTER_OFFSET,
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SDMA0_GFX_RB_WPTR + SDMA0_REGISTER_OFFSET,
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SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0));
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if (r)
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return r;
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ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
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r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET,
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SDMA0_GFX_RB_RPTR + SDMA1_REGISTER_OFFSET,
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SDMA0_GFX_RB_WPTR + SDMA1_REGISTER_OFFSET,
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SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0));
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if (r)
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return r;
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@ -7664,7 +7687,6 @@ static int cik_startup(struct radeon_device *rdev)
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ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
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if (ring->ring_size) {
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r = radeon_ring_init(rdev, ring, ring->ring_size, 0,
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UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR,
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RADEON_CP_PACKET2);
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if (!r)
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r = uvd_v1_0_init(rdev);
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@ -51,6 +51,75 @@ u32 cik_gpu_check_soft_reset(struct radeon_device *rdev);
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* buffers.
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*/
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/**
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* cik_sdma_get_rptr - get the current read pointer
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*
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* @rdev: radeon_device pointer
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* @ring: radeon ring pointer
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*
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* Get the current rptr from the hardware (CIK+).
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*/
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uint32_t cik_sdma_get_rptr(struct radeon_device *rdev,
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struct radeon_ring *ring)
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{
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u32 rptr, reg;
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if (rdev->wb.enabled) {
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rptr = rdev->wb.wb[ring->rptr_offs/4];
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} else {
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if (ring->idx == R600_RING_TYPE_DMA_INDEX)
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reg = SDMA0_GFX_RB_RPTR + SDMA0_REGISTER_OFFSET;
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else
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reg = SDMA0_GFX_RB_RPTR + SDMA1_REGISTER_OFFSET;
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rptr = RREG32(reg);
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}
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return (rptr & 0x3fffc) >> 2;
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}
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/**
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* cik_sdma_get_wptr - get the current write pointer
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*
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* @rdev: radeon_device pointer
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* @ring: radeon ring pointer
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*
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* Get the current wptr from the hardware (CIK+).
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*/
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uint32_t cik_sdma_get_wptr(struct radeon_device *rdev,
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struct radeon_ring *ring)
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{
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u32 reg;
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if (ring->idx == R600_RING_TYPE_DMA_INDEX)
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reg = SDMA0_GFX_RB_WPTR + SDMA0_REGISTER_OFFSET;
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else
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reg = SDMA0_GFX_RB_WPTR + SDMA1_REGISTER_OFFSET;
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return (RREG32(reg) & 0x3fffc) >> 2;
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}
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/**
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* cik_sdma_set_wptr - commit the write pointer
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*
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* @rdev: radeon_device pointer
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* @ring: radeon ring pointer
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*
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* Write the wptr back to the hardware (CIK+).
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*/
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void cik_sdma_set_wptr(struct radeon_device *rdev,
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struct radeon_ring *ring)
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{
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u32 reg;
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if (ring->idx == R600_RING_TYPE_DMA_INDEX)
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reg = SDMA0_GFX_RB_WPTR + SDMA0_REGISTER_OFFSET;
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else
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reg = SDMA0_GFX_RB_WPTR + SDMA1_REGISTER_OFFSET;
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WREG32(reg, (ring->wptr << 2) & 0x3fffc);
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}
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/**
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* cik_sdma_ring_ib_execute - Schedule an IB on the DMA engine
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*
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@ -5184,14 +5184,12 @@ static int evergreen_startup(struct radeon_device *rdev)
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ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
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r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
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R600_CP_RB_RPTR, R600_CP_RB_WPTR,
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RADEON_CP_PACKET2);
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if (r)
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return r;
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ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
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r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
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DMA_RB_RPTR, DMA_RB_WPTR,
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DMA_PACKET(DMA_PACKET_NOP, 0, 0));
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if (r)
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return r;
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@ -5209,7 +5207,6 @@ static int evergreen_startup(struct radeon_device *rdev)
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ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
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if (ring->ring_size) {
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r = radeon_ring_init(rdev, ring, ring->ring_size, 0,
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UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR,
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RADEON_CP_PACKET2);
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if (!r)
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r = uvd_v1_0_init(rdev);
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@ -1386,6 +1386,55 @@ static void cayman_cp_enable(struct radeon_device *rdev, bool enable)
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}
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}
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u32 cayman_gfx_get_rptr(struct radeon_device *rdev,
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struct radeon_ring *ring)
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{
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u32 rptr;
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if (rdev->wb.enabled)
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rptr = rdev->wb.wb[ring->rptr_offs/4];
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else {
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if (ring->idx == RADEON_RING_TYPE_GFX_INDEX)
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rptr = RREG32(CP_RB0_RPTR);
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else if (ring->idx == CAYMAN_RING_TYPE_CP1_INDEX)
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rptr = RREG32(CP_RB1_RPTR);
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else
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rptr = RREG32(CP_RB2_RPTR);
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}
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return rptr;
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}
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u32 cayman_gfx_get_wptr(struct radeon_device *rdev,
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struct radeon_ring *ring)
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{
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u32 wptr;
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if (ring->idx == RADEON_RING_TYPE_GFX_INDEX)
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wptr = RREG32(CP_RB0_WPTR);
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else if (ring->idx == CAYMAN_RING_TYPE_CP1_INDEX)
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wptr = RREG32(CP_RB1_WPTR);
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else
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wptr = RREG32(CP_RB2_WPTR);
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return wptr;
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}
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void cayman_gfx_set_wptr(struct radeon_device *rdev,
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struct radeon_ring *ring)
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{
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if (ring->idx == RADEON_RING_TYPE_GFX_INDEX) {
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WREG32(CP_RB0_WPTR, ring->wptr);
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(void)RREG32(CP_RB0_WPTR);
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} else if (ring->idx == CAYMAN_RING_TYPE_CP1_INDEX) {
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WREG32(CP_RB1_WPTR, ring->wptr);
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(void)RREG32(CP_RB1_WPTR);
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} else {
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WREG32(CP_RB2_WPTR, ring->wptr);
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(void)RREG32(CP_RB2_WPTR);
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}
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}
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static int cayman_cp_load_microcode(struct radeon_device *rdev)
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{
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const __be32 *fw_data;
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@ -1514,6 +1563,16 @@ static int cayman_cp_resume(struct radeon_device *rdev)
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CP_RB1_BASE,
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CP_RB2_BASE
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};
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static const unsigned cp_rb_rptr[] = {
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CP_RB0_RPTR,
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CP_RB1_RPTR,
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CP_RB2_RPTR
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};
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static const unsigned cp_rb_wptr[] = {
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CP_RB0_WPTR,
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CP_RB1_WPTR,
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CP_RB2_WPTR
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};
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struct radeon_ring *ring;
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int i, r;
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@ -1572,8 +1631,8 @@ static int cayman_cp_resume(struct radeon_device *rdev)
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WREG32_P(cp_rb_cntl[i], RB_RPTR_WR_ENA, ~RB_RPTR_WR_ENA);
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ring->rptr = ring->wptr = 0;
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WREG32(ring->rptr_reg, ring->rptr);
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WREG32(ring->wptr_reg, ring->wptr);
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WREG32(cp_rb_rptr[i], ring->rptr);
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WREG32(cp_rb_wptr[i], ring->wptr);
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mdelay(1);
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WREG32_P(cp_rb_cntl[i], 0, ~RB_RPTR_WR_ENA);
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@ -1953,23 +2012,18 @@ static int cayman_startup(struct radeon_device *rdev)
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evergreen_irq_set(rdev);
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r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
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CP_RB0_RPTR, CP_RB0_WPTR,
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RADEON_CP_PACKET2);
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if (r)
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return r;
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ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
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r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
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DMA_RB_RPTR + DMA0_REGISTER_OFFSET,
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DMA_RB_WPTR + DMA0_REGISTER_OFFSET,
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DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
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if (r)
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return r;
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ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
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r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET,
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DMA_RB_RPTR + DMA1_REGISTER_OFFSET,
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DMA_RB_WPTR + DMA1_REGISTER_OFFSET,
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DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
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if (r)
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return r;
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@ -1988,7 +2042,6 @@ static int cayman_startup(struct radeon_device *rdev)
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ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
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if (ring->ring_size) {
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r = radeon_ring_init(rdev, ring, ring->ring_size, 0,
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UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR,
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RADEON_CP_PACKET2);
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if (!r)
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r = uvd_v1_0_init(rdev);
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@ -42,6 +42,75 @@ u32 cayman_gpu_check_soft_reset(struct radeon_device *rdev);
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* Cayman and newer support two asynchronous DMA engines.
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*/
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/**
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* cayman_dma_get_rptr - get the current read pointer
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*
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* @rdev: radeon_device pointer
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* @ring: radeon ring pointer
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*
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* Get the current rptr from the hardware (cayman+).
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*/
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uint32_t cayman_dma_get_rptr(struct radeon_device *rdev,
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struct radeon_ring *ring)
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{
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u32 rptr, reg;
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if (rdev->wb.enabled) {
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rptr = rdev->wb.wb[ring->rptr_offs/4];
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} else {
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if (ring->idx == R600_RING_TYPE_DMA_INDEX)
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reg = DMA_RB_RPTR + DMA0_REGISTER_OFFSET;
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else
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reg = DMA_RB_RPTR + DMA1_REGISTER_OFFSET;
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rptr = RREG32(reg);
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}
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return (rptr & 0x3fffc) >> 2;
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}
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/**
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* cayman_dma_get_wptr - get the current write pointer
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*
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* @rdev: radeon_device pointer
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* @ring: radeon ring pointer
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*
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* Get the current wptr from the hardware (cayman+).
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*/
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uint32_t cayman_dma_get_wptr(struct radeon_device *rdev,
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struct radeon_ring *ring)
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{
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u32 reg;
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if (ring->idx == R600_RING_TYPE_DMA_INDEX)
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reg = DMA_RB_WPTR + DMA0_REGISTER_OFFSET;
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else
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reg = DMA_RB_WPTR + DMA1_REGISTER_OFFSET;
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return (RREG32(reg) & 0x3fffc) >> 2;
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}
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/**
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* cayman_dma_set_wptr - commit the write pointer
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*
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* @rdev: radeon_device pointer
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* @ring: radeon ring pointer
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*
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* Write the wptr back to the hardware (cayman+).
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*/
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void cayman_dma_set_wptr(struct radeon_device *rdev,
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struct radeon_ring *ring)
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{
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u32 reg;
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|
||||
if (ring->idx == R600_RING_TYPE_DMA_INDEX)
|
||||
reg = DMA_RB_WPTR + DMA0_REGISTER_OFFSET;
|
||||
else
|
||||
reg = DMA_RB_WPTR + DMA1_REGISTER_OFFSET;
|
||||
|
||||
WREG32(reg, (ring->wptr << 2) & 0x3fffc);
|
||||
}
|
||||
|
||||
/**
|
||||
* cayman_dma_ring_ib_execute - Schedule an IB on the DMA engine
|
||||
*
|
||||
|
||||
@ -1050,6 +1050,36 @@ static int r100_cp_init_microcode(struct radeon_device *rdev)
|
||||
return err;
|
||||
}
|
||||
|
||||
u32 r100_gfx_get_rptr(struct radeon_device *rdev,
|
||||
struct radeon_ring *ring)
|
||||
{
|
||||
u32 rptr;
|
||||
|
||||
if (rdev->wb.enabled)
|
||||
rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]);
|
||||
else
|
||||
rptr = RREG32(RADEON_CP_RB_RPTR);
|
||||
|
||||
return rptr;
|
||||
}
|
||||
|
||||
u32 r100_gfx_get_wptr(struct radeon_device *rdev,
|
||||
struct radeon_ring *ring)
|
||||
{
|
||||
u32 wptr;
|
||||
|
||||
wptr = RREG32(RADEON_CP_RB_WPTR);
|
||||
|
||||
return wptr;
|
||||
}
|
||||
|
||||
void r100_gfx_set_wptr(struct radeon_device *rdev,
|
||||
struct radeon_ring *ring)
|
||||
{
|
||||
WREG32(RADEON_CP_RB_WPTR, ring->wptr);
|
||||
(void)RREG32(RADEON_CP_RB_WPTR);
|
||||
}
|
||||
|
||||
static void r100_cp_load_microcode(struct radeon_device *rdev)
|
||||
{
|
||||
const __be32 *fw_data;
|
||||
@ -1102,7 +1132,6 @@ int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
|
||||
ring_size = (1 << (rb_bufsz + 1)) * 4;
|
||||
r100_cp_load_microcode(rdev);
|
||||
r = radeon_ring_init(rdev, ring, ring_size, RADEON_WB_CP_RPTR_OFFSET,
|
||||
RADEON_CP_RB_RPTR, RADEON_CP_RB_WPTR,
|
||||
RADEON_CP_PACKET2);
|
||||
if (r) {
|
||||
return r;
|
||||
|
||||
@ -2382,6 +2382,36 @@ out:
|
||||
return err;
|
||||
}
|
||||
|
||||
u32 r600_gfx_get_rptr(struct radeon_device *rdev,
|
||||
struct radeon_ring *ring)
|
||||
{
|
||||
u32 rptr;
|
||||
|
||||
if (rdev->wb.enabled)
|
||||
rptr = rdev->wb.wb[ring->rptr_offs/4];
|
||||
else
|
||||
rptr = RREG32(R600_CP_RB_RPTR);
|
||||
|
||||
return rptr;
|
||||
}
|
||||
|
||||
u32 r600_gfx_get_wptr(struct radeon_device *rdev,
|
||||
struct radeon_ring *ring)
|
||||
{
|
||||
u32 wptr;
|
||||
|
||||
wptr = RREG32(R600_CP_RB_WPTR);
|
||||
|
||||
return wptr;
|
||||
}
|
||||
|
||||
void r600_gfx_set_wptr(struct radeon_device *rdev,
|
||||
struct radeon_ring *ring)
|
||||
{
|
||||
WREG32(R600_CP_RB_WPTR, ring->wptr);
|
||||
(void)RREG32(R600_CP_RB_WPTR);
|
||||
}
|
||||
|
||||
static int r600_cp_load_microcode(struct radeon_device *rdev)
|
||||
{
|
||||
const __be32 *fw_data;
|
||||
@ -2818,14 +2848,12 @@ static int r600_startup(struct radeon_device *rdev)
|
||||
|
||||
ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
|
||||
r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
|
||||
R600_CP_RB_RPTR, R600_CP_RB_WPTR,
|
||||
RADEON_CP_PACKET2);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
|
||||
r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
|
||||
DMA_RB_RPTR, DMA_RB_WPTR,
|
||||
DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
@ -51,7 +51,14 @@ u32 r600_gpu_check_soft_reset(struct radeon_device *rdev);
|
||||
uint32_t r600_dma_get_rptr(struct radeon_device *rdev,
|
||||
struct radeon_ring *ring)
|
||||
{
|
||||
return (radeon_ring_generic_get_rptr(rdev, ring) & 0x3fffc) >> 2;
|
||||
u32 rptr;
|
||||
|
||||
if (rdev->wb.enabled)
|
||||
rptr = rdev->wb.wb[ring->rptr_offs/4];
|
||||
else
|
||||
rptr = RREG32(DMA_RB_RPTR);
|
||||
|
||||
return (rptr & 0x3fffc) >> 2;
|
||||
}
|
||||
|
||||
/**
|
||||
@ -65,7 +72,7 @@ uint32_t r600_dma_get_rptr(struct radeon_device *rdev,
|
||||
uint32_t r600_dma_get_wptr(struct radeon_device *rdev,
|
||||
struct radeon_ring *ring)
|
||||
{
|
||||
return (RREG32(ring->wptr_reg) & 0x3fffc) >> 2;
|
||||
return (RREG32(DMA_RB_WPTR) & 0x3fffc) >> 2;
|
||||
}
|
||||
|
||||
/**
|
||||
@ -79,7 +86,7 @@ uint32_t r600_dma_get_wptr(struct radeon_device *rdev,
|
||||
void r600_dma_set_wptr(struct radeon_device *rdev,
|
||||
struct radeon_ring *ring)
|
||||
{
|
||||
WREG32(ring->wptr_reg, (ring->wptr << 2) & 0x3fffc);
|
||||
WREG32(DMA_RB_WPTR, (ring->wptr << 2) & 0x3fffc);
|
||||
}
|
||||
|
||||
/**
|
||||
|
||||
@ -785,13 +785,11 @@ struct radeon_ring {
|
||||
volatile uint32_t *ring;
|
||||
unsigned rptr;
|
||||
unsigned rptr_offs;
|
||||
unsigned rptr_reg;
|
||||
unsigned rptr_save_reg;
|
||||
u64 next_rptr_gpu_addr;
|
||||
volatile u32 *next_rptr_cpu_addr;
|
||||
unsigned wptr;
|
||||
unsigned wptr_old;
|
||||
unsigned wptr_reg;
|
||||
unsigned ring_size;
|
||||
unsigned ring_free_dw;
|
||||
int count_dw;
|
||||
@ -955,7 +953,7 @@ unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring
|
||||
int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
|
||||
unsigned size, uint32_t *data);
|
||||
int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
|
||||
unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg, u32 nop);
|
||||
unsigned rptr_offs, u32 nop);
|
||||
void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
|
||||
|
||||
|
||||
|
||||
@ -182,9 +182,9 @@ static struct radeon_asic_ring r100_gfx_ring = {
|
||||
.ring_test = &r100_ring_test,
|
||||
.ib_test = &r100_ib_test,
|
||||
.is_lockup = &r100_gpu_is_lockup,
|
||||
.get_rptr = &radeon_ring_generic_get_rptr,
|
||||
.get_wptr = &radeon_ring_generic_get_wptr,
|
||||
.set_wptr = &radeon_ring_generic_set_wptr,
|
||||
.get_rptr = &r100_gfx_get_rptr,
|
||||
.get_wptr = &r100_gfx_get_wptr,
|
||||
.set_wptr = &r100_gfx_set_wptr,
|
||||
};
|
||||
|
||||
static struct radeon_asic r100_asic = {
|
||||
@ -330,9 +330,9 @@ static struct radeon_asic_ring r300_gfx_ring = {
|
||||
.ring_test = &r100_ring_test,
|
||||
.ib_test = &r100_ib_test,
|
||||
.is_lockup = &r100_gpu_is_lockup,
|
||||
.get_rptr = &radeon_ring_generic_get_rptr,
|
||||
.get_wptr = &radeon_ring_generic_get_wptr,
|
||||
.set_wptr = &radeon_ring_generic_set_wptr,
|
||||
.get_rptr = &r100_gfx_get_rptr,
|
||||
.get_wptr = &r100_gfx_get_wptr,
|
||||
.set_wptr = &r100_gfx_set_wptr,
|
||||
};
|
||||
|
||||
static struct radeon_asic r300_asic = {
|
||||
@ -883,9 +883,9 @@ static struct radeon_asic_ring r600_gfx_ring = {
|
||||
.ring_test = &r600_ring_test,
|
||||
.ib_test = &r600_ib_test,
|
||||
.is_lockup = &r600_gfx_is_lockup,
|
||||
.get_rptr = &radeon_ring_generic_get_rptr,
|
||||
.get_wptr = &radeon_ring_generic_get_wptr,
|
||||
.set_wptr = &radeon_ring_generic_set_wptr,
|
||||
.get_rptr = &r600_gfx_get_rptr,
|
||||
.get_wptr = &r600_gfx_get_wptr,
|
||||
.set_wptr = &r600_gfx_set_wptr,
|
||||
};
|
||||
|
||||
static struct radeon_asic_ring r600_dma_ring = {
|
||||
@ -1270,9 +1270,9 @@ static struct radeon_asic_ring evergreen_gfx_ring = {
|
||||
.ring_test = &r600_ring_test,
|
||||
.ib_test = &r600_ib_test,
|
||||
.is_lockup = &evergreen_gfx_is_lockup,
|
||||
.get_rptr = &radeon_ring_generic_get_rptr,
|
||||
.get_wptr = &radeon_ring_generic_get_wptr,
|
||||
.set_wptr = &radeon_ring_generic_set_wptr,
|
||||
.get_rptr = &r600_gfx_get_rptr,
|
||||
.get_wptr = &r600_gfx_get_wptr,
|
||||
.set_wptr = &r600_gfx_set_wptr,
|
||||
};
|
||||
|
||||
static struct radeon_asic_ring evergreen_dma_ring = {
|
||||
@ -1576,9 +1576,9 @@ static struct radeon_asic_ring cayman_gfx_ring = {
|
||||
.ib_test = &r600_ib_test,
|
||||
.is_lockup = &cayman_gfx_is_lockup,
|
||||
.vm_flush = &cayman_vm_flush,
|
||||
.get_rptr = &radeon_ring_generic_get_rptr,
|
||||
.get_wptr = &radeon_ring_generic_get_wptr,
|
||||
.set_wptr = &radeon_ring_generic_set_wptr,
|
||||
.get_rptr = &cayman_gfx_get_rptr,
|
||||
.get_wptr = &cayman_gfx_get_wptr,
|
||||
.set_wptr = &cayman_gfx_set_wptr,
|
||||
};
|
||||
|
||||
static struct radeon_asic_ring cayman_dma_ring = {
|
||||
@ -1591,9 +1591,9 @@ static struct radeon_asic_ring cayman_dma_ring = {
|
||||
.ib_test = &r600_dma_ib_test,
|
||||
.is_lockup = &cayman_dma_is_lockup,
|
||||
.vm_flush = &cayman_dma_vm_flush,
|
||||
.get_rptr = &r600_dma_get_rptr,
|
||||
.get_wptr = &r600_dma_get_wptr,
|
||||
.set_wptr = &r600_dma_set_wptr
|
||||
.get_rptr = &cayman_dma_get_rptr,
|
||||
.get_wptr = &cayman_dma_get_wptr,
|
||||
.set_wptr = &cayman_dma_set_wptr
|
||||
};
|
||||
|
||||
static struct radeon_asic_ring cayman_uvd_ring = {
|
||||
@ -1821,9 +1821,9 @@ static struct radeon_asic_ring si_gfx_ring = {
|
||||
.ib_test = &r600_ib_test,
|
||||
.is_lockup = &si_gfx_is_lockup,
|
||||
.vm_flush = &si_vm_flush,
|
||||
.get_rptr = &radeon_ring_generic_get_rptr,
|
||||
.get_wptr = &radeon_ring_generic_get_wptr,
|
||||
.set_wptr = &radeon_ring_generic_set_wptr,
|
||||
.get_rptr = &cayman_gfx_get_rptr,
|
||||
.get_wptr = &cayman_gfx_get_wptr,
|
||||
.set_wptr = &cayman_gfx_set_wptr,
|
||||
};
|
||||
|
||||
static struct radeon_asic_ring si_dma_ring = {
|
||||
@ -1836,9 +1836,9 @@ static struct radeon_asic_ring si_dma_ring = {
|
||||
.ib_test = &r600_dma_ib_test,
|
||||
.is_lockup = &si_dma_is_lockup,
|
||||
.vm_flush = &si_dma_vm_flush,
|
||||
.get_rptr = &r600_dma_get_rptr,
|
||||
.get_wptr = &r600_dma_get_wptr,
|
||||
.set_wptr = &r600_dma_set_wptr,
|
||||
.get_rptr = &cayman_dma_get_rptr,
|
||||
.get_wptr = &cayman_dma_get_wptr,
|
||||
.set_wptr = &cayman_dma_set_wptr,
|
||||
};
|
||||
|
||||
static struct radeon_asic si_asic = {
|
||||
@ -1952,9 +1952,9 @@ static struct radeon_asic_ring ci_gfx_ring = {
|
||||
.ib_test = &cik_ib_test,
|
||||
.is_lockup = &cik_gfx_is_lockup,
|
||||
.vm_flush = &cik_vm_flush,
|
||||
.get_rptr = &radeon_ring_generic_get_rptr,
|
||||
.get_wptr = &radeon_ring_generic_get_wptr,
|
||||
.set_wptr = &radeon_ring_generic_set_wptr,
|
||||
.get_rptr = &cik_gfx_get_rptr,
|
||||
.get_wptr = &cik_gfx_get_wptr,
|
||||
.set_wptr = &cik_gfx_set_wptr,
|
||||
};
|
||||
|
||||
static struct radeon_asic_ring ci_cp_ring = {
|
||||
@ -1967,9 +1967,9 @@ static struct radeon_asic_ring ci_cp_ring = {
|
||||
.ib_test = &cik_ib_test,
|
||||
.is_lockup = &cik_gfx_is_lockup,
|
||||
.vm_flush = &cik_vm_flush,
|
||||
.get_rptr = &cik_compute_ring_get_rptr,
|
||||
.get_wptr = &cik_compute_ring_get_wptr,
|
||||
.set_wptr = &cik_compute_ring_set_wptr,
|
||||
.get_rptr = &cik_compute_get_rptr,
|
||||
.get_wptr = &cik_compute_get_wptr,
|
||||
.set_wptr = &cik_compute_set_wptr,
|
||||
};
|
||||
|
||||
static struct radeon_asic_ring ci_dma_ring = {
|
||||
@ -1982,9 +1982,9 @@ static struct radeon_asic_ring ci_dma_ring = {
|
||||
.ib_test = &cik_sdma_ib_test,
|
||||
.is_lockup = &cik_sdma_is_lockup,
|
||||
.vm_flush = &cik_dma_vm_flush,
|
||||
.get_rptr = &r600_dma_get_rptr,
|
||||
.get_wptr = &r600_dma_get_wptr,
|
||||
.set_wptr = &r600_dma_set_wptr,
|
||||
.get_rptr = &cik_sdma_get_rptr,
|
||||
.get_wptr = &cik_sdma_get_wptr,
|
||||
.set_wptr = &cik_sdma_set_wptr,
|
||||
};
|
||||
|
||||
static struct radeon_asic ci_asic = {
|
||||
|
||||
@ -47,13 +47,6 @@ u8 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder);
|
||||
void radeon_legacy_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level);
|
||||
u8 radeon_legacy_get_backlight_level(struct radeon_encoder *radeon_encoder);
|
||||
|
||||
u32 radeon_ring_generic_get_rptr(struct radeon_device *rdev,
|
||||
struct radeon_ring *ring);
|
||||
u32 radeon_ring_generic_get_wptr(struct radeon_device *rdev,
|
||||
struct radeon_ring *ring);
|
||||
void radeon_ring_generic_set_wptr(struct radeon_device *rdev,
|
||||
struct radeon_ring *ring);
|
||||
|
||||
/*
|
||||
* r100,rv100,rs100,rv200,rs200
|
||||
*/
|
||||
@ -148,6 +141,13 @@ extern void r100_post_page_flip(struct radeon_device *rdev, int crtc);
|
||||
extern void r100_wait_for_vblank(struct radeon_device *rdev, int crtc);
|
||||
extern int r100_mc_wait_for_idle(struct radeon_device *rdev);
|
||||
|
||||
u32 r100_gfx_get_rptr(struct radeon_device *rdev,
|
||||
struct radeon_ring *ring);
|
||||
u32 r100_gfx_get_wptr(struct radeon_device *rdev,
|
||||
struct radeon_ring *ring);
|
||||
void r100_gfx_set_wptr(struct radeon_device *rdev,
|
||||
struct radeon_ring *ring);
|
||||
|
||||
/*
|
||||
* r200,rv250,rs300,rv280
|
||||
*/
|
||||
@ -368,6 +368,12 @@ int r600_mc_wait_for_idle(struct radeon_device *rdev);
|
||||
int r600_pcie_gart_init(struct radeon_device *rdev);
|
||||
void r600_scratch_init(struct radeon_device *rdev);
|
||||
int r600_init_microcode(struct radeon_device *rdev);
|
||||
u32 r600_gfx_get_rptr(struct radeon_device *rdev,
|
||||
struct radeon_ring *ring);
|
||||
u32 r600_gfx_get_wptr(struct radeon_device *rdev,
|
||||
struct radeon_ring *ring);
|
||||
void r600_gfx_set_wptr(struct radeon_device *rdev,
|
||||
struct radeon_ring *ring);
|
||||
/* r600 irq */
|
||||
int r600_irq_process(struct radeon_device *rdev);
|
||||
int r600_irq_init(struct radeon_device *rdev);
|
||||
@ -594,6 +600,19 @@ void cayman_dma_vm_set_page(struct radeon_device *rdev,
|
||||
|
||||
void cayman_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
|
||||
|
||||
u32 cayman_gfx_get_rptr(struct radeon_device *rdev,
|
||||
struct radeon_ring *ring);
|
||||
u32 cayman_gfx_get_wptr(struct radeon_device *rdev,
|
||||
struct radeon_ring *ring);
|
||||
void cayman_gfx_set_wptr(struct radeon_device *rdev,
|
||||
struct radeon_ring *ring);
|
||||
uint32_t cayman_dma_get_rptr(struct radeon_device *rdev,
|
||||
struct radeon_ring *ring);
|
||||
uint32_t cayman_dma_get_wptr(struct radeon_device *rdev,
|
||||
struct radeon_ring *ring);
|
||||
void cayman_dma_set_wptr(struct radeon_device *rdev,
|
||||
struct radeon_ring *ring);
|
||||
|
||||
int ni_dpm_init(struct radeon_device *rdev);
|
||||
void ni_dpm_setup_asic(struct radeon_device *rdev);
|
||||
int ni_dpm_enable(struct radeon_device *rdev);
|
||||
@ -744,12 +763,24 @@ void cik_sdma_vm_set_page(struct radeon_device *rdev,
|
||||
uint32_t incr, uint32_t flags);
|
||||
void cik_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
|
||||
int cik_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
|
||||
u32 cik_compute_ring_get_rptr(struct radeon_device *rdev,
|
||||
struct radeon_ring *ring);
|
||||
u32 cik_compute_ring_get_wptr(struct radeon_device *rdev,
|
||||
struct radeon_ring *ring);
|
||||
void cik_compute_ring_set_wptr(struct radeon_device *rdev,
|
||||
struct radeon_ring *ring);
|
||||
u32 cik_gfx_get_rptr(struct radeon_device *rdev,
|
||||
struct radeon_ring *ring);
|
||||
u32 cik_gfx_get_wptr(struct radeon_device *rdev,
|
||||
struct radeon_ring *ring);
|
||||
void cik_gfx_set_wptr(struct radeon_device *rdev,
|
||||
struct radeon_ring *ring);
|
||||
u32 cik_compute_get_rptr(struct radeon_device *rdev,
|
||||
struct radeon_ring *ring);
|
||||
u32 cik_compute_get_wptr(struct radeon_device *rdev,
|
||||
struct radeon_ring *ring);
|
||||
void cik_compute_set_wptr(struct radeon_device *rdev,
|
||||
struct radeon_ring *ring);
|
||||
u32 cik_sdma_get_rptr(struct radeon_device *rdev,
|
||||
struct radeon_ring *ring);
|
||||
u32 cik_sdma_get_wptr(struct radeon_device *rdev,
|
||||
struct radeon_ring *ring);
|
||||
void cik_sdma_set_wptr(struct radeon_device *rdev,
|
||||
struct radeon_ring *ring);
|
||||
int ci_get_temp(struct radeon_device *rdev);
|
||||
int kv_get_temp(struct radeon_device *rdev);
|
||||
|
||||
|
||||
@ -332,36 +332,6 @@ bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
|
||||
}
|
||||
}
|
||||
|
||||
u32 radeon_ring_generic_get_rptr(struct radeon_device *rdev,
|
||||
struct radeon_ring *ring)
|
||||
{
|
||||
u32 rptr;
|
||||
|
||||
if (rdev->wb.enabled)
|
||||
rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]);
|
||||
else
|
||||
rptr = RREG32(ring->rptr_reg);
|
||||
|
||||
return rptr;
|
||||
}
|
||||
|
||||
u32 radeon_ring_generic_get_wptr(struct radeon_device *rdev,
|
||||
struct radeon_ring *ring)
|
||||
{
|
||||
u32 wptr;
|
||||
|
||||
wptr = RREG32(ring->wptr_reg);
|
||||
|
||||
return wptr;
|
||||
}
|
||||
|
||||
void radeon_ring_generic_set_wptr(struct radeon_device *rdev,
|
||||
struct radeon_ring *ring)
|
||||
{
|
||||
WREG32(ring->wptr_reg, ring->wptr);
|
||||
(void)RREG32(ring->wptr_reg);
|
||||
}
|
||||
|
||||
/**
|
||||
* radeon_ring_free_size - update the free size
|
||||
*
|
||||
@ -689,22 +659,18 @@ int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
|
||||
* @ring: radeon_ring structure holding ring information
|
||||
* @ring_size: size of the ring
|
||||
* @rptr_offs: offset of the rptr writeback location in the WB buffer
|
||||
* @rptr_reg: MMIO offset of the rptr register
|
||||
* @wptr_reg: MMIO offset of the wptr register
|
||||
* @nop: nop packet for this ring
|
||||
*
|
||||
* Initialize the driver information for the selected ring (all asics).
|
||||
* Returns 0 on success, error on failure.
|
||||
*/
|
||||
int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size,
|
||||
unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg, u32 nop)
|
||||
unsigned rptr_offs, u32 nop)
|
||||
{
|
||||
int r;
|
||||
|
||||
ring->ring_size = ring_size;
|
||||
ring->rptr_offs = rptr_offs;
|
||||
ring->rptr_reg = rptr_reg;
|
||||
ring->wptr_reg = wptr_reg;
|
||||
ring->nop = nop;
|
||||
/* Allocate ring buffer */
|
||||
if (ring->ring_obj == NULL) {
|
||||
@ -798,12 +764,12 @@ static int radeon_debugfs_ring_info(struct seq_file *m, void *data)
|
||||
count = (ring->ring_size / 4) - ring->ring_free_dw;
|
||||
|
||||
wptr = radeon_ring_get_wptr(rdev, ring);
|
||||
seq_printf(m, "wptr(0x%04x): 0x%08x [%5d]\n",
|
||||
ring->wptr_reg, wptr, wptr);
|
||||
seq_printf(m, "wptr: 0x%08x [%5d]\n",
|
||||
wptr, wptr);
|
||||
|
||||
rptr = radeon_ring_get_rptr(rdev, ring);
|
||||
seq_printf(m, "rptr(0x%04x): 0x%08x [%5d]\n",
|
||||
ring->rptr_reg, rptr, rptr);
|
||||
seq_printf(m, "rptr: 0x%08x [%5d]\n",
|
||||
rptr, rptr);
|
||||
|
||||
if (ring->rptr_save_reg) {
|
||||
rptr_next = RREG32(ring->rptr_save_reg);
|
||||
|
||||
@ -1720,14 +1720,12 @@ static int rv770_startup(struct radeon_device *rdev)
|
||||
|
||||
ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
|
||||
r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
|
||||
R600_CP_RB_RPTR, R600_CP_RB_WPTR,
|
||||
RADEON_CP_PACKET2);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
|
||||
r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
|
||||
DMA_RB_RPTR, DMA_RB_WPTR,
|
||||
DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
|
||||
if (r)
|
||||
return r;
|
||||
@ -1746,7 +1744,6 @@ static int rv770_startup(struct radeon_device *rdev)
|
||||
ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
|
||||
if (ring->ring_size) {
|
||||
r = radeon_ring_init(rdev, ring, ring->ring_size, 0,
|
||||
UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR,
|
||||
RADEON_CP_PACKET2);
|
||||
if (!r)
|
||||
r = uvd_v1_0_init(rdev);
|
||||
|
||||
@ -6412,37 +6412,30 @@ static int si_startup(struct radeon_device *rdev)
|
||||
|
||||
ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
|
||||
r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
|
||||
CP_RB0_RPTR, CP_RB0_WPTR,
|
||||
RADEON_CP_PACKET2);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
|
||||
r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP1_RPTR_OFFSET,
|
||||
CP_RB1_RPTR, CP_RB1_WPTR,
|
||||
RADEON_CP_PACKET2);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
|
||||
r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP2_RPTR_OFFSET,
|
||||
CP_RB2_RPTR, CP_RB2_WPTR,
|
||||
RADEON_CP_PACKET2);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
|
||||
r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
|
||||
DMA_RB_RPTR + DMA0_REGISTER_OFFSET,
|
||||
DMA_RB_WPTR + DMA0_REGISTER_OFFSET,
|
||||
DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0));
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
|
||||
r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET,
|
||||
DMA_RB_RPTR + DMA1_REGISTER_OFFSET,
|
||||
DMA_RB_WPTR + DMA1_REGISTER_OFFSET,
|
||||
DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0));
|
||||
if (r)
|
||||
return r;
|
||||
@ -6462,7 +6455,6 @@ static int si_startup(struct radeon_device *rdev)
|
||||
ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
|
||||
if (ring->ring_size) {
|
||||
r = radeon_ring_init(rdev, ring, ring->ring_size, 0,
|
||||
UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR,
|
||||
RADEON_CP_PACKET2);
|
||||
if (!r)
|
||||
r = uvd_v1_0_init(rdev);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user