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KVM: nVMX: Improve nested msr switch checking
This patch improve checks required by Intel Software Developer Manual. - SMM MSRs are not allowed. - microcode MSRs are not allowed. - check x2apic MSRs only when LAPIC is in x2apic mode. - MSR switch areas must be aligned to 16 bytes. - address of first and last byte in MSR switch areas should not set any bits beyond the processor's physical-address width. Also it adds warning messages on failures during MSR switch. These messages are useful for people who debug their VMMs in nVMX. Signed-off-by: Eugene Korenevsky <ekorenevsky@gmail.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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@ -356,6 +356,9 @@
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#define MSR_IA32_UCODE_WRITE 0x00000079
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#define MSR_IA32_UCODE_REV 0x0000008b
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#define MSR_IA32_SMM_MONITOR_CTL 0x0000009b
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#define MSR_IA32_SMBASE 0x0000009e
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#define MSR_IA32_PERF_STATUS 0x00000198
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#define MSR_IA32_PERF_CTL 0x00000199
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#define MSR_AMD_PSTATE_DEF_BASE 0xc0010064
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@ -8293,18 +8293,80 @@ static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
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ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
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}
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static inline int nested_vmx_msr_check_common(struct vmx_msr_entry *e)
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static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
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unsigned long count_field,
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unsigned long addr_field,
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int maxphyaddr)
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{
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if (e->index >> 8 == 0x8 || e->reserved != 0)
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u64 count, addr;
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if (vmcs12_read_any(vcpu, count_field, &count) ||
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vmcs12_read_any(vcpu, addr_field, &addr)) {
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WARN_ON(1);
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return -EINVAL;
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}
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if (count == 0)
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return 0;
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if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
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(addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
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pr_warn_ratelimited(
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"nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
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addr_field, maxphyaddr, count, addr);
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return -EINVAL;
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}
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return 0;
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}
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static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
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struct vmcs12 *vmcs12)
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{
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int maxphyaddr;
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if (vmcs12->vm_exit_msr_load_count == 0 &&
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vmcs12->vm_exit_msr_store_count == 0 &&
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vmcs12->vm_entry_msr_load_count == 0)
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return 0; /* Fast path */
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maxphyaddr = cpuid_maxphyaddr(vcpu);
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if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
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VM_EXIT_MSR_LOAD_ADDR, maxphyaddr) ||
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nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
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VM_EXIT_MSR_STORE_ADDR, maxphyaddr) ||
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nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
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VM_ENTRY_MSR_LOAD_ADDR, maxphyaddr))
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return -EINVAL;
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return 0;
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}
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static inline int nested_vmx_load_msr_check(struct vmx_msr_entry *e)
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static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
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struct vmx_msr_entry *e)
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{
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/* x2APIC MSR accesses are not allowed */
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if (apic_x2apic_mode(vcpu->arch.apic) && e->index >> 8 == 0x8)
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return -EINVAL;
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if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
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e->index == MSR_IA32_UCODE_REV)
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return -EINVAL;
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if (e->reserved != 0)
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return -EINVAL;
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return 0;
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}
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static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
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struct vmx_msr_entry *e)
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{
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if (e->index == MSR_FS_BASE ||
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e->index == MSR_GS_BASE ||
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nested_vmx_msr_check_common(e))
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e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
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nested_vmx_msr_check_common(vcpu, e))
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return -EINVAL;
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return 0;
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}
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static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
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struct vmx_msr_entry *e)
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{
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if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
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nested_vmx_msr_check_common(vcpu, e))
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return -EINVAL;
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return 0;
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}
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@ -8321,14 +8383,28 @@ static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
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msr.host_initiated = false;
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for (i = 0; i < count; i++) {
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kvm_read_guest(vcpu->kvm, gpa + i * sizeof(e), &e, sizeof(e));
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if (nested_vmx_load_msr_check(&e))
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if (kvm_read_guest(vcpu->kvm, gpa + i * sizeof(e),
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&e, sizeof(e))) {
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pr_warn_ratelimited(
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"%s cannot read MSR entry (%u, 0x%08llx)\n",
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__func__, i, gpa + i * sizeof(e));
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goto fail;
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}
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if (nested_vmx_load_msr_check(vcpu, &e)) {
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pr_warn_ratelimited(
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"%s check failed (%u, 0x%x, 0x%x)\n",
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__func__, i, e.index, e.reserved);
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goto fail;
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}
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msr.index = e.index;
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msr.data = e.value;
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if (kvm_set_msr(vcpu, &msr))
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if (kvm_set_msr(vcpu, &msr)) {
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pr_warn_ratelimited(
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"%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
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__func__, i, e.index, e.value);
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goto fail;
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}
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}
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return 0;
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fail:
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return i + 1;
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@ -8340,16 +8416,35 @@ static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
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struct vmx_msr_entry e;
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for (i = 0; i < count; i++) {
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kvm_read_guest(vcpu->kvm, gpa + i * sizeof(e),
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&e, 2 * sizeof(u32));
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if (nested_vmx_msr_check_common(&e))
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if (kvm_read_guest(vcpu->kvm,
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gpa + i * sizeof(e),
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&e, 2 * sizeof(u32))) {
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pr_warn_ratelimited(
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"%s cannot read MSR entry (%u, 0x%08llx)\n",
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__func__, i, gpa + i * sizeof(e));
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return -EINVAL;
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if (kvm_get_msr(vcpu, e.index, &e.value))
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}
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if (nested_vmx_store_msr_check(vcpu, &e)) {
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pr_warn_ratelimited(
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"%s check failed (%u, 0x%x, 0x%x)\n",
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__func__, i, e.index, e.reserved);
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return -EINVAL;
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kvm_write_guest(vcpu->kvm,
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}
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if (kvm_get_msr(vcpu, e.index, &e.value)) {
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pr_warn_ratelimited(
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"%s cannot read MSR (%u, 0x%x)\n",
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__func__, i, e.index);
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return -EINVAL;
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}
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if (kvm_write_guest(vcpu->kvm,
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gpa + i * sizeof(e) +
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offsetof(struct vmx_msr_entry, value),
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&e.value, sizeof(e.value));
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&e.value, sizeof(e.value))) {
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pr_warn_ratelimited(
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"%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
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__func__, i, e.index, e.value);
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return -EINVAL;
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}
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}
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return 0;
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}
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@ -8698,6 +8793,11 @@ static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
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return 1;
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}
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if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12)) {
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nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
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return 1;
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}
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if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
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nested_vmx_true_procbased_ctls_low,
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nested_vmx_procbased_ctls_high) ||
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