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1-Wire bus drivers for v6.8
1. Add new AMD AXI 1-wire host driver for AMD programmable logic IP
core.
2. Add support for Analog Devices DS28EC20 EEPROM to existing DS2433
driver.
3. Few cleanups in W1 GPIO driver.
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Merge tag 'w1-drv-6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-w1 into char-misc-next
Krzysztof writes:
1-Wire bus drivers for v6.8
1. Add new AMD AXI 1-wire host driver for AMD programmable logic IP
core.
2. Add support for Analog Devices DS28EC20 EEPROM to existing DS2433
driver.
3. Few cleanups in W1 GPIO driver.
* tag 'w1-drv-6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-w1:
w1: ds2433: add support for ds28ec20 eeprom
w1: ds2433: use the kernel bitmap implementation
w1: ds2433: introduce a configuration structure
w1: ds2433: remove unused definitions
w1: ds2490: support block sizes larger than 128 bytes in ds_read_block
w1: amd_axi_w1: Explicitly include correct DT includes
w1: gpio: rename pointer to driver data from pdata to ddata
w1: gpio: Drop unused enable_external_pullup from driver data
w1: gpio: Don't use platform data for driver data
w1: Add AXI 1-wire host driver for AMD programmable logic IP core
dt-bindings: w1: Add AMD AXI w1 host and MAINTAINERS entry
This commit is contained in:
Greg Kroah-Hartman
commit
e9215fcca2
44
Documentation/devicetree/bindings/w1/amd,axi-1wire-host.yaml
Normal file
44
Documentation/devicetree/bindings/w1/amd,axi-1wire-host.yaml
Normal file
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@ -0,0 +1,44 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/w1/amd,axi-1wire-host.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: AMD AXI 1-wire bus host for programmable logic
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maintainers:
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- Kris Chaplin <kris.chaplin@amd.com>
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properties:
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compatible:
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const: amd,axi-1wire-host
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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interrupts:
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maxItems: 1
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required:
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- compatible
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- reg
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- clocks
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- interrupts
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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onewire@a0000000 {
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compatible = "amd,axi-1wire-host";
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reg = <0xa0000000 0x10000>;
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clocks = <&zynqmp_clk 0x47>;
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interrupts = <GIC_SPI 0x59 IRQ_TYPE_LEVEL_HIGH>;
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};
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...
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@ -881,6 +881,14 @@ Q: https://patchwork.kernel.org/project/linux-rdma/list/
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F: drivers/infiniband/hw/efa/
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F: include/uapi/rdma/efa-abi.h
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AMD AXI W1 DRIVER
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M: Kris Chaplin <kris.chaplin@amd.com>
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R: Thomas Delev <thomas.delev@amd.com>
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R: Michal Simek <michal.simek@amd.com>
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S: Maintained
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F: Documentation/devicetree/bindings/w1/amd,axi-1wire-host.yaml
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F: drivers/w1/masters/amd_axi_w1.c
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AMD CDX BUS DRIVER
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M: Nipun Gupta <nipun.gupta@amd.com>
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M: Nikhil Agarwal <nikhil.agarwal@amd.com>
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@ -5,6 +5,17 @@
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menu "1-wire Bus Masters"
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config W1_MASTER_AMD_AXI
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tristate "AMD AXI 1-wire bus host"
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help
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Say Y here is you want to support the AMD AXI 1-wire IP core.
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This driver makes use of the programmable logic IP to perform
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correctly timed 1 wire transactions without relying on GPIO timing
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through the kernel.
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This driver can also be built as a module. If so, the module will be
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called amd_w1_axi.
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config W1_MASTER_MATROX
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tristate "Matrox G400 transport layer for 1-wire"
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depends on PCI
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@ -3,6 +3,7 @@
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# Makefile for 1-wire bus master drivers.
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#
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obj-$(CONFIG_W1_MASTER_AMD_AXI) += amd_axi_w1.o
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obj-$(CONFIG_W1_MASTER_MATROX) += matrox_w1.o
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obj-$(CONFIG_W1_MASTER_DS2490) += ds2490.o
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obj-$(CONFIG_W1_MASTER_DS2482) += ds2482.o
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396
drivers/w1/masters/amd_axi_w1.c
Normal file
396
drivers/w1/masters/amd_axi_w1.c
Normal file
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@ -0,0 +1,396 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* amd_axi_w1 - AMD 1Wire programmable logic bus host driver
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*
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* Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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*/
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#include <linux/atomic.h>
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/jiffies.h>
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#include <linux/kernel.h>
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#include <linux/mod_devicetable.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/types.h>
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#include <linux/wait.h>
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#include <linux/w1.h>
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/* 1-wire AMD IP definition */
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#define AXIW1_IPID 0x10ee4453
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/* Registers offset */
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#define AXIW1_INST_REG 0x0
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#define AXIW1_CTRL_REG 0x4
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#define AXIW1_IRQE_REG 0x8
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#define AXIW1_STAT_REG 0xC
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#define AXIW1_DATA_REG 0x10
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#define AXIW1_IPVER_REG 0x18
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#define AXIW1_IPID_REG 0x1C
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/* Instructions */
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#define AXIW1_INITPRES 0x0800
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#define AXIW1_READBIT 0x0C00
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#define AXIW1_WRITEBIT 0x0E00
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#define AXIW1_READBYTE 0x0D00
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#define AXIW1_WRITEBYTE 0x0F00
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/* Status flag masks */
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#define AXIW1_DONE BIT(0)
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#define AXIW1_READY BIT(4)
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#define AXIW1_PRESENCE BIT(31)
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#define AXIW1_MAJORVER_MASK GENMASK(23, 8)
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#define AXIW1_MINORVER_MASK GENMASK(7, 0)
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/* Control flag */
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#define AXIW1_GO BIT(0)
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#define AXI_CLEAR 0
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#define AXI_RESET BIT(31)
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#define AXIW1_READDATA BIT(0)
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/* Interrupt Enable */
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#define AXIW1_READY_IRQ_EN BIT(4)
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#define AXIW1_DONE_IRQ_EN BIT(0)
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#define AXIW1_TIMEOUT msecs_to_jiffies(100)
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#define DRIVER_NAME "amd_axi_w1"
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struct amd_axi_w1_local {
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struct device *dev;
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void __iomem *base_addr;
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int irq;
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atomic_t flag; /* Set on IRQ, cleared once serviced */
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wait_queue_head_t wait_queue;
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struct w1_bus_master bus_host;
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};
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/**
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* amd_axi_w1_wait_irq_interruptible_timeout() - Wait for IRQ with timeout.
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*
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* @amd_axi_w1_local: Pointer to device structure
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* @IRQ: IRQ channel to wait on
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*
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* Return: %0 - OK, %-EINTR - Interrupted, %-EBUSY - Timed out
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*/
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static int amd_axi_w1_wait_irq_interruptible_timeout(struct amd_axi_w1_local *amd_axi_w1_local,
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u32 IRQ)
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{
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int ret;
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/* Enable the IRQ requested and wait for flag to indicate it's been triggered */
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iowrite32(IRQ, amd_axi_w1_local->base_addr + AXIW1_IRQE_REG);
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ret = wait_event_interruptible_timeout(amd_axi_w1_local->wait_queue,
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atomic_read(&amd_axi_w1_local->flag) != 0,
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AXIW1_TIMEOUT);
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if (ret < 0) {
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dev_err(amd_axi_w1_local->dev, "Wait IRQ Interrupted\n");
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return -EINTR;
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}
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if (!ret) {
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dev_err(amd_axi_w1_local->dev, "Wait IRQ Timeout\n");
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return -EBUSY;
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}
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atomic_set(&amd_axi_w1_local->flag, 0);
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return 0;
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}
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/**
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* amd_axi_w1_touch_bit() - Performs the touch-bit function - write a 0 or 1 and reads the level.
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*
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* @data: Pointer to device structure
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* @bit: The level to write
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*
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* Return: The level read
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*/
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static u8 amd_axi_w1_touch_bit(void *data, u8 bit)
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{
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struct amd_axi_w1_local *amd_axi_w1_local = data;
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u8 val = 0;
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int rc;
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/* Wait for READY signal to be 1 to ensure 1-wire IP is ready */
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while ((ioread32(amd_axi_w1_local->base_addr + AXIW1_STAT_REG) & AXIW1_READY) == 0) {
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rc = amd_axi_w1_wait_irq_interruptible_timeout(amd_axi_w1_local,
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AXIW1_READY_IRQ_EN);
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if (rc < 0)
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return 1; /* Callee doesn't test for error. Return inactive bus state */
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}
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if (bit)
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/* Read. Write read Bit command in register 0 */
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iowrite32(AXIW1_READBIT, amd_axi_w1_local->base_addr + AXIW1_INST_REG);
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else
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/* Write. Write tx Bit command in instruction register with bit to transmit */
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iowrite32(AXIW1_WRITEBIT + (bit & 0x01),
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amd_axi_w1_local->base_addr + AXIW1_INST_REG);
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/* Write Go signal and clear control reset signal in control register */
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iowrite32(AXIW1_GO, amd_axi_w1_local->base_addr + AXIW1_CTRL_REG);
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/* Wait for done signal to be 1 */
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while ((ioread32(amd_axi_w1_local->base_addr + AXIW1_STAT_REG) & AXIW1_DONE) != 1) {
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rc = amd_axi_w1_wait_irq_interruptible_timeout(amd_axi_w1_local, AXIW1_DONE_IRQ_EN);
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if (rc < 0)
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return 1; /* Callee doesn't test for error. Return inactive bus state */
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}
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/* If read, Retrieve data from register */
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if (bit)
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val = (u8)(ioread32(amd_axi_w1_local->base_addr + AXIW1_DATA_REG) & AXIW1_READDATA);
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/* Clear Go signal in register 1 */
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iowrite32(AXI_CLEAR, amd_axi_w1_local->base_addr + AXIW1_CTRL_REG);
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return val;
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}
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/**
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* amd_axi_w1_read_byte - Performs the read byte function.
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*
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* @data: Pointer to device structure
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* Return: The value read
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*/
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static u8 amd_axi_w1_read_byte(void *data)
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{
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struct amd_axi_w1_local *amd_axi_w1_local = data;
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u8 val = 0;
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int rc;
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/* Wait for READY signal to be 1 to ensure 1-wire IP is ready */
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while ((ioread32(amd_axi_w1_local->base_addr + AXIW1_STAT_REG) & AXIW1_READY) == 0) {
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rc = amd_axi_w1_wait_irq_interruptible_timeout(amd_axi_w1_local,
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AXIW1_READY_IRQ_EN);
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if (rc < 0)
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return 0xFF; /* Return inactive bus state */
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}
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/* Write read Byte command in instruction register*/
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iowrite32(AXIW1_READBYTE, amd_axi_w1_local->base_addr + AXIW1_INST_REG);
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/* Write Go signal and clear control reset signal in control register */
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iowrite32(AXIW1_GO, amd_axi_w1_local->base_addr + AXIW1_CTRL_REG);
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/* Wait for done signal to be 1 */
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while ((ioread32(amd_axi_w1_local->base_addr + AXIW1_STAT_REG) & AXIW1_DONE) != 1) {
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rc = amd_axi_w1_wait_irq_interruptible_timeout(amd_axi_w1_local, AXIW1_DONE_IRQ_EN);
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if (rc < 0)
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return 0xFF; /* Return inactive bus state */
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}
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/* Retrieve LSB bit in data register to get RX byte */
|
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val = (u8)(ioread32(amd_axi_w1_local->base_addr + AXIW1_DATA_REG) & 0x000000FF);
|
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/* Clear Go signal in control register */
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iowrite32(AXI_CLEAR, amd_axi_w1_local->base_addr + AXIW1_CTRL_REG);
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|
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return val;
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||||
}
|
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|
||||
/**
|
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* amd_axi_w1_write_byte - Performs the write byte function.
|
||||
*
|
||||
* @data: The ds2482 channel pointer
|
||||
* @val: The value to write
|
||||
*/
|
||||
static void amd_axi_w1_write_byte(void *data, u8 val)
|
||||
{
|
||||
struct amd_axi_w1_local *amd_axi_w1_local = data;
|
||||
int rc;
|
||||
|
||||
/* Wait for READY signal to be 1 to ensure 1-wire IP is ready */
|
||||
while ((ioread32(amd_axi_w1_local->base_addr + AXIW1_STAT_REG) & AXIW1_READY) == 0) {
|
||||
rc = amd_axi_w1_wait_irq_interruptible_timeout(amd_axi_w1_local,
|
||||
AXIW1_READY_IRQ_EN);
|
||||
if (rc < 0)
|
||||
return;
|
||||
}
|
||||
|
||||
/* Write tx Byte command in instruction register with bit to transmit */
|
||||
iowrite32(AXIW1_WRITEBYTE + val, amd_axi_w1_local->base_addr + AXIW1_INST_REG);
|
||||
|
||||
/* Write Go signal and clear control reset signal in register 1 */
|
||||
iowrite32(AXIW1_GO, amd_axi_w1_local->base_addr + AXIW1_CTRL_REG);
|
||||
|
||||
/* Wait for done signal to be 1 */
|
||||
while ((ioread32(amd_axi_w1_local->base_addr + AXIW1_STAT_REG) & AXIW1_DONE) != 1) {
|
||||
rc = amd_axi_w1_wait_irq_interruptible_timeout(amd_axi_w1_local,
|
||||
AXIW1_DONE_IRQ_EN);
|
||||
if (rc < 0)
|
||||
return;
|
||||
}
|
||||
|
||||
/* Clear Go signal in control register */
|
||||
iowrite32(AXI_CLEAR, amd_axi_w1_local->base_addr + AXIW1_CTRL_REG);
|
||||
}
|
||||
|
||||
/**
|
||||
* amd_axi_w1_reset_bus() - Issues a reset bus sequence.
|
||||
*
|
||||
* @data: the bus host data struct
|
||||
* Return: 0=Device present, 1=No device present or error
|
||||
*/
|
||||
static u8 amd_axi_w1_reset_bus(void *data)
|
||||
{
|
||||
struct amd_axi_w1_local *amd_axi_w1_local = data;
|
||||
u8 val = 0;
|
||||
int rc;
|
||||
|
||||
/* Reset 1-wire Axi IP */
|
||||
iowrite32(AXI_RESET, amd_axi_w1_local->base_addr + AXIW1_CTRL_REG);
|
||||
|
||||
/* Wait for READY signal to be 1 to ensure 1-wire IP is ready */
|
||||
while ((ioread32(amd_axi_w1_local->base_addr + AXIW1_STAT_REG) & AXIW1_READY) == 0) {
|
||||
rc = amd_axi_w1_wait_irq_interruptible_timeout(amd_axi_w1_local,
|
||||
AXIW1_READY_IRQ_EN);
|
||||
if (rc < 0)
|
||||
return 1; /* Something went wrong with the hardware */
|
||||
}
|
||||
/* Write Initialization command in instruction register */
|
||||
iowrite32(AXIW1_INITPRES, amd_axi_w1_local->base_addr + AXIW1_INST_REG);
|
||||
|
||||
/* Write Go signal and clear control reset signal in register 1 */
|
||||
iowrite32(AXIW1_GO, amd_axi_w1_local->base_addr + AXIW1_CTRL_REG);
|
||||
|
||||
/* Wait for done signal to be 1 */
|
||||
while ((ioread32(amd_axi_w1_local->base_addr + AXIW1_STAT_REG) & AXIW1_DONE) != 1) {
|
||||
rc = amd_axi_w1_wait_irq_interruptible_timeout(amd_axi_w1_local, AXIW1_DONE_IRQ_EN);
|
||||
if (rc < 0)
|
||||
return 1; /* Something went wrong with the hardware */
|
||||
}
|
||||
/* Retrieve MSB bit in status register to get failure bit */
|
||||
if ((ioread32(amd_axi_w1_local->base_addr + AXIW1_STAT_REG) & AXIW1_PRESENCE) != 0)
|
||||
val = 1;
|
||||
|
||||
/* Clear Go signal in control register */
|
||||
iowrite32(AXI_CLEAR, amd_axi_w1_local->base_addr + AXIW1_CTRL_REG);
|
||||
|
||||
return val;
|
||||
}
|
||||
|
||||
/* Reset the 1-wire AXI IP. Put the IP in reset state and clear registers */
|
||||
static void amd_axi_w1_reset(struct amd_axi_w1_local *amd_axi_w1_local)
|
||||
{
|
||||
iowrite32(AXI_RESET, amd_axi_w1_local->base_addr + AXIW1_CTRL_REG);
|
||||
iowrite32(AXI_CLEAR, amd_axi_w1_local->base_addr + AXIW1_INST_REG);
|
||||
iowrite32(AXI_CLEAR, amd_axi_w1_local->base_addr + AXIW1_IRQE_REG);
|
||||
iowrite32(AXI_CLEAR, amd_axi_w1_local->base_addr + AXIW1_STAT_REG);
|
||||
iowrite32(AXI_CLEAR, amd_axi_w1_local->base_addr + AXIW1_DATA_REG);
|
||||
}
|
||||
|
||||
static irqreturn_t amd_axi_w1_irq(int irq, void *lp)
|
||||
{
|
||||
struct amd_axi_w1_local *amd_axi_w1_local = lp;
|
||||
|
||||
/* Reset interrupt trigger */
|
||||
iowrite32(AXI_CLEAR, amd_axi_w1_local->base_addr + AXIW1_IRQE_REG);
|
||||
|
||||
atomic_set(&amd_axi_w1_local->flag, 1);
|
||||
wake_up_interruptible(&amd_axi_w1_local->wait_queue);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static int amd_axi_w1_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct amd_axi_w1_local *lp;
|
||||
struct clk *clk;
|
||||
u32 ver_major, ver_minor;
|
||||
int val, rc = 0;
|
||||
|
||||
lp = devm_kzalloc(dev, sizeof(*lp), GFP_KERNEL);
|
||||
if (!lp)
|
||||
return -ENOMEM;
|
||||
|
||||
lp->dev = dev;
|
||||
lp->base_addr = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(lp->base_addr))
|
||||
return PTR_ERR(lp->base_addr);
|
||||
|
||||
lp->irq = platform_get_irq(pdev, 0);
|
||||
if (lp->irq < 0)
|
||||
return lp->irq;
|
||||
|
||||
rc = devm_request_irq(dev, lp->irq, &amd_axi_w1_irq, IRQF_TRIGGER_HIGH, DRIVER_NAME, lp);
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
/* Initialize wait queue and flag */
|
||||
init_waitqueue_head(&lp->wait_queue);
|
||||
|
||||
clk = devm_clk_get_enabled(dev, NULL);
|
||||
if (IS_ERR(clk))
|
||||
return PTR_ERR(clk);
|
||||
|
||||
/* Verify IP presence in HW */
|
||||
if (ioread32(lp->base_addr + AXIW1_IPID_REG) != AXIW1_IPID) {
|
||||
dev_err(dev, "AMD 1-wire IP not detected in hardware\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
/*
|
||||
* Allow for future driver expansion supporting new hardware features
|
||||
* This driver currently only supports hardware 1.x, but include logic
|
||||
* to detect if a potentially incompatible future version is used
|
||||
* by reading major version ID. It is highly undesirable for new IP versions
|
||||
* to break the API, but this code will at least allow for graceful failure
|
||||
* should that happen. Future new features can be enabled by hardware
|
||||
* incrementing the minor version and augmenting the driver to detect capability
|
||||
* using the minor version number
|
||||
*/
|
||||
val = ioread32(lp->base_addr + AXIW1_IPVER_REG);
|
||||
ver_major = FIELD_GET(AXIW1_MAJORVER_MASK, val);
|
||||
ver_minor = FIELD_GET(AXIW1_MINORVER_MASK, val);
|
||||
|
||||
if (ver_major != 1) {
|
||||
dev_err(dev, "AMD AXI W1 host version %u.%u is not supported by this driver",
|
||||
ver_major, ver_minor);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
lp->bus_host.data = lp;
|
||||
lp->bus_host.touch_bit = amd_axi_w1_touch_bit;
|
||||
lp->bus_host.read_byte = amd_axi_w1_read_byte;
|
||||
lp->bus_host.write_byte = amd_axi_w1_write_byte;
|
||||
lp->bus_host.reset_bus = amd_axi_w1_reset_bus;
|
||||
|
||||
amd_axi_w1_reset(lp);
|
||||
|
||||
platform_set_drvdata(pdev, lp);
|
||||
rc = w1_add_master_device(&lp->bus_host);
|
||||
if (rc) {
|
||||
dev_err(dev, "Could not add host device\n");
|
||||
return rc;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void amd_axi_w1_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct amd_axi_w1_local *lp = platform_get_drvdata(pdev);
|
||||
|
||||
w1_remove_master_device(&lp->bus_host);
|
||||
}
|
||||
|
||||
static const struct of_device_id amd_axi_w1_of_match[] = {
|
||||
{ .compatible = "amd,axi-1wire-host" },
|
||||
{ /* end of list */ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, amd_axi_w1_of_match);
|
||||
|
||||
static struct platform_driver amd_axi_w1_driver = {
|
||||
.probe = amd_axi_w1_probe,
|
||||
.remove_new = amd_axi_w1_remove,
|
||||
.driver = {
|
||||
.name = DRIVER_NAME,
|
||||
.of_match_table = amd_axi_w1_of_match,
|
||||
},
|
||||
};
|
||||
module_platform_driver(amd_axi_w1_driver);
|
||||
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_AUTHOR("Kris Chaplin <kris.chaplin@amd.com>");
|
||||
MODULE_DESCRIPTION("Driver for AMD AXI 1 Wire IP core");
|
||||
|
|
@ -98,6 +98,8 @@
|
|||
#define ST_EPOF 0x80
|
||||
/* Status transfer size, 16 bytes status, 16 byte result flags */
|
||||
#define ST_SIZE 0x20
|
||||
/* 1-wire data i/o fifo size, 128 bytes */
|
||||
#define FIFO_SIZE 0x80
|
||||
|
||||
/* Result Register flags */
|
||||
#define RR_DETECT 0xA5 /* New device detected */
|
||||
|
|
@ -614,14 +616,11 @@ static int ds_read_byte(struct ds_device *dev, u8 *byte)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int ds_read_block(struct ds_device *dev, u8 *buf, int len)
|
||||
static int read_block_chunk(struct ds_device *dev, u8 *buf, int len)
|
||||
{
|
||||
struct ds_status st;
|
||||
int err;
|
||||
|
||||
if (len > 64*1024)
|
||||
return -E2BIG;
|
||||
|
||||
memset(buf, 0xFF, len);
|
||||
|
||||
err = ds_send_data(dev, buf, len);
|
||||
|
|
@ -640,6 +639,24 @@ static int ds_read_block(struct ds_device *dev, u8 *buf, int len)
|
|||
return err;
|
||||
}
|
||||
|
||||
static int ds_read_block(struct ds_device *dev, u8 *buf, int len)
|
||||
{
|
||||
int err, to_read, rem = len;
|
||||
|
||||
if (len > 64 * 1024)
|
||||
return -E2BIG;
|
||||
|
||||
do {
|
||||
to_read = rem <= FIFO_SIZE ? rem : FIFO_SIZE;
|
||||
err = read_block_chunk(dev, &buf[len - rem], to_read);
|
||||
if (err < 0)
|
||||
return err;
|
||||
rem -= to_read;
|
||||
} while (rem);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static int ds_write_block(struct ds_device *dev, u8 *buf, int len)
|
||||
{
|
||||
int err;
|
||||
|
|
|
|||
|
|
@ -9,7 +9,6 @@
|
|||
#include <linux/module.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/w1-gpio.h>
|
||||
#include <linux/gpio/consumer.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/err.h>
|
||||
|
|
@ -18,27 +17,33 @@
|
|||
|
||||
#include <linux/w1.h>
|
||||
|
||||
struct w1_gpio_ddata {
|
||||
struct gpio_desc *gpiod;
|
||||
struct gpio_desc *pullup_gpiod;
|
||||
unsigned int pullup_duration;
|
||||
};
|
||||
|
||||
static u8 w1_gpio_set_pullup(void *data, int delay)
|
||||
{
|
||||
struct w1_gpio_platform_data *pdata = data;
|
||||
struct w1_gpio_ddata *ddata = data;
|
||||
|
||||
if (delay) {
|
||||
pdata->pullup_duration = delay;
|
||||
ddata->pullup_duration = delay;
|
||||
} else {
|
||||
if (pdata->pullup_duration) {
|
||||
if (ddata->pullup_duration) {
|
||||
/*
|
||||
* This will OVERRIDE open drain emulation and force-pull
|
||||
* the line high for some time.
|
||||
*/
|
||||
gpiod_set_raw_value(pdata->gpiod, 1);
|
||||
msleep(pdata->pullup_duration);
|
||||
gpiod_set_raw_value(ddata->gpiod, 1);
|
||||
msleep(ddata->pullup_duration);
|
||||
/*
|
||||
* This will simply set the line as input since we are doing
|
||||
* open drain emulation in the GPIO library.
|
||||
*/
|
||||
gpiod_set_value(pdata->gpiod, 1);
|
||||
gpiod_set_value(ddata->gpiod, 1);
|
||||
}
|
||||
pdata->pullup_duration = 0;
|
||||
ddata->pullup_duration = 0;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
@ -46,16 +51,16 @@ static u8 w1_gpio_set_pullup(void *data, int delay)
|
|||
|
||||
static void w1_gpio_write_bit(void *data, u8 bit)
|
||||
{
|
||||
struct w1_gpio_platform_data *pdata = data;
|
||||
struct w1_gpio_ddata *ddata = data;
|
||||
|
||||
gpiod_set_value(pdata->gpiod, bit);
|
||||
gpiod_set_value(ddata->gpiod, bit);
|
||||
}
|
||||
|
||||
static u8 w1_gpio_read_bit(void *data)
|
||||
{
|
||||
struct w1_gpio_platform_data *pdata = data;
|
||||
struct w1_gpio_ddata *ddata = data;
|
||||
|
||||
return gpiod_get_value(pdata->gpiod) ? 1 : 0;
|
||||
return gpiod_get_value(ddata->gpiod) ? 1 : 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_OF)
|
||||
|
|
@ -69,58 +74,48 @@ MODULE_DEVICE_TABLE(of, w1_gpio_dt_ids);
|
|||
static int w1_gpio_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct w1_bus_master *master;
|
||||
struct w1_gpio_platform_data *pdata;
|
||||
struct w1_gpio_ddata *ddata;
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device_node *np = dev->of_node;
|
||||
/* Enforce open drain mode by default */
|
||||
enum gpiod_flags gflags = GPIOD_OUT_LOW_OPEN_DRAIN;
|
||||
int err;
|
||||
|
||||
if (of_have_populated_dt()) {
|
||||
pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
|
||||
if (!pdata)
|
||||
return -ENOMEM;
|
||||
ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL);
|
||||
if (!ddata)
|
||||
return -ENOMEM;
|
||||
|
||||
/*
|
||||
* This parameter means that something else than the gpiolib has
|
||||
* already set the line into open drain mode, so we should just
|
||||
* driver it high/low like we are in full control of the line and
|
||||
* open drain will happen transparently.
|
||||
*/
|
||||
if (of_property_present(np, "linux,open-drain"))
|
||||
gflags = GPIOD_OUT_LOW;
|
||||
|
||||
pdev->dev.platform_data = pdata;
|
||||
}
|
||||
pdata = dev_get_platdata(dev);
|
||||
|
||||
if (!pdata) {
|
||||
dev_err(dev, "No configuration data\n");
|
||||
return -ENXIO;
|
||||
}
|
||||
/*
|
||||
* This parameter means that something else than the gpiolib has
|
||||
* already set the line into open drain mode, so we should just
|
||||
* driver it high/low like we are in full control of the line and
|
||||
* open drain will happen transparently.
|
||||
*/
|
||||
if (of_property_present(np, "linux,open-drain"))
|
||||
gflags = GPIOD_OUT_LOW;
|
||||
|
||||
master = devm_kzalloc(dev, sizeof(struct w1_bus_master),
|
||||
GFP_KERNEL);
|
||||
if (!master)
|
||||
return -ENOMEM;
|
||||
|
||||
pdata->gpiod = devm_gpiod_get_index(dev, NULL, 0, gflags);
|
||||
if (IS_ERR(pdata->gpiod)) {
|
||||
ddata->gpiod = devm_gpiod_get_index(dev, NULL, 0, gflags);
|
||||
if (IS_ERR(ddata->gpiod)) {
|
||||
dev_err(dev, "gpio_request (pin) failed\n");
|
||||
return PTR_ERR(pdata->gpiod);
|
||||
return PTR_ERR(ddata->gpiod);
|
||||
}
|
||||
|
||||
pdata->pullup_gpiod =
|
||||
ddata->pullup_gpiod =
|
||||
devm_gpiod_get_index_optional(dev, NULL, 1, GPIOD_OUT_LOW);
|
||||
if (IS_ERR(pdata->pullup_gpiod)) {
|
||||
if (IS_ERR(ddata->pullup_gpiod)) {
|
||||
dev_err(dev, "gpio_request_one "
|
||||
"(ext_pullup_enable_pin) failed\n");
|
||||
return PTR_ERR(pdata->pullup_gpiod);
|
||||
return PTR_ERR(ddata->pullup_gpiod);
|
||||
}
|
||||
|
||||
master->data = pdata;
|
||||
master->data = ddata;
|
||||
master->read_bit = w1_gpio_read_bit;
|
||||
gpiod_direction_output(pdata->gpiod, 1);
|
||||
gpiod_direction_output(ddata->gpiod, 1);
|
||||
master->write_bit = w1_gpio_write_bit;
|
||||
|
||||
/*
|
||||
|
|
@ -138,11 +133,8 @@ static int w1_gpio_probe(struct platform_device *pdev)
|
|||
return err;
|
||||
}
|
||||
|
||||
if (pdata->enable_external_pullup)
|
||||
pdata->enable_external_pullup(1);
|
||||
|
||||
if (pdata->pullup_gpiod)
|
||||
gpiod_set_value(pdata->pullup_gpiod, 1);
|
||||
if (ddata->pullup_gpiod)
|
||||
gpiod_set_value(ddata->pullup_gpiod, 1);
|
||||
|
||||
platform_set_drvdata(pdev, master);
|
||||
|
||||
|
|
@ -152,45 +144,19 @@ static int w1_gpio_probe(struct platform_device *pdev)
|
|||
static int w1_gpio_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct w1_bus_master *master = platform_get_drvdata(pdev);
|
||||
struct w1_gpio_platform_data *pdata = dev_get_platdata(&pdev->dev);
|
||||
struct w1_gpio_ddata *ddata = master->data;
|
||||
|
||||
if (pdata->enable_external_pullup)
|
||||
pdata->enable_external_pullup(0);
|
||||
|
||||
if (pdata->pullup_gpiod)
|
||||
gpiod_set_value(pdata->pullup_gpiod, 0);
|
||||
if (ddata->pullup_gpiod)
|
||||
gpiod_set_value(ddata->pullup_gpiod, 0);
|
||||
|
||||
w1_remove_master_device(master);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __maybe_unused w1_gpio_suspend(struct device *dev)
|
||||
{
|
||||
struct w1_gpio_platform_data *pdata = dev_get_platdata(dev);
|
||||
|
||||
if (pdata->enable_external_pullup)
|
||||
pdata->enable_external_pullup(0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __maybe_unused w1_gpio_resume(struct device *dev)
|
||||
{
|
||||
struct w1_gpio_platform_data *pdata = dev_get_platdata(dev);
|
||||
|
||||
if (pdata->enable_external_pullup)
|
||||
pdata->enable_external_pullup(1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static SIMPLE_DEV_PM_OPS(w1_gpio_pm_ops, w1_gpio_suspend, w1_gpio_resume);
|
||||
|
||||
static struct platform_driver w1_gpio_driver = {
|
||||
.driver = {
|
||||
.name = "w1-gpio",
|
||||
.pm = &w1_gpio_pm_ops,
|
||||
.of_match_table = of_match_ptr(w1_gpio_dt_ids),
|
||||
},
|
||||
.probe = w1_gpio_probe,
|
||||
|
|
|
|||
|
|
@ -1,8 +1,9 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* w1_ds2433.c - w1 family 23 (DS2433) driver
|
||||
* w1_ds2433.c - w1 family 23 (DS2433) & 43 (DS28EC20) eeprom driver
|
||||
*
|
||||
* Copyright (c) 2005 Ben Gardner <bgardner@wabtec.com>
|
||||
* Copyright (c) 2023 Marc Ferland <marc.ferland@sonatest.com>
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
|
|
@ -23,23 +24,45 @@
|
|||
#include <linux/w1.h>
|
||||
|
||||
#define W1_EEPROM_DS2433 0x23
|
||||
#define W1_EEPROM_DS28EC20 0x43
|
||||
|
||||
#define W1_EEPROM_DS2433_SIZE 512
|
||||
#define W1_EEPROM_DS28EC20_SIZE 2560
|
||||
|
||||
#define W1_EEPROM_SIZE 512
|
||||
#define W1_PAGE_COUNT 16
|
||||
#define W1_PAGE_SIZE 32
|
||||
#define W1_PAGE_BITS 5
|
||||
#define W1_PAGE_MASK 0x1F
|
||||
|
||||
#define W1_F23_TIME 300
|
||||
#define W1_VALIDCRC_MAX 96
|
||||
|
||||
#define W1_F23_READ_EEPROM 0xF0
|
||||
#define W1_F23_WRITE_SCRATCH 0x0F
|
||||
#define W1_F23_READ_SCRATCH 0xAA
|
||||
#define W1_F23_COPY_SCRATCH 0x55
|
||||
|
||||
struct ds2433_config {
|
||||
size_t eeprom_size; /* eeprom size in bytes */
|
||||
unsigned int page_count; /* number of 256 bits pages */
|
||||
unsigned int tprog; /* time in ms for page programming */
|
||||
};
|
||||
|
||||
static const struct ds2433_config config_f23 = {
|
||||
.eeprom_size = W1_EEPROM_DS2433_SIZE,
|
||||
.page_count = 16,
|
||||
.tprog = 5,
|
||||
};
|
||||
|
||||
static const struct ds2433_config config_f43 = {
|
||||
.eeprom_size = W1_EEPROM_DS28EC20_SIZE,
|
||||
.page_count = 80,
|
||||
.tprog = 10,
|
||||
};
|
||||
|
||||
struct w1_f23_data {
|
||||
u8 memory[W1_EEPROM_SIZE];
|
||||
u32 validcrc;
|
||||
#ifdef CONFIG_W1_SLAVE_DS2433_CRC
|
||||
u8 *memory;
|
||||
DECLARE_BITMAP(validcrc, W1_VALIDCRC_MAX);
|
||||
#endif
|
||||
const struct ds2433_config *cfg;
|
||||
};
|
||||
|
||||
/*
|
||||
|
|
@ -64,11 +87,11 @@ static int w1_f23_refresh_block(struct w1_slave *sl, struct w1_f23_data *data,
|
|||
u8 wrbuf[3];
|
||||
int off = block * W1_PAGE_SIZE;
|
||||
|
||||
if (data->validcrc & (1 << block))
|
||||
if (test_bit(block, data->validcrc))
|
||||
return 0;
|
||||
|
||||
if (w1_reset_select_slave(sl)) {
|
||||
data->validcrc = 0;
|
||||
bitmap_zero(data->validcrc, data->cfg->page_count);
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
|
|
@ -80,7 +103,7 @@ static int w1_f23_refresh_block(struct w1_slave *sl, struct w1_f23_data *data,
|
|||
|
||||
/* cache the block if the CRC is valid */
|
||||
if (crc16(CRC16_INIT, &data->memory[off], W1_PAGE_SIZE) == CRC16_VALID)
|
||||
data->validcrc |= (1 << block);
|
||||
set_bit(block, data->validcrc);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -98,7 +121,7 @@ static ssize_t eeprom_read(struct file *filp, struct kobject *kobj,
|
|||
u8 wrbuf[3];
|
||||
#endif
|
||||
|
||||
count = w1_f23_fix_count(off, count, W1_EEPROM_SIZE);
|
||||
count = w1_f23_fix_count(off, count, bin_attr->size);
|
||||
if (!count)
|
||||
return 0;
|
||||
|
||||
|
|
@ -153,9 +176,7 @@ out_up:
|
|||
*/
|
||||
static int w1_f23_write(struct w1_slave *sl, int addr, int len, const u8 *data)
|
||||
{
|
||||
#ifdef CONFIG_W1_SLAVE_DS2433_CRC
|
||||
struct w1_f23_data *f23 = sl->family_data;
|
||||
#endif
|
||||
u8 wrbuf[4];
|
||||
u8 rdbuf[W1_PAGE_SIZE + 3];
|
||||
u8 es = (addr + len - 1) & 0x1f;
|
||||
|
|
@ -191,13 +212,13 @@ static int w1_f23_write(struct w1_slave *sl, int addr, int len, const u8 *data)
|
|||
wrbuf[3] = es;
|
||||
w1_write_block(sl->master, wrbuf, 4);
|
||||
|
||||
/* Sleep for 5 ms to wait for the write to complete */
|
||||
msleep(5);
|
||||
/* Sleep for tprog ms to wait for the write to complete */
|
||||
msleep(f23->cfg->tprog);
|
||||
|
||||
/* Reset the bus to wake up the EEPROM (this may not be needed) */
|
||||
w1_reset_bus(sl->master);
|
||||
#ifdef CONFIG_W1_SLAVE_DS2433_CRC
|
||||
f23->validcrc &= ~(1 << (addr >> W1_PAGE_BITS));
|
||||
clear_bit(addr >> W1_PAGE_BITS, f23->validcrc);
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -209,7 +230,7 @@ static ssize_t eeprom_write(struct file *filp, struct kobject *kobj,
|
|||
struct w1_slave *sl = kobj_to_w1_slave(kobj);
|
||||
int addr, len, idx;
|
||||
|
||||
count = w1_f23_fix_count(off, count, W1_EEPROM_SIZE);
|
||||
count = w1_f23_fix_count(off, count, bin_attr->size);
|
||||
if (!count)
|
||||
return 0;
|
||||
|
||||
|
|
@ -253,10 +274,22 @@ out_up:
|
|||
return count;
|
||||
}
|
||||
|
||||
static BIN_ATTR_RW(eeprom, W1_EEPROM_SIZE);
|
||||
static struct bin_attribute bin_attr_f23_eeprom = {
|
||||
.attr = { .name = "eeprom", .mode = 0644 },
|
||||
.read = eeprom_read,
|
||||
.write = eeprom_write,
|
||||
.size = W1_EEPROM_DS2433_SIZE,
|
||||
};
|
||||
|
||||
static struct bin_attribute bin_attr_f43_eeprom = {
|
||||
.attr = { .name = "eeprom", .mode = 0644 },
|
||||
.read = eeprom_read,
|
||||
.write = eeprom_write,
|
||||
.size = W1_EEPROM_DS28EC20_SIZE,
|
||||
};
|
||||
|
||||
static struct bin_attribute *w1_f23_bin_attributes[] = {
|
||||
&bin_attr_eeprom,
|
||||
&bin_attr_f23_eeprom,
|
||||
NULL,
|
||||
};
|
||||
|
||||
|
|
@ -269,26 +302,63 @@ static const struct attribute_group *w1_f23_groups[] = {
|
|||
NULL,
|
||||
};
|
||||
|
||||
static struct bin_attribute *w1_f43_bin_attributes[] = {
|
||||
&bin_attr_f43_eeprom,
|
||||
NULL,
|
||||
};
|
||||
|
||||
static const struct attribute_group w1_f43_group = {
|
||||
.bin_attrs = w1_f43_bin_attributes,
|
||||
};
|
||||
|
||||
static const struct attribute_group *w1_f43_groups[] = {
|
||||
&w1_f43_group,
|
||||
NULL,
|
||||
};
|
||||
|
||||
static int w1_f23_add_slave(struct w1_slave *sl)
|
||||
{
|
||||
#ifdef CONFIG_W1_SLAVE_DS2433_CRC
|
||||
struct w1_f23_data *data;
|
||||
|
||||
data = kzalloc(sizeof(struct w1_f23_data), GFP_KERNEL);
|
||||
if (!data)
|
||||
return -ENOMEM;
|
||||
|
||||
switch (sl->family->fid) {
|
||||
case W1_EEPROM_DS2433:
|
||||
data->cfg = &config_f23;
|
||||
break;
|
||||
case W1_EEPROM_DS28EC20:
|
||||
data->cfg = &config_f43;
|
||||
break;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_W1_SLAVE_DS2433_CRC
|
||||
if (data->cfg->page_count > W1_VALIDCRC_MAX) {
|
||||
dev_err(&sl->dev, "page count too big for crc bitmap\n");
|
||||
kfree(data);
|
||||
return -EINVAL;
|
||||
}
|
||||
data->memory = kzalloc(data->cfg->eeprom_size, GFP_KERNEL);
|
||||
if (!data->memory) {
|
||||
kfree(data);
|
||||
return -ENOMEM;
|
||||
}
|
||||
bitmap_zero(data->validcrc, data->cfg->page_count);
|
||||
#endif /* CONFIG_W1_SLAVE_DS2433_CRC */
|
||||
sl->family_data = data;
|
||||
|
||||
#endif /* CONFIG_W1_SLAVE_DS2433_CRC */
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void w1_f23_remove_slave(struct w1_slave *sl)
|
||||
{
|
||||
#ifdef CONFIG_W1_SLAVE_DS2433_CRC
|
||||
kfree(sl->family_data);
|
||||
struct w1_f23_data *data = sl->family_data;
|
||||
sl->family_data = NULL;
|
||||
#endif /* CONFIG_W1_SLAVE_DS2433_CRC */
|
||||
#ifdef CONFIG_W1_SLAVE_DS2433_CRC
|
||||
kfree(data->memory);
|
||||
#endif /* CONFIG_W1_SLAVE_DS2433_CRC */
|
||||
kfree(data);
|
||||
}
|
||||
|
||||
static const struct w1_family_ops w1_f23_fops = {
|
||||
|
|
@ -297,13 +367,53 @@ static const struct w1_family_ops w1_f23_fops = {
|
|||
.groups = w1_f23_groups,
|
||||
};
|
||||
|
||||
static const struct w1_family_ops w1_f43_fops = {
|
||||
.add_slave = w1_f23_add_slave,
|
||||
.remove_slave = w1_f23_remove_slave,
|
||||
.groups = w1_f43_groups,
|
||||
};
|
||||
|
||||
static struct w1_family w1_family_23 = {
|
||||
.fid = W1_EEPROM_DS2433,
|
||||
.fops = &w1_f23_fops,
|
||||
};
|
||||
module_w1_family(w1_family_23);
|
||||
|
||||
static struct w1_family w1_family_43 = {
|
||||
.fid = W1_EEPROM_DS28EC20,
|
||||
.fops = &w1_f43_fops,
|
||||
};
|
||||
|
||||
static int __init w1_ds2433_init(void)
|
||||
{
|
||||
int err;
|
||||
|
||||
err = w1_register_family(&w1_family_23);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
err = w1_register_family(&w1_family_43);
|
||||
if (err)
|
||||
goto err_43;
|
||||
|
||||
return 0;
|
||||
|
||||
err_43:
|
||||
w1_unregister_family(&w1_family_23);
|
||||
return err;
|
||||
}
|
||||
|
||||
static void __exit w1_ds2433_exit(void)
|
||||
{
|
||||
w1_unregister_family(&w1_family_23);
|
||||
w1_unregister_family(&w1_family_43);
|
||||
}
|
||||
|
||||
module_init(w1_ds2433_init);
|
||||
module_exit(w1_ds2433_exit);
|
||||
|
||||
MODULE_AUTHOR("Ben Gardner <bgardner@wabtec.com>");
|
||||
MODULE_DESCRIPTION("w1 family 23 driver for DS2433, 4kb EEPROM");
|
||||
MODULE_AUTHOR("Marc Ferland <marc.ferland@sonatest.com>");
|
||||
MODULE_DESCRIPTION("w1 family 23/43 driver for DS2433 (4kb) and DS28EC20 (20kb)");
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_ALIAS("w1-family-" __stringify(W1_EEPROM_DS2433));
|
||||
MODULE_ALIAS("w1-family-" __stringify(W1_EEPROM_DS28EC20));
|
||||
|
|
|
|||
|
|
@ -1,22 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* w1-gpio interface to platform code
|
||||
*
|
||||
* Copyright (C) 2007 Ville Syrjala <syrjala@sci.fi>
|
||||
*/
|
||||
#ifndef _LINUX_W1_GPIO_H
|
||||
#define _LINUX_W1_GPIO_H
|
||||
|
||||
struct gpio_desc;
|
||||
|
||||
/**
|
||||
* struct w1_gpio_platform_data - Platform-dependent data for w1-gpio
|
||||
*/
|
||||
struct w1_gpio_platform_data {
|
||||
struct gpio_desc *gpiod;
|
||||
struct gpio_desc *pullup_gpiod;
|
||||
void (*enable_external_pullup)(int enable);
|
||||
unsigned int pullup_duration;
|
||||
};
|
||||
|
||||
#endif /* _LINUX_W1_GPIO_H */
|
||||
Loading…
Reference in New Issue
Block a user