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mvebu dt changes for v3.15 (incremental pull #3)

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- mvebu
     - merge armada 375, 380, 385 boards (mvebu/dt-3xx)
 
  - kirkwood
     - Add many Synology NAS boards
     - add board HP T5325
     - add L2 cache node
     - add system-controller node
     - add audio node
 
  - dove
     - add pinctrl and global-config register
 
 Depends:
  - tags/mvebu-dt-fixes-3.14 (mvebu/dt-fixes)
     - removed dove PMU interrupt controller
 
 Conflicts:
  - mvebu/soc (arch/arm/boot/dts/Makefile)
     - add/add conflict.
     - move CONFIG_ARCH_LPC32XX to alphabetical order (after KIRKWOOD)
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Merge tag 'mvebu-dt-3.15-3' of git://git.infradead.org/linux-mvebu into next/dt

Merge "mvebu dt changes for v3.15 (incremental pull #3)" from Jason Cooper:

 - mvebu
    - merge armada 375, 380, 385 boards (mvebu/dt-3xx)

 - kirkwood
    - Add many Synology NAS boards
    - add board HP T5325
    - add L2 cache node
    - add system-controller node
    - add audio node

 - dove
    - add pinctrl and global-config register

Depends:
 - tags/mvebu-dt-fixes-3.14 (mvebu/dt-fixes)
    - removed dove PMU interrupt controller

Conflicts:
 - mvebu/soc (arch/arm/boot/dts/Makefile)
    - add/add conflict.
    - move CONFIG_ARCH_LPC32XX to alphabetical order (after KIRKWOOD)

* tag 'mvebu-dt-3.15-3' of git://git.infradead.org/linux-mvebu:
  ARM: kirkwood: Add dts file describing HP T5325 thin client
  ARM: kirkwood: Add i2c alias so setting bus number
  ARM: kirkwood: Add audio node to kirkwood.dtsi
  ARM: mvebu: select dtbs from MACH_ARMADA_*
  ARM: dove: add global-config register node
  ARM: dove: add additional pinctrl registers
  ARM: mvebu: Instantiate system controller in kirkwood.dtsi
  ARM: kirkwood: Instantiate L2 cache from DT.
  ARM: mvebu: use macros for interrupt flags on Armada 375/38x
  ARM: mvebu: use GIC_{SPI,PPI} in Armada 375/38x DTs
  ARM: mvebu: use C preprocessor include for Armada 375/38x DTs
  ARM: Kirkwood: Add support for many Synology NAS devices
  DT: i2c: Trivial: Add sii,s35390a
  DT: Vendor prefixes: Add ricoh, qnap, sii and synology
  ARM: dove: dt: revert PMU interrupt controller node
  ARM: mvebu: add Device Tree for the Armada 385 DB board
  ARM: mvebu: add Device Tree description of the Armada 380/385 SoCs
  ARM: mvebu: add Device Tree for the Armada 375 DB board
  ARM: mvebu: add Device Tree description of the Armada 375 SoC
  ARM: mvebu: dt: add missing alias 'eth3' on Armada XP mv78260

Conflicts:
	Documentation/devicetree/bindings/vendor-prefixes.txt
	arch/arm/boot/dts/Makefile

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2014-03-17 11:02:46 +01:00
commit e887ae25b0
30 changed files with 3185 additions and 25 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
Documentation/devicetree/bindings/i2c/trivial-devices.txt
View File

@ -58,6 +58,7 @@ plx,pex8648 48-Lane, 12-Port PCI Express Gen 2 (5.0 GT/s) Switch
ramtron,24c64 i2c serial eeprom (24cxx)
ricoh,rs5c372a I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC
samsung,24ad0xd1 S524AD0XF1 (128K/256K-bit Serial EEPROM for Low Power)
sii,s35390a 2-wire CMOS real-time clock
st-micro,24c256 i2c serial eeprom (24cxx)
stm,m41t00 Serial Access TIMEKEEPER
stm,m41t62 Serial real-time clock (RTC) with alarm

4
Documentation/devicetree/bindings/vendor-prefixes.txt
View File

@ -70,10 +70,12 @@ picochip Picochip Ltd
powervr PowerVR (deprecated, use img)
qca Qualcomm Atheros, Inc.
qcom Qualcomm Technologies, Inc
qnap QNAP Systems, Inc.
ralink Mediatek/Ralink Technology Corp.
ramtron Ramtron International
realtek Realtek Semiconductor Corp.
renesas Renesas Electronics Corporation
ricoh Ricoh Co. Ltd.
rockchip Fuzhou Rockchip Electronics Co., Ltd
samsung Samsung Semiconductor
sbs Smart Battery System
@ -81,12 +83,14 @@ schindler Schindler
sil Silicon Image
silabs Silicon Laboratories
simtek
sii Seiko Instruments, Inc.
sirf SiRF Technology, Inc.
snps Synopsys, Inc.
spansion Spansion Inc.
st STMicroelectronics
ste ST-Ericsson
stericsson ST-Ericsson
synology Synology, Inc.
ti Texas Instruments
tlm Trusted Logic Mobility
toshiba Toshiba Corporation

44
arch/arm/boot/dts/Makefile
View File

@ -91,6 +91,18 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-b3.dtb \
kirkwood-dns325.dtb \
kirkwood-dockstar.dtb \
kirkwood-dreamplug.dtb \
kirkwood-ds109.dtb \
kirkwood-ds110jv10.dtb \
kirkwood-ds111.dtb \
kirkwood-ds209.dtb \
kirkwood-ds210.dtb \
kirkwood-ds212.dtb \
kirkwood-ds212j.dtb \
kirkwood-ds409.dtb \
kirkwood-ds409slim.dtb \
kirkwood-ds411.dtb \
kirkwood-ds411j.dtb \
kirkwood-ds411slim.dtb \
kirkwood-goflexnet.dtb \
kirkwood-guruplug-server-plus.dtb \
kirkwood-ib62x0.dtb \
@ -116,8 +128,12 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-b3.dtb \
kirkwood-rd88f6192.dtb \
kirkwood-rd88f6281-a0.dtb \
kirkwood-rd88f6281-a1.dtb \
kirkwood-rs212.dtb \
kirkwood-rs409.dtb \
kirkwood-rs411.dtb \
kirkwood-sheevaplug.dtb \
kirkwood-sheevaplug-esata.dtb \
kirkwood-t5325.dtb \
kirkwood-topkick.dtb \
kirkwood-ts219-6281.dtb \
kirkwood-ts219-6282.dtb \
@ -125,17 +141,6 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-b3.dtb \
kirkwood-ts419-6282.dtb
dtb-$(CONFIG_ARCH_MARCO) += marco-evb.dtb
dtb-$(CONFIG_ARCH_MOXART) += moxart-uc7112lx.dtb
dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \
armada-370-mirabox.dtb \
armada-370-netgear-rn102.dtb \
armada-370-netgear-rn104.dtb \
armada-370-rd.dtb \
armada-xp-axpwifiap.dtb \
armada-xp-db.dtb \
armada-xp-gp.dtb \
armada-xp-netgear-rn2120.dtb \
armada-xp-matrix.dtb \
armada-xp-openblocks-ax3-4.dtb
dtb-$(CONFIG_ARCH_MXC) += \
imx25-eukrea-mbimxsd25-baseboard.dtb \
imx25-karo-tx25.dtb \
@ -361,6 +366,23 @@ dtb-$(CONFIG_ARCH_VT8500) += vt8500-bv07.dtb \
dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \
zynq-zc706.dtb \
zynq-zed.dtb
dtb-$(CONFIG_MACH_ARMADA_370) += \
armada-370-db.dtb \
armada-370-mirabox.dtb \
armada-370-netgear-rn102.dtb \
armada-370-netgear-rn104.dtb \
armada-370-rd.dtb
dtb-$(CONFIG_MACH_ARMADA_375) += \
armada-375-db.dtb
dtb-$(CONFIG_MACH_ARMADA_38X) += \
armada-385-db.dtb
dtb-$(CONFIG_MACH_ARMADA_XP) += \
armada-xp-axpwifiap.dtb \
armada-xp-db.dtb \
armada-xp-gp.dtb \
armada-xp-netgear-rn2120.dtb \
armada-xp-matrix.dtb \
armada-xp-openblocks-ax3-4.dtb
targets += dtbs
targets += $(dtb-y)

130
arch/arm/boot/dts/armada-375-db.dts Normal file
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@ -0,0 +1,130 @@
/*
* Device Tree file for Marvell Armada 375 evaluation board
* (DB-88F6720)
*
* Copyright (C) 2014 Marvell
*
* Gregory CLEMENT <gregory.clement@free-electrons.com>
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "armada-375.dtsi"
/ {
model = "Marvell Armada 375 Development Board";
compatible = "marvell,a375-db", "marvell,armada375";
chosen {
bootargs = "console=ttyS0,115200 earlyprintk";
};
memory {
device_type = "memory";
reg = <0x00000000 0x40000000>; /* 1 GB */
};
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
internal-regs {
spi@10600 {
pinctrl-0 = <&spi0_pins>;
pinctrl-names = "default";
/*
* SPI conflicts with NAND, so we disable it
* here, and select NAND as the enabled device
* by default.
*/
status = "disabled";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q128a13";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <108000000>;
};
};
i2c@11000 {
status = "okay";
clock-frequency = <100000>;
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
};
i2c@11100 {
status = "okay";
clock-frequency = <100000>;
pinctrl-0 = <&i2c1_pins>;
pinctrl-names = "default";
};
serial@12000 {
clock-frequency = <200000000>;
status = "okay";
};
pinctrl {
sdio_st_pins: sdio-st-pins {
marvell,pins = "mpp44", "mpp45";
marvell,function = "gpio";
};
};
nand: nand@d0000 {
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
status = "okay";
num-cs = <1>;
marvell,nand-keep-config;
marvell,nand-enable-arbiter;
nand-on-flash-bbt;
partition@0 {
label = "U-Boot";
reg = <0 0x800000>;
};
partition@800000 {
label = "Linux";
reg = <0x800000 0x800000>;
};
partition@1000000 {
label = "Filesystem";
reg = <0x1000000 0x3f000000>;
};
};
mvsdio@d4000 {
pinctrl-0 = <&sdio_pins &sdio_st_pins>;
pinctrl-names = "default";
status = "okay";
cd-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
};
};
pcie-controller {
status = "okay";
/*
* The two PCIe units are accessible through
* standard PCIe slots on the board.
*/
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
pcie@2,0 {
/* Port 1, Lane 0 */
status = "okay";
};
};
};
};

464
arch/arm/boot/dts/armada-375.dtsi Normal file
View File

@ -0,0 +1,464 @@
/*
* Device Tree Include file for Marvell Armada 375 family SoC
*
* Copyright (C) 2014 Marvell
*
* Gregory CLEMENT <gregory.clement@free-electrons.com>
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include "skeleton.dtsi"
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
/ {
model = "Marvell Armada 375 family SoC";
compatible = "marvell,armada375";
aliases {
gpio0 = &gpio0;
gpio1 = &gpio1;
gpio2 = &gpio2;
};
clocks {
/* 2 GHz fixed main PLL */
mainpll: mainpll {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <2000000000>;
};
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <1>;
};
};
soc {
compatible = "marvell,armada375-mbus", "marvell,armada370-mbus", "simple-bus";
#address-cells = <2>;
#size-cells = <1>;
controller = <&mbusc>;
interrupt-parent = <&gic>;
pcie-mem-aperture = <0xe0000000 0x8000000>;
pcie-io-aperture = <0xe8000000 0x100000>;
bootrom {
compatible = "marvell,bootrom";
reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
};
devbus-bootcs {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
devbus-cs0 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
devbus-cs1 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
devbus-cs2 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
devbus-cs3 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
internal-regs {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
L2: cache-controller@8000 {
compatible = "arm,pl310-cache";
reg = <0x8000 0x1000>;
cache-unified;
cache-level = <2>;
};
timer@c600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0xc600 0x20>;
interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
clocks = <&coreclk 2>;
};
gic: interrupt-controller@d000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#size-cells = <0>;
interrupt-controller;
reg = <0xd000 0x1000>,
<0xc100 0x100>;
};
spi0: spi@10600 {
compatible = "marvell,orion-spi";
reg = <0x10600 0x50>;
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&coreclk 0>;
status = "disabled";
};
spi1: spi@10680 {
compatible = "marvell,orion-spi";
reg = <0x10680 0x50>;
#address-cells = <1>;
#size-cells = <0>;
cell-index = <1>;
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&coreclk 0>;
status = "disabled";
};
i2c0: i2c@11000 {
compatible = "marvell,mv64xxx-i2c";
reg = <0x11000 0x20>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
timeout-ms = <1000>;
clocks = <&coreclk 0>;
status = "disabled";
};
i2c1: i2c@11100 {
compatible = "marvell,mv64xxx-i2c";
reg = <0x11100 0x20>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
timeout-ms = <1000>;
clocks = <&coreclk 0>;
status = "disabled";
};
serial@12000 {
compatible = "snps,dw-apb-uart";
reg = <0x12000 0x100>;
reg-shift = <2>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <1>;
status = "disabled";
};
serial@12100 {
compatible = "snps,dw-apb-uart";
reg = <0x12100 0x100>;
reg-shift = <2>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <1>;
status = "disabled";
};
pinctrl {
compatible = "marvell,mv88f6720-pinctrl";
reg = <0x18000 0x24>;
i2c0_pins: i2c0-pins {
marvell,pins = "mpp14", "mpp15";
marvell,function = "i2c0";
};
i2c1_pins: i2c1-pins {
marvell,pins = "mpp61", "mpp62";
marvell,function = "i2c1";
};
nand_pins: nand-pins {
marvell,pins = "mpp0", "mpp1", "mpp2",
"mpp3", "mpp4", "mpp5",
"mpp6", "mpp7", "mpp8",
"mpp9", "mpp10", "mpp11",
"mpp12", "mpp13";
marvell,function = "nand";
};
sdio_pins: sdio-pins {
marvell,pins = "mpp24", "mpp25", "mpp26",
"mpp27", "mpp28", "mpp29";
marvell,function = "sd";
};
spi0_pins: spi0-pins {
marvell,pins = "mpp0", "mpp1", "mpp4",
"mpp5", "mpp8", "mpp9";
marvell,function = "spi0";
};
};
gpio0: gpio@18100 {
compatible = "marvell,orion-gpio";
reg = <0x18100 0x40>;
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
};
gpio1: gpio@18140 {
compatible = "marvell,orion-gpio";
reg = <0x18140 0x40>;
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
};
gpio2: gpio@18180 {
compatible = "marvell,orion-gpio";
reg = <0x18180 0x40>;
ngpios = <3>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
};
system-controller@18200 {
compatible = "marvell,armada-375-system-controller";
reg = <0x18200 0x100>;
};
gateclk: clock-gating-control@18220 {
compatible = "marvell,armada-375-gating-clock";
reg = <0x18220 0x4>;
clocks = <&coreclk 0>;
#clock-cells = <1>;
};
mbusc: mbus-controller@20000 {
compatible = "marvell,mbus-controller";
reg = <0x20000 0x100>, <0x20180 0x20>;
};
mpic: interrupt-controller@20000 {
compatible = "marvell,mpic";
reg = <0x20a00 0x2d0>, <0x21070 0x58>;
#interrupt-cells = <1>;
#size-cells = <1>;
interrupt-controller;
msi-controller;
interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
};
timer@20300 {
compatible = "marvell,armada-375-timer", "marvell,armada-370-timer";
reg = <0x20300 0x30>, <0x21040 0x30>;
interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
<&mpic 5>,
<&mpic 6>;
clocks = <&coreclk 0>;
};
xor@60800 {
compatible = "marvell,orion-xor";
reg = <0x60800 0x100
0x60A00 0x100>;
clocks = <&gateclk 22>;
status = "okay";
xor00 {
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
dmacap,memcpy;
dmacap,xor;
};
xor01 {
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
dmacap,memcpy;
dmacap,xor;
dmacap,memset;
};
};
xor@60900 {
compatible = "marvell,orion-xor";
reg = <0x60900 0x100
0x60b00 0x100>;
clocks = <&gateclk 23>;
status = "okay";
xor10 {
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
dmacap,memcpy;
dmacap,xor;
};
xor11 {
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
dmacap,memcpy;
dmacap,xor;
dmacap,memset;
};
};
sata@a0000 {
compatible = "marvell,orion-sata";
reg = <0xa0000 0x5000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gateclk 14>, <&gateclk 20>;
clock-names = "0", "1";
status = "disabled";
};
nand@d0000 {
compatible = "marvell,armada370-nand";
reg = <0xd0000 0x54>;
#address-cells = <1>;
#size-cells = <1>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gateclk 11>;
status = "disabled";
};
mvsdio@d4000 {
compatible = "marvell,orion-sdio";
reg = <0xd4000 0x200>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gateclk 17>;
bus-width = <4>;
cap-sdio-irq;
cap-sd-highspeed;
cap-mmc-highspeed;
status = "disabled";
};
coreclk: mvebu-sar@e8204 {
compatible = "marvell,armada-375-core-clock";
reg = <0xe8204 0x04>;
#clock-cells = <1>;
};
coredivclk: corediv-clock@e8250 {
compatible = "marvell,armada-375-corediv-clock";
reg = <0xe8250 0xc>;
#clock-cells = <1>;
clocks = <&mainpll>;
clock-output-names = "nand";
};
};
pcie-controller {
compatible = "marvell,armada-370-pcie";
status = "disabled";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
msi-parent = <&mpic>;
bus-range = <0x00 0xff>;
ranges =
<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0 MEM */
0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0 IO */
0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1 MEM */
0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1 IO */>;
pcie@1,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
reg = <0x0800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0x81000000 0 0 0x81000000 0x1 0 1 0>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 5>;
status = "disabled";
};
pcie@2,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
reg = <0x1000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
0x81000000 0 0 0x81000000 0x2 0 1 0>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <1>;
clocks = <&gateclk 6>;
status = "disabled";
};
};
};
};

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/*
* Device Tree Include file for Marvell Armada 380 SoC.
*
* Copyright (C) 2014 Marvell
*
* Lior Amsalem <alior@marvell.com>
* Gregory CLEMENT <gregory.clement@free-electrons.com>
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include "armada-38x.dtsi"
/ {
model = "Marvell Armada 380 family SoC";
compatible = "marvell,armada380", "marvell,armada38x";
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
};
};
soc {
internal-regs {
pinctrl {
compatible = "marvell,mv88f6810-pinctrl";
reg = <0x18000 0x20>;
};
};
pcie-controller {
compatible = "marvell,armada-370-pcie";
status = "disabled";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
msi-parent = <&mpic>;
bus-range = <0x00 0xff>;
ranges =
<0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */
0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */
0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */>;
/* x1 port */
pcie@1,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
reg = <0x0800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0x81000000 0 0 0x81000000 0x1 0 1 0>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 8>;
status = "disabled";
};
/* x1 port */
pcie@2,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
reg = <0x1000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
0x81000000 0 0 0x81000000 0x2 0 1 0>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
marvell,pcie-port = <1>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 5>;
status = "disabled";
};
/* x1 port */
pcie@3,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
reg = <0x1000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
0x81000000 0 0 0x81000000 0x3 0 1 0>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
marvell,pcie-port = <2>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 6>;
status = "disabled";
};
};
};
};

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/*
* Device Tree file for Marvell Armada 385 evaluation board
* (DB-88F6820)
*
* Copyright (C) 2014 Marvell
*
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
/dts-v1/;
#include "armada-385.dtsi"
/ {
model = "Marvell Armada 385 Development Board";
compatible = "marvell,a385-db", "marvell,armada385", "marvell,armada38x";
chosen {
bootargs = "console=ttyS0,115200 earlyprintk";
};
memory {
device_type = "memory";
reg = <0x00000000 0x10000000>; /* 256 MB */
};
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
internal-regs {
spi@10600 {
status = "okay";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "w25q32";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <108000000>;
};
};
i2c@11000 {
status = "okay";
clock-frequency = <100000>;
};
i2c@11100 {
status = "okay";
clock-frequency = <100000>;
};
serial@12000 {
clock-frequency = <200000000>;
status = "okay";
};
ethernet@30000 {
status = "okay";
phy = <&phy1>;
phy-mode = "rgmii";
};
ethernet@70000 {
status = "okay";
phy = <&phy0>;
phy-mode = "rgmii";
};
mdio {
phy0: ethernet-phy@0 {
reg = <0>;
};
phy1: ethernet-phy@1 {
reg = <1>;
};
};
};
pcie-controller {
status = "okay";
/*
* The two PCIe units are accessible through
* standard PCIe slots on the board.
*/
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
pcie@2,0 {
/* Port 1, Lane 0 */
status = "okay";
};
};
};
};

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/*
* Device Tree Include file for Marvell Armada 385 SoC.
*
* Copyright (C) 2014 Marvell
*
* Lior Amsalem <alior@marvell.com>
* Gregory CLEMENT <gregory.clement@free-electrons.com>
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include "armada-38x.dtsi"
/ {
model = "Marvell Armada 385 family SoC";
compatible = "marvell,armada385", "marvell,armada38x";
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <1>;
};
};
soc {
internal-regs {
pinctrl {
compatible = "marvell,mv88f6820-pinctrl";
reg = <0x18000 0x20>;
};
};
pcie-controller {
compatible = "marvell,armada-370-pcie";
status = "disabled";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
msi-parent = <&mpic>;
bus-range = <0x00 0xff>;
ranges =
<0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */
0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */
0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */
0x82000000 0x4 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 3 MEM */
0x81000000 0x4 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 3 IO */>;
/*
* This port can be either x4 or x1. When
* configured in x4 by the bootloader, then
* pcie@4,0 is not available.
*/
pcie@1,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
reg = <0x0800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0x81000000 0 0 0x81000000 0x1 0 1 0>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 8>;
status = "disabled";
};
/* x1 port */
pcie@2,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
reg = <0x1000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
0x81000000 0 0 0x81000000 0x2 0 1 0>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
marvell,pcie-port = <1>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 5>;
status = "disabled";
};
/* x1 port */
pcie@3,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
reg = <0x1000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
0x81000000 0 0 0x81000000 0x3 0 1 0>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
marvell,pcie-port = <2>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 6>;
status = "disabled";
};
/*
* x1 port only available when pcie@1,0 is
* configured as a x1 port
*/
pcie@4,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
reg = <0x1000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
0x81000000 0 0 0x81000000 0x4 0 1 0>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
marvell,pcie-port = <3>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 7>;
status = "disabled";
};
};
};
};

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/*
* Device Tree Include file for Marvell Armada 38x family of SoCs.
*
* Copyright (C) 2014 Marvell
*
* Lior Amsalem <alior@marvell.com>
* Gregory CLEMENT <gregory.clement@free-electrons.com>
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include "skeleton.dtsi"
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
/ {
model = "Marvell Armada 38x family SoC";
compatible = "marvell,armada38x";
aliases {
gpio0 = &gpio0;
gpio1 = &gpio1;
eth0 = &eth0;
eth1 = &eth1;
eth2 = &eth2;
};
soc {
compatible = "marvell,armada380-mbus", "marvell,armada370-mbus",
"simple-bus";
#address-cells = <2>;
#size-cells = <1>;
controller = <&mbusc>;
interrupt-parent = <&gic>;
pcie-mem-aperture = <0xe0000000 0x8000000>;
pcie-io-aperture = <0xe8000000 0x100000>;
bootrom {
compatible = "marvell,bootrom";
reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
};
devbus-bootcs {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
devbus-cs0 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
devbus-cs1 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
devbus-cs2 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
devbus-cs3 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
internal-regs {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
L2: cache-controller@8000 {
compatible = "arm,pl310-cache";
reg = <0x8000 0x1000>;
cache-unified;
cache-level = <2>;
};
timer@c600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0xc600 0x20>;
interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
clocks = <&coreclk 2>;
};
gic: interrupt-controller@d000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#size-cells = <0>;
interrupt-controller;
reg = <0xd000 0x1000>,
<0xc100 0x100>;
};
spi0: spi@10600 {
compatible = "marvell,orion-spi";
reg = <0x10600 0x50>;
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&coreclk 0>;
status = "disabled";
};
spi1: spi@10680 {
compatible = "marvell,orion-spi";
reg = <0x10680 0x50>;
#address-cells = <1>;
#size-cells = <0>;
cell-index = <1>;
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&coreclk 0>;
status = "disabled";
};
i2c0: i2c@11000 {
compatible = "marvell,mv64xxx-i2c";
reg = <0x11000 0x20>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
timeout-ms = <1000>;
clocks = <&coreclk 0>;
status = "disabled";
};
i2c1: i2c@11100 {
compatible = "marvell,mv64xxx-i2c";
reg = <0x11100 0x20>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
timeout-ms = <1000>;
clocks = <&coreclk 0>;
status = "disabled";
};
serial@12000 {
compatible = "snps,dw-apb-uart";
reg = <0x12000 0x100>;
reg-shift = <2>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <1>;
status = "disabled";
};
serial@12100 {
compatible = "snps,dw-apb-uart";
reg = <0x12100 0x100>;
reg-shift = <2>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <1>;
status = "disabled";
};
pinctrl {
compatible = "marvell,mv88f6820-pinctrl";
reg = <0x18000 0x20>;
};
gpio0: gpio@18100 {
compatible = "marvell,orion-gpio";
reg = <0x18100 0x40>;
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
};
gpio1: gpio@18140 {
compatible = "marvell,orion-gpio";
reg = <0x18140 0x40>;
ngpios = <28>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
};
system-controller@18200 {
compatible = "marvell,armada-380-system-controller",
"marvell,armada-370-xp-system-controller";
reg = <0x18200 0x100>;
};
gateclk: clock-gating-control@18220 {
compatible = "marvell,armada-380-gating-clock";
reg = <0x18220 0x4>;
clocks = <&coreclk 0>;
#clock-cells = <1>;
};
coreclk: mvebu-sar@18600 {
compatible = "marvell,armada-380-core-clock";
reg = <0x18600 0x04>;
#clock-cells = <1>;
};
mbusc: mbus-controller@20000 {
compatible = "marvell,mbus-controller";
reg = <0x20000 0x100>, <0x20180 0x20>;
};
mpic: interrupt-controller@20000 {
compatible = "marvell,mpic";
reg = <0x20a00 0x2d0>, <0x21070 0x58>;
#interrupt-cells = <1>;
#size-cells = <1>;
interrupt-controller;
msi-controller;
interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
};
timer@20300 {
compatible = "marvell,armada-380-timer",
"marvell,armada-xp-timer";
reg = <0x20300 0x30>, <0x21040 0x30>;
interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
<&mpic 5>,
<&mpic 6>;
clocks = <&coreclk 2>, <&refclk>;
clock-names = "nbclk", "fixed";
};
eth1: ethernet@30000 {
compatible = "marvell,armada-370-neta";
reg = <0x30000 0x4000>;
interrupts-extended = <&mpic 10>;
clocks = <&gateclk 3>;
status = "disabled";
};
eth2: ethernet@34000 {
compatible = "marvell,armada-370-neta";
reg = <0x34000 0x4000>;
interrupts-extended = <&mpic 12>;
clocks = <&gateclk 2>;
status = "disabled";
};
xor@60800 {
compatible = "marvell,orion-xor";
reg = <0x60800 0x100
0x60a00 0x100>;
clocks = <&gateclk 22>;
status = "okay";
xor00 {
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
dmacap,memcpy;
dmacap,xor;
};
xor01 {
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
dmacap,memcpy;
dmacap,xor;
dmacap,memset;
};
};
xor@60900 {
compatible = "marvell,orion-xor";
reg = <0x60900 0x100
0x60b00 0x100>;
clocks = <&gateclk 28>;
status = "okay";
xor10 {
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
dmacap,memcpy;
dmacap,xor;
};
xor11 {
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
dmacap,memcpy;
dmacap,xor;
dmacap,memset;
};
};
eth0: ethernet@70000 {
compatible = "marvell,armada-370-neta";
reg = <0x70000 0x4000>;
interrupts-extended = <&mpic 8>;
clocks = <&gateclk 4>;
status = "disabled";
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "marvell,orion-mdio";
reg = <0x72004 0x4>;
};
};
};
clocks {
/* 25 MHz reference crystal */
refclk: oscillator {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
};
};

3
arch/arm/boot/dts/armada-xp-mv78260.dtsi
View File

@ -23,6 +23,7 @@
gpio0 = &gpio0;
gpio1 = &gpio1;
gpio2 = &gpio2;
eth3 = &eth3;
};
cpus {
@ -291,7 +292,7 @@
interrupts = <91>;
};
ethernet@34000 {
eth3: ethernet@34000 {
compatible = "marvell,armada-370-neta";
reg = <0x34000 0x4000>;
interrupts = <14>;

21
arch/arm/boot/dts/dove.dtsi
View File

@ -387,18 +387,11 @@
#clock-cells = <1>;
};
pmu_intc: pmu-interrupt-ctrl@d0050 {
compatible = "marvell,dove-pmu-intc";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0xd0050 0x8>;
interrupts = <33>;
marvell,#interrupts = <7>;
};
pinctrl: pin-ctrl@d0200 {
compatible = "marvell,dove-pinctrl";
reg = <0xd0200 0x10>;
reg = <0xd0200 0x14>,
<0xd0440 0x04>,
<0xd802c 0x08>;
clocks = <&gate_clk 22>;
pmx_gpio_0: pmx-gpio-0 {
@ -618,8 +611,12 @@
rtc: real-time-clock@d8500 {
compatible = "marvell,orion-rtc";
reg = <0xd8500 0x20>;
interrupt-parent = <&pmu_intc>;
interrupts = <5>;
};
gconf: global-config@e802c {
compatible = "marvell,dove-global-config",
"syscon";
reg = <0xe802c 0x14>;
};
gpio2: gpio-ctrl@e8400 {

41
arch/arm/boot/dts/kirkwood-ds109.dts Normal file
View File

@ -0,0 +1,41 @@
/*
* Andrew Lunn <andrew@lunn.ch>
* Ben Peddell <klightspeed@killerwolves.net>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
/dts-v1/;
#include "kirkwood.dtsi"
#include "kirkwood-6281.dtsi"
#include "kirkwood-synology.dtsi"
/ {
model = "Synology DS109, DS110, DS110jv20";
compatible = "synology,ds109", "synology,ds110jv20",
"synology,ds110", "marvell,kirkwood";
memory {
device_type = "memory";
reg = <0x00000000 0x8000000>;
};
chosen {
bootargs = "console=ttyS0,115200n8";
};
gpio-fan-150-32-35 {
status = "okay";
};
gpio-leds-hdd-21-1 {
status = "okay";
};
};
&rs5c372 {
status = "okay";
};

41
arch/arm/boot/dts/kirkwood-ds110jv10.dts Normal file
View File

@ -0,0 +1,41 @@
/*
* Andrew Lunn <andrew@lunn.ch>
* Ben Peddell <klightspeed@killerwolves.net>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
/dts-v1/;
#include "kirkwood.dtsi"
#include "kirkwood-6281.dtsi"
#include "kirkwood-synology.dtsi"
/ {
model = "Synology DS110j v10 and v30";
compatible = "synology,ds110jv10", "synology,ds110jv30",
"marvell,kirkwood";
memory {
device_type = "memory";
reg = <0x00000000 0x8000000>;
};
chosen {
bootargs = "console=ttyS0,115200n8";
};
gpio-fan-150-32-35 {
status = "okay";
};
gpio-leds-hdd-21-1 {
status = "okay";
};
};
&s35390a {
status = "okay";
};

44
arch/arm/boot/dts/kirkwood-ds111.dts Normal file
View File

@ -0,0 +1,44 @@
/*
* Andrew Lunn <andrew@lunn.ch>
* Ben Peddell <klightspeed@killerwolves.net>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
/dts-v1/;
#include "kirkwood.dtsi"
#include "kirkwood-6282.dtsi"
#include "kirkwood-synology.dtsi"
/ {
model = "Synology DS111";
compatible = "synology,ds111", "marvell,kirkwood";
memory {
device_type = "memory";
reg = <0x00000000 0x8000000>;
};
chosen {
bootargs = "console=ttyS0,115200n8";
};
gpio-fan-100-15-35-1 {
status = "okay";
};
gpio-leds-hdd-21-1 {
status = "okay";
};
};
&s35390a {
status = "okay";
};
&pcie2 {
status = "okay";
};

48
arch/arm/boot/dts/kirkwood-ds112.dts Normal file
View File

@ -0,0 +1,48 @@
/*
* Andrew Lunn <andrew@lunn.ch>
* Ben Peddell <klightspeed@killerwolves.net>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
/dts-v1/;
#include "kirkwood.dtsi"
#include "kirkwood-6282.dtsi"
#include "kirkwood-synology.dtsi"
/ {
model = "Synology DS111";
compatible = "synology,ds111", "marvell,kirkwood";
memory {
device_type = "memory";
reg = <0x00000000 0x8000000>;
};
chosen {
bootargs = "console=ttyS0,115200n8";
};
gpio-fan-100-15-35-1 {
status = "okay";
};
gpio-leds-21-2 {
status = "okay";
};
regulators-hdd-30 {
status = "okay";
};
};
&s35390a {
status = "okay";
};
&pcie2 {
status = "okay";
};

44
arch/arm/boot/dts/kirkwood-ds209.dts Normal file
View File

@ -0,0 +1,44 @@
/*
* Andrew Lunn <andrew@lunn.ch>
* Ben Peddell <klightspeed@killerwolves.net>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
/dts-v1/;
#include "kirkwood.dtsi"
#include "kirkwood-6281.dtsi"
#include "kirkwood-synology.dtsi"
/ {
model = "Synology DS209";
compatible = "synology,ds209", "marvell,kirkwood";
memory {
device_type = "memory";
reg = <0x00000000 0x8000000>;
};
chosen {
bootargs = "console=ttyS0,115200n8";
};
gpio-fan-150-32-35 {
status = "okay";
};
gpio-leds-hdd-21-2 {
status = "okay";
};
regulators-hdd-31 {
status = "okay";
};
};
&rs5c372 {
status = "okay";
};

46
arch/arm/boot/dts/kirkwood-ds210.dts Normal file
View File

@ -0,0 +1,46 @@
/*
* Andrew Lunn <andrew@lunn.ch>
* Ben Peddell <klightspeed@killerwolves.net>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
/dts-v1/;
#include "kirkwood.dtsi"
#include "kirkwood-6281.dtsi"
#include "kirkwood-synology.dtsi"
/ {
model = "Synology DS210 v10, v20, v30, DS211j";
compatible = "synology,ds210jv10", "synology,ds210jv20",
"synology,ds210jv30", "synology,ds211j",
"marvell,kirkwood";
memory {
device_type = "memory";
reg = <0x00000000 0x8000000>;
};
chosen {
bootargs = "console=ttyS0,115200n8";
};
gpio-fan-150-32-35 {
status = "okay";
};
gpio-leds-hdd-21-2 {
status = "okay";
};
regulators-hdd-31 {
status = "okay";
};
};
&s35390a {
status = "okay";
};

47
arch/arm/boot/dts/kirkwood-ds212.dts Normal file
View File

@ -0,0 +1,47 @@
/*
* Andrew Lunn <andrew@lunn.ch>
* Ben Peddell <klightspeed@killerwolves.net>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
/dts-v1/;
#include "kirkwood.dtsi"
#include "kirkwood-6282.dtsi"
#include "kirkwood-synology.dtsi"
/ {
model = "Synology DS212, DS212p v10, v20, DS213air v10, DS213 v10";
compatible = "synology,ds212", "synology,ds212pv10",
"synology,ds212pv10", "synology,ds212pv20",
"synology,ds213airv10", "synology,ds213v10",
"marvell,kirkwood";
memory {
device_type = "memory";
reg = <0x00000000 0x8000000>;
};
chosen {
bootargs = "console=ttyS0,115200n8";
};
gpio-fan-100-15-35-1 {
status = "okay";
};
gpio-leds-hdd-21-2 {
status = "okay";
};
};
&s35390a {
status = "okay";
};
&pcie2 {
status = "okay";
};

41
arch/arm/boot/dts/kirkwood-ds212j.dts Normal file
View File

@ -0,0 +1,41 @@
/*
* Andrew Lunn <andrew@lunn.ch>
* Ben Peddell <klightspeed@killerwolves.net>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
/dts-v1/;
#include "kirkwood.dtsi"
#include "kirkwood-6281.dtsi"
#include "kirkwood-synology.dtsi"
/ {
model = "Synology DS212j v10, v20";
compatible = "synology,ds212jv10", "synology,ds212jv20",
"marvell,kirkwood";
memory {
device_type = "memory";
reg = <0x00000000 0x8000000>;
};
chosen {
bootargs = "console=ttyS0,115200n8";
};
gpio-fan-100-32-35 {
status = "okay";
};
gpio-leds-hdd-21-2 {
status = "okay";
};
};
&s35390a {
status = "okay";
};

48
arch/arm/boot/dts/kirkwood-ds409.dts Normal file
View File

@ -0,0 +1,48 @@
/*
* Andrew Lunn <andrew@lunn.ch>
* Ben Peddell <klightspeed@killerwolves.net>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
/dts-v1/;
#include "kirkwood.dtsi"
#include "kirkwood-6281.dtsi"
#include "kirkwood-synology.dtsi"
/ {
model = "Synology DS409, DS410j";
compatible = "synology,ds409", "synology,ds410j", "marvell,kirkwood";
memory {
device_type = "memory";
reg = <0x00000000 0x8000000>;
};
chosen {
bootargs = "console=ttyS0,115200n8";
};
gpio-fan-150-15-18 {
status = "okay";
};
gpio-leds-hdd-36 {
status = "okay";
};
gpio-leds-alarm-12 {
status = "okay";
};
};
&eth1 {
status = "okay";
};
&rs5c372 {
status = "okay";
};

40
arch/arm/boot/dts/kirkwood-ds409slim.dts Normal file
View File

@ -0,0 +1,40 @@
/*
* Andrew Lunn <andrew@lunn.ch>
* Ben Peddell <klightspeed@killerwolves.net>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
/dts-v1/;
#include "kirkwood.dtsi"
#include "kirkwood-6281.dtsi"
#include "kirkwood-synology.dtsi"
/ {
model = "Synology 409slim";
compatible = "synology,ds409slim", "marvell,kirkwood";
memory {
device_type = "memory";
reg = <0x00000000 0x8000000>;
};
chosen {
bootargs = "console=ttyS0,115200n8";
};
gpio-fan-150-32-35 {
status = "okay";
};
gpio-leds-hdd-20 {
status = "okay";
};
};
&rs5c372 {
status = "okay";
};

52
arch/arm/boot/dts/kirkwood-ds411.dts Normal file
View File

@ -0,0 +1,52 @@
/*
* Andrew Lunn <andrew@lunn.ch>
* Ben Peddell <klightspeed@killerwolves.net>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
/dts-v1/;
#include "kirkwood.dtsi"
#include "kirkwood-6282.dtsi"
#include "kirkwood-synology.dtsi"
/ {
model = "Synology DS411, DS413jv10";
compatible = "synology,ds411", "synology,ds413jv10", "marvell,kirkwood";
memory {
device_type = "memory";
reg = <0x00000000 0x8000000>;
};
chosen {
bootargs = "console=ttyS0,115200n8";
};
gpio-fan-100-15-35-1 {
status = "okay";
};
gpio-leds-hdd-36 {
status = "okay";
};
regulators-hdd-34 {
status = "okay";
};
};
&eth1 {
status = "okay";
};
&s35390a {
status = "okay";
};
&pcie2 {
status = "okay";
};

48
arch/arm/boot/dts/kirkwood-ds411j.dts Normal file
View File

@ -0,0 +1,48 @@
/*
* Andrew Lunn <andrew@lunn.ch>
* Ben Peddell <klightspeed@killerwolves.net>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
/dts-v1/;
#include "kirkwood.dtsi"
#include "kirkwood-6281.dtsi"
#include "kirkwood-synology.dtsi"
/ {
model = "Synology DS411j";
compatible = "synology,ds411j", "marvell,kirkwood";
memory {
device_type = "memory";
reg = <0x00000000 0x8000000>;
};
chosen {
bootargs = "console=ttyS0,115200n8";
};
gpio-fan-150-15-18 {
status = "okay";
};
gpio-leds-hdd-36 {
status = "okay";
};
gpio-leds-alarm-12 {
status = "okay";
};
};
&eth1 {
status = "okay";
};
&s35390a {
status = "okay";
};

48
arch/arm/boot/dts/kirkwood-ds411slim.dts Normal file
View File

@ -0,0 +1,48 @@
/*
* Andrew Lunn <andrew@lunn.ch>
* Ben Peddell <klightspeed@killerwolves.net>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
/dts-v1/;
#include "kirkwood.dtsi"
#include "kirkwood-6282.dtsi"
#include "kirkwood-synology.dtsi"
/ {
model = "Synology DS411slim";
compatible = "synology,ds411slim", "marvell,kirkwood";
memory {
device_type = "memory";
reg = <0x00000000 0x8000000>;
};
chosen {
bootargs = "console=ttyS0,115200n8";
};
gpio-fan-100-15-35-1 {
status = "okay";
};
gpio-leds-hdd-36 {
status = "okay";
};
};
&eth1 {
status = "okay";
};
&s35390a {
status = "okay";
};
&pcie2 {
status = "okay";
};

48
arch/arm/boot/dts/kirkwood-rs212.dts Normal file
View File

@ -0,0 +1,48 @@
/*
* Andrew Lunn <andrew@lunn.ch>
* Ben Peddell <klightspeed@killerwolves.net>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
/dts-v1/;
#include "kirkwood.dtsi"
#include "kirkwood-6282.dtsi"
#include "kirkwood-synology.dtsi"
/ {
model = "Synology RS212";
compatible = "synology,rs212", "marvell,kirkwood";
memory {
device_type = "memory";
reg = <0x00000000 0x8000000>;
};
chosen {
bootargs = "console=ttyS0,115200n8";
};
gpio-fan-100-15-35-3 {
status = "okay";
};
gpio-leds-hdd-38 {
status = "okay";
};
regulators-hdd-30-2 {
status = "okay";
};
};
&s35390a {
status = "okay";
};
&pcie2 {
status = "okay";
};

44
arch/arm/boot/dts/kirkwood-rs409.dts Normal file
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@ -0,0 +1,44 @@
/*
* Andrew Lunn <andrew@lunn.ch>
* Ben Peddell <klightspeed@killerwolves.net>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
/dts-v1/;
#include "kirkwood.dtsi"
#include "kirkwood-6281.dtsi"
#include "kirkwood-synology.dtsi"
/ {
model = "Synology RS409";
compatible = "synology,rs409", "marvell,kirkwood";
memory {
device_type = "memory";
reg = <0x00000000 0x8000000>;
};
chosen {
bootargs = "console=ttyS0,115200n8";
};
gpio-fan-150-15-18 {
status = "okay";
};
gpio-leds-hdd-36 {
status = "okay";
};
};
&eth1 {
status = "okay";
};
&rs5c372 {
status = "okay";
};

44
arch/arm/boot/dts/kirkwood-rs411.dts Normal file
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@ -0,0 +1,44 @@
/*
* Andrew Lunn <andrew@lunn.ch>
* Ben Peddell <klightspeed@killerwolves.net>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
/dts-v1/;
#include "kirkwood.dtsi"
#include "kirkwood-6282.dtsi"
#include "kirkwood-synology.dtsi"
/ {
model = "Synology RS411 RS812";
compatible = "synology,rs411", "synology,rs812", "marvell,kirkwood";
memory {
device_type = "memory";
reg = <0x00000000 0x8000000>;
};
chosen {
bootargs = "console=ttyS0,115200n8";
};
gpio-fan-100-15-35-3 {
status = "okay";
};
gpio-leds-hdd-36 {
status = "okay";
};
};
&eth1 {
status = "okay";
};
&s35390a {
status = "okay";
};

871
arch/arm/boot/dts/kirkwood-synology.dtsi Normal file
View File

@ -0,0 +1,871 @@
/*
* Nodes for Marvell 628x Synology devices
*
* Andrew Lunn <andrew@lunn.ch>
* Ben Peddell <klightspeed@killerwolves.net>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
/ {
mbus {
pcie-controller {
status = "okay";
pcie@1,0 {
status = "okay";
};
pcie2: pcie@2,0 {
status = "disabled";
};
};
};
ocp@f1000000 {
pinctrl: pinctrl@10000 {
pmx_alarmled_12: pmx-alarmled-12 {
marvell,pins = "mpp12";
marvell,function = "gpio";
};
pmx_fanctrl_15: pmx-fanctrl-15 {
marvell,pins = "mpp15";
marvell,function = "gpio";
};
pmx_fanctrl_16: pmx-fanctrl-16 {
marvell,pins = "mpp16";
marvell,function = "gpio";
};
pmx_fanctrl_17: pmx-fanctrl-17 {
marvell,pins = "mpp17";
marvell,function = "gpio";
};
pmx_fanalarm_18: pmx-fanalarm-18 {
marvell,pins = "mpp18";
marvell,function = "gpo";
};
pmx_hddled_20: pmx-hddled-20 {
marvell,pins = "mpp20";
marvell,function = "gpio";
};
pmx_hddled_21: pmx-hddled-21 {
marvell,pins = "mpp21";
marvell,function = "gpio";
};
pmx_hddled_22: pmx-hddled-22 {
marvell,pins = "mpp22";
marvell,function = "gpio";
};
pmx_hddled_23: pmx-hddled-23 {
marvell,pins = "mpp23";
marvell,function = "gpio";
};
pmx_hddled_24: pmx-hddled-24 {
marvell,pins = "mpp24";
marvell,function = "gpio";
};
pmx_hddled_25: pmx-hddled-25 {
marvell,pins = "mpp25";
marvell,function = "gpio";
};
pmx_hddled_26: pmx-hddled-26 {
marvell,pins = "mpp26";
marvell,function = "gpio";
};
pmx_hddled_27: pmx-hddled-27 {
marvell,pins = "mpp27";
marvell,function = "gpio";
};
pmx_hddled_28: pmx-hddled-28 {
marvell,pins = "mpp28";
marvell,function = "gpio";
};
pmx_hdd1_pwr_29: pmx-hdd1-pwr-29 {
marvell,pins = "mpp29";
marvell,function = "gpio";
};
pmx_hdd1_pwr_30: pmx-hdd-pwr-30 {
marvell,pins = "mpp30";
marvell,function = "gpio";
};
pmx_hdd2_pwr_31: pmx-hdd2-pwr-31 {
marvell,pins = "mpp31";
marvell,function = "gpio";
};
pmx_fanctrl_32: pmx-fanctrl-32 {
marvell,pins = "mpp32";
marvell,function = "gpio";
};
pmx_fanctrl_33: pmx-fanctrl-33 {
marvell,pins = "mpp33";
marvell,function = "gpo";
};
pmx_fanctrl_34: pmx-fanctrl-34 {
marvell,pins = "mpp34";
marvell,function = "gpio";
};
pmx_hdd2_pwr_34: pmx-hdd2-pwr-34 {
marvell,pins = "mpp34";
marvell,function = "gpio";
};
pmx_fanalarm_35: pmx-fanalarm-35 {
marvell,pins = "mpp35";
marvell,function = "gpio";
};
pmx_hddled_36: pmx-hddled-36 {
marvell,pins = "mpp36";
marvell,function = "gpio";
};
pmx_hddled_37: pmx-hddled-37 {
marvell,pins = "mpp37";
marvell,function = "gpio";
};
pmx_hddled_38: pmx-hddled-38 {
marvell,pins = "mpp38";
marvell,function = "gpio";
};
pmx_hddled_39: pmx-hddled-39 {
marvell,pins = "mpp39";
marvell,function = "gpio";
};
pmx_hddled_40: pmx-hddled-40 {
marvell,pins = "mpp40";
marvell,function = "gpio";
};
pmx_hddled_41: pmx-hddled-41 {
marvell,pins = "mpp41";
marvell,function = "gpio";
};
pmx_hddled_42: pmx-hddled-42 {
marvell,pins = "mpp42";
marvell,function = "gpio";
};
pmx_hddled_43: pmx-hddled-43 {
marvell,pins = "mpp43";
marvell,function = "gpio";
};
pmx_hddled_44: pmx-hddled-44 {
marvell,pins = "mpp44";
marvell,function = "gpio";
};
pmx_hddled_45: pmx-hddled-45 {
marvell,pins = "mpp45";
marvell,function = "gpio";
};
pmx_hdd3_pwr_44: pmx-hdd3-pwr-44 {
marvell,pins = "mpp44";
marvell,function = "gpio";
};
pmx_hdd4_pwr_45: pmx-hdd4-pwr-45 {
marvell,pins = "mpp45";
marvell,function = "gpio";
};
pmx_fanalarm_44: pmx-fanalarm-44 {
marvell,pins = "mpp44";
marvell,function = "gpio";
};
pmx_fanalarm_45: pmx-fanalarm-45 {
marvell,pins = "mpp45";
marvell,function = "gpio";
};
};
rtc@10300 {
status = "disabled";
};
spi@10600 {
status = "okay";
pinctrl-0 = <&pmx_spi>;
pinctrl-names = "default";
m25p80@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p80";
reg = <0>;
spi-max-frequency = <20000000>;
mode = <0>;
partition@00000000 {
reg = <0x00000000 0x00080000>;
label = "RedBoot";
};
partition@00080000 {
reg = <0x00080000 0x00200000>;
label = "zImage";
};
partition@00280000 {
reg = <0x00280000 0x00140000>;
label = "rd.gz";
};
partition@003c0000 {
reg = <0x003c0000 0x00010000>;
label = "vendor";
};
partition@003d0000 {
reg = <0x003d0000 0x00020000>;
label = "RedBoot config";
};
partition@003f0000 {
reg = <0x003f0000 0x00010000>;
label = "FIS directory";
};
};
};
i2c@11000 {
status = "okay";
clock-frequency = <400000>;
pinctrl-0 = <&pmx_twsi0>;
pinctrl-names = "default";
rs5c372: rs5c372@32 {
status = "disabled";
compatible = "ricoh,rs5c372";
reg = <0x32>;
};
s35390a: s35390a@30 {
status = "disabled";
compatible = "ssi,s35390a";
reg = <0x30>;
};
};
serial@12000 {
status = "okay";
pinctrl-0 = <&pmx_uart0>;
pinctrl-names = "default";
};
serial@12100 {
status = "okay";
pinctrl-0 = <&pmx_uart1>;
pinctrl-names = "default";
};
poweroff@12100 {
compatible = "synology,power-off";
reg = <0x12100 0x100>;
clocks = <&gate_clk 7>;
};
sata@80000 {
pinctrl-0 = <&pmx_sata0 &pmx_sata1>;
pinctrl-names = "default";
status = "okay";
nr-ports = <2>;
};
};
gpio-fan-150-32-35 {
status = "disabled";
compatible = "gpio-fan";
pinctrl-0 = <&pmx_fanctrl_32 &pmx_fanctrl_33 &pmx_fanctrl_34
&pmx_fanalarm_35>;
pinctrl-names = "default";
gpios = <&gpio1 0 GPIO_ACTIVE_HIGH
&gpio1 1 GPIO_ACTIVE_HIGH
&gpio1 2 GPIO_ACTIVE_HIGH>;
gpio-fan,speed-map = < 0 0
2200 1
2500 2
3000 4
3300 3
3700 5
3800 6
4200 7 >;
};
gpio-fan-150-15-18 {
status = "disabled";
compatible = "gpio-fan";
pinctrl-0 = <&pmx_fanctrl_15 &pmx_fanctrl_16 &pmx_fanctrl_17
&pmx_fanalarm_18>;
pinctrl-names = "default";
gpios = <&gpio0 15 GPIO_ACTIVE_HIGH
&gpio0 16 GPIO_ACTIVE_HIGH
&gpio0 17 GPIO_ACTIVE_HIGH>;
alarm-gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>;
gpio-fan,speed-map = < 0 0
2200 1
2500 2
3000 4
3300 3
3700 5
3800 6
4200 7 >;
};
gpio-fan-100-32-35 {
status = "disabled";
compatible = "gpio-fan";
pinctrl-0 = <&pmx_fanctrl_32 &pmx_fanctrl_33 &pmx_fanctrl_34
&pmx_fanalarm_35>;
pinctrl-names = "default";
gpios = <&gpio1 0 GPIO_ACTIVE_HIGH
&gpio1 1 GPIO_ACTIVE_HIGH
&gpio1 2 GPIO_ACTIVE_HIGH>;
alarm-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
gpio-fan,speed-map = < 0 0
2500 1
3100 2
3800 3
4600 4
4800 5
4900 6
5000 7 >;
};
gpio-fan-100-15-18 {
status = "disabled";
compatible = "gpio-fan";
pinctrl-0 = <&pmx_fanctrl_15 &pmx_fanctrl_16 &pmx_fanctrl_17
&pmx_fanalarm_18>;
pinctrl-names = "default";
gpios = <&gpio0 15 GPIO_ACTIVE_HIGH
&gpio0 16 GPIO_ACTIVE_HIGH
&gpio0 17 GPIO_ACTIVE_HIGH>;
alarm-gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>;
gpio-fan,speed-map = < 0 0
2500 1
3100 2
3800 3
4600 4
4800 5
4900 6
5000 7 >;
};
gpio-fan-100-15-35-1 {
status = "disabled";
compatible = "gpio-fan";
pinctrl-0 = <&pmx_fanctrl_15 &pmx_fanctrl_16 &pmx_fanctrl_17
&pmx_fanalarm_35>;
pinctrl-names = "default";
gpios = <&gpio0 15 GPIO_ACTIVE_HIGH
&gpio0 16 GPIO_ACTIVE_HIGH
&gpio0 17 GPIO_ACTIVE_HIGH>;
alarm-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
gpio-fan,speed-map = < 0 0
2500 1
3100 2
3800 3
4600 4
4800 5
4900 6
5000 7 >;
};
gpio-fan-100-15-35-3 {
status = "disabled";
compatible = "gpio-fan";
pinctrl-0 = <&pmx_fanctrl_15 &pmx_fanctrl_16 &pmx_fanctrl_17
&pmx_fanalarm_35 &pmx_fanalarm_44 &pmx_fanalarm_45>;
pinctrl-names = "default";
gpios = <&gpio0 15 GPIO_ACTIVE_HIGH
&gpio0 16 GPIO_ACTIVE_HIGH
&gpio0 17 GPIO_ACTIVE_HIGH>;
alarm-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH
&gpio1 12 GPIO_ACTIVE_HIGH
&gpio1 13 GPIO_ACTIVE_HIGH>;
gpio-fan,speed-map = < 0 0
2500 1
3100 2
3800 3
4600 4
4800 5
4900 6
5000 7 >;
};
gpio-leds-alarm-12 {
status = "disabled";
compatible = "gpio-leds";
pinctrl-0 = <&pmx_alarmled_12>;
pinctrl-names = "default";
hdd1-green {
label = "synology:alarm";
gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
};
};
gpio-leds-hdd-20 {
status = "disabled";
compatible = "gpio-leds";
pinctrl-0 = <&pmx_hddled_20 &pmx_hddled_21 &pmx_hddled_22
&pmx_hddled_23 &pmx_hddled_24 &pmx_hddled_25
&pmx_hddled_26 &pmx_hddled_27>;
pinctrl-names = "default";
hdd1-green {
label = "synology:green:hdd1";
gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
};
hdd1-amber {
label = "synology:amber:hdd1";
gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
};
hdd2-green {
label = "synology:green:hdd2";
gpios = <&gpio0 22 GPIO_ACTIVE_LOW>;
};
hdd2-amber {
label = "synology:amber:hdd2";
gpios = <&gpio0 23 GPIO_ACTIVE_LOW>;
};
hdd3-green {
label = "synology:green:hdd3";
gpios = <&gpio0 24 GPIO_ACTIVE_LOW>;
};
hdd3-amber {
label = "synology:amber:hdd3";
gpios = <&gpio0 25 GPIO_ACTIVE_LOW>;
};
hdd4-green {
label = "synology:green:hdd4";
gpios = <&gpio0 26 GPIO_ACTIVE_LOW>;
};
hdd4-amber {
label = "synology:amber:hdd4";
gpios = <&gpio0 27 GPIO_ACTIVE_LOW>;
};
};
gpio-leds-hdd-21-1 {
status = "disabled";
compatible = "gpio-leds";
pinctrl-0 = <&pmx_hddled_21 &pmx_hddled_23>;
pinctrl-names = "default";
hdd1-green {
label = "synology:green:hdd1";
gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
};
hdd1-amber {
label = "synology:amber:hdd1";
gpios = <&gpio0 23 GPIO_ACTIVE_LOW>;
};
};
gpio-leds-hdd-21-2 {
status = "disabled";
compatible = "gpio-leds";
pinctrl-0 = <&pmx_hddled_21 &pmx_hddled_23 &pmx_hddled_20 &pmx_hddled_22>;
pinctrl-names = "default";
hdd1-green {
label = "synology:green:hdd1";
gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
};
hdd1-amber {
label = "synology:amber:hdd1";
gpios = <&gpio0 23 GPIO_ACTIVE_LOW>;
};
hdd2-green {
label = "synology:green:hdd2";
gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
};
hdd2-amber {
label = "synology:amber:hdd2";
gpios = <&gpio0 22 GPIO_ACTIVE_LOW>;
};
};
gpio-leds-hdd-36 {
status = "disabled";
compatible = "gpio-leds";
pinctrl-0 = <&pmx_hddled_36 &pmx_hddled_37 &pmx_hddled_38
&pmx_hddled_39 &pmx_hddled_40 &pmx_hddled_41
&pmx_hddled_42 &pmx_hddled_43 &pmx_hddled_44
&pmx_hddled_45>;
pinctrl-names = "default";
hdd1-green {
label = "synology:green:hdd1";
gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
};
hdd1-amber {
label = "synology:amber:hdd1";
gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
};
hdd2-green {
label = "synology:green:hdd2";
gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
};
hdd2-amber {
label = "synology:amber:hdd2";
gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
};
hdd3-green {
label = "synology:green:hdd3";
gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
};
hdd3-amber {
label = "synology:amber:hdd3";
gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
};
hdd4-green {
label = "synology:green:hdd4";
gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
};
hdd4-amber {
label = "synology:amber:hdd4";
gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
};
hdd5-green {
label = "synology:green:hdd5";
gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
};
hdd5-amber {
label = "synology:amber:hdd5";
gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
};
};
gpio-leds-hdd-38 {
status = "disabled";
compatible = "gpio-leds";
pinctrl-0 = <&pmx_hddled_38 &pmx_hddled_39 &pmx_hddled_36 &pmx_hddled_37>;
pinctrl-names = "default";
hdd1-green {
label = "synology:green:hdd1";
gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
};
hdd1-amber {
label = "synology:amber:hdd1";
gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
};
hdd2-green {
label = "synology:green:hdd2";
gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
};
hdd2-amber {
label = "synology:amber:hdd2";
gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
};
};
regulators-hdd-29 {
status = "disabled";
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
pinctrl-0 = <&pmx_hdd1_pwr_29 &pmx_hdd2_pwr_31>;
pinctrl-names = "default";
regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "hdd1power";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
regulator-always-on;
regulator-boot-on;
startup-delay-us = <5000000>;
gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>;
};
regulator@2 {
compatible = "regulator-fixed";
reg = <2>;
regulator-name = "hdd2power";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
regulator-always-on;
regulator-boot-on;
startup-delay-us = <5000000>;
gpio = <&gpio0 31 GPIO_ACTIVE_HIGH>;
};
};
regulators-hdd-30-1 {
status = "disabled";
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
pinctrl-0 = <&pmx_hdd1_pwr_30>;
pinctrl-names = "default";
regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "hdd1power";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
regulator-always-on;
regulator-boot-on;
startup-delay-us = <5000000>;
gpio = <&gpio0 30 GPIO_ACTIVE_HIGH>;
};
};
regulators-hdd-30-2 {
status = "disabled";
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
pinctrl-0 = <&pmx_hdd1_pwr_30 &pmx_hdd2_pwr_34>;
pinctrl-names = "default";
regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "hdd1power";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
regulator-always-on;
regulator-boot-on;
startup-delay-us = <5000000>;
gpio = <&gpio0 30 GPIO_ACTIVE_HIGH>;
};
regulator@2 {
compatible = "regulator-fixed";
reg = <2>;
regulator-name = "hdd2power";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
regulator-always-on;
regulator-boot-on;
startup-delay-us = <5000000>;
gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
};
};
regulators-hdd-30-4 {
status = "disabled";
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
pinctrl-0 = <&pmx_hdd1_pwr_30 &pmx_hdd2_pwr_34
&pmx_hdd3_pwr_44 &pmx_hdd4_pwr_45>;
pinctrl-names = "default";
regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "hdd1power";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
regulator-always-on;
regulator-boot-on;
startup-delay-us = <5000000>;
gpio = <&gpio0 30 GPIO_ACTIVE_HIGH>;
};
regulator@2 {
compatible = "regulator-fixed";
reg = <2>;
regulator-name = "hdd2power";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
regulator-always-on;
regulator-boot-on;
startup-delay-us = <5000000>;
gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
};
regulator@3 {
compatible = "regulator-fixed";
reg = <3>;
regulator-name = "hdd3power";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
regulator-always-on;
regulator-boot-on;
startup-delay-us = <5000000>;
gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
};
regulator@4 {
compatible = "regulator-fixed";
reg = <4>;
regulator-name = "hdd4power";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
regulator-always-on;
regulator-boot-on;
startup-delay-us = <5000000>;
gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>;
};
};
regulators-hdd-31 {
status = "disabled";
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
pinctrl-0 = <&pmx_hdd2_pwr_31>;
pinctrl-names = "default";
regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "hdd2power";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
regulator-always-on;
regulator-boot-on;
startup-delay-us = <5000000>;
gpio = <&gpio0 31 GPIO_ACTIVE_HIGH>;
};
};
regulators-hdd-34 {
status = "disabled";
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
pinctrl-0 = <&pmx_hdd2_pwr_34 &pmx_hdd3_pwr_44
&pmx_hdd4_pwr_45>;
pinctrl-names = "default";
regulator@2 {
compatible = "regulator-fixed";
reg = <2>;
regulator-name = "hdd2power";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
regulator-always-on;
regulator-boot-on;
startup-delay-us = <5000000>;
gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
};
regulator@3 {
compatible = "regulator-fixed";
reg = <3>;
regulator-name = "hdd3power";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
regulator-always-on;
regulator-boot-on;
startup-delay-us = <5000000>;
gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
};
regulator@4 {
compatible = "regulator-fixed";
reg = <4>;
regulator-name = "hdd4power";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
regulator-always-on;
regulator-boot-on;
startup-delay-us = <5000000>;
gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>;
};
};
};
&mdio {
status = "okay";
ethphy0: ethernet-phy@0 {
device_type = "ethernet-phy";
reg = <8>;
};
ethphy1: ethernet-phy@1 {
device_type = "ethernet-phy";
reg = <9>;
};
};
&eth0 {
status = "okay";
ethernet0-port@0 {
phy-handle = <&ethphy0>;
};
};
&eth1 {
status = "disabled";
ethernet1-port@0 {
phy-handle = <&ethphy1>;
};
};

208
arch/arm/boot/dts/kirkwood-t5325.dts Normal file
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@ -0,0 +1,208 @@
/*
* Device Tree file for HP t5325 Thin Client"
*
* Copyright (C) 2014
*
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
* Andrew Lunn <andrew@lunn.ch>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
/dts-v1/;
#include "kirkwood.dtsi"
#include "kirkwood-6281.dtsi"
/ {
model = "HP t5325 Thin Client";
compatible = "hp,t5325", "marvell,kirkwood-88f6281", "marvell,kirkwood";
memory {
device_type = "memory";
reg = <0x00000000 0x20000000>;
};
chosen {
bootargs = "console=ttyS0,115200n8";
};
mbus {
pcie-controller {
status = "okay";
pcie@1,0 {
status = "okay";
};
};
};
ocp@f1000000 {
pinctrl: pinctrl@10000 {
pinctrl-0 = <&pmx_i2s &pmx_sysrst>;
pinctrl-names = "default";
pmx_button_power: pmx-button_power {
marvell,pins = "mpp45";
marvell,function = "gpio";
};
pmx_power_off: pmx-power-off {
marvell,pins = "mpp48";
marvell,function = "gpio";
};
pmx_led: pmx-led {
marvell,pins = "mpp21";
marvell,function = "gpio";
};
pmx_usb_sata_power_enable: pmx-usb-sata-power-enable {
marvell,pins = "mpp44";
marvell,function = "gpio";
};
/*
* Redefined from kirkwood-6281.dtsi, because
* we don't use SPI CS on MPP0, but on MPP7.
*/
pmx_spi: pmx-spi {
marvell,pins = "mpp1", "mpp2", "mpp3", "mpp7";
marvell,function = "spi";
};
pmx_sysrst: pmx-sysrst {
marvell,pins = "mpp6";
marvell,function = "sysrst";
};
pmx_i2s: pmx-i2s {
marvell,pins = "mpp39", "mpp40", "mpp41", "mpp42",
"mpp43";
marvell,function = "audio";
};
};
spi@10600 {
pinctrl-0 = <&pmx_spi>;
pinctrl-names = "default";
status = "okay";
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p80";
spi-max-frequency = <86000000>;
reg = <0>;
mode = <0>;
partition@0 {
reg = <0x0 0x80000>;
label = "u-boot";
};
partition@1 {
reg = <0x80000 0x40000>;
label = "SSD firmware";
};
partition@2 {
reg = <0xc0000 0x10000>;
label = "u-boot env";
};
partition@3 {
reg = <0xd0000 0x10000>;
label = "permanent u-boot env";
};
partition@4 {
reg = <0xd0000 0x10000>;
label = "permanent u-boot env";
};
};
};
i2c@11000 {
status = "okay";
alc5621: alc5621@1a {
compatible = "realtek,alc5621";
reg = <0x1a>;
};
};
serial@12000 {
status = "okay";
};
sata@80000 {
status = "okay";
nr-ports = <2>;
};
audio: audio-controller@a0000 {
status = "okay";
};
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
pinctrl-0 = <&pmx_usb_sata_power_enable>;
pinctrl-names = "default";
usb_power: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "USB-SATA Power";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
regulator-always-on;
regulator-boot-on;
gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
};
};
gpio_keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
pinctrl-0 = <&pmx_button_power>;
pinctrl-names = "default";
button@1 {
label = "Power Button";
linux,code = <KEY_POWER>;
gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
};
};
gpio_poweroff {
compatible = "gpio-poweroff";
pinctrl-0 = <&pmx_power_off>;
pinctrl-names = "default";
gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
};
};
&mdio {
status = "okay";
ethphy0: ethernet-phy {
device_type = "ethernet-phy";
reg = <8>;
};
};
&eth0 {
status = "okay";
ethernet0-port@0 {
phy-handle = <&ethphy0>;
};
};

22
arch/arm/boot/dts/kirkwood.dtsi
View File

@ -24,6 +24,7 @@
aliases {
gpio0 = &gpio0;
gpio1 = &gpio1;
i2c0 = &i2c0;
};
mbus {
@ -111,7 +112,7 @@
clocks = <&gate_clk 7>;
};
i2c@11000 {
i2c0: i2c@11000 {
compatible = "marvell,mv64xxx-i2c";
reg = <0x11000 0x20>;
#address-cells = <1>;
@ -145,6 +146,11 @@
reg = <0x20000 0x80>, <0x1500 0x20>;
};
system-controller@20000 {
compatible = "marvell,orion-system-controller";
reg = <0x20000 0x120>;
};
bridge_intc: bridge-interrupt-ctrl@20110 {
compatible = "marvell,orion-bridge-intc";
interrupt-controller;
@ -161,6 +167,11 @@
#clock-cells = <1>;
};
l2: l2-cache@20128 {
compatible = "marvell,kirkwood-cache";
reg = <0x20128 0x4>;
};
intc: main-interrupt-ctrl@20200 {
compatible = "marvell,orion-intc";
interrupt-controller;
@ -300,5 +311,14 @@
#phy-cells = <0>;
status = "ok";
};
audio0: audio-controller@a0000 {
compatible = "marvell,kirkwood-audio";
reg = <0xa0000 0x2210>;
interrupts = <24>;
clocks = <&gate_clk 9>;
clock-names = "internal";
status = "disabled";
};
};
};