From e8510d43f219beff1f426080049a5462148afd2f Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Thu, 28 May 2020 08:46:39 -0700 Subject: [PATCH] spi: spi-cavium-thunderx: flag controller as half duplex The OcteonTX (TX1/ThunderX) SPI controller does not support full duplex transactions. Set the appropriate flag such that the spi core will return -EINVAL on such transactions requested by chip drivers. This is an RFC as I need someone from Marvell/Cavium to confirm if this driver is used for other silicon that does support full duplex transfers (in which case we will need to identify that we are running on the ThunderX arch before setting the flag). Signed-off-by: Tim Harvey Cc: Robert Richter Link: https://lore.kernel.org/r/1590680799-5640-1-git-send-email-tharvey@gateworks.com Signed-off-by: Mark Brown --- drivers/spi/spi-cavium-thunderx.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/spi/spi-cavium-thunderx.c b/drivers/spi/spi-cavium-thunderx.c index fd6b9caffaf0..60c0d6934654 100644 --- a/drivers/spi/spi-cavium-thunderx.c +++ b/drivers/spi/spi-cavium-thunderx.c @@ -64,6 +64,7 @@ static int thunderx_spi_probe(struct pci_dev *pdev, p->sys_freq = SYS_FREQ_DEFAULT; dev_info(dev, "Set system clock to %u\n", p->sys_freq); + master->flags = SPI_MASTER_HALF_DUPLEX; master->num_chipselect = 4; master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH | SPI_LSB_FIRST | SPI_3WIRE;