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spi: axi-spi-engine: check for valid clock rate
This adds a check for a valid SCLK rate in the axi-spi-engine driver during probe. A valid rate is required to get accurate timing for delays and by not allowing 0 we can avoid divide by zero errors later without additional checks. Signed-off-by: David Lechner <dlechner@baylibre.com> Link: https://lore.kernel.org/r/20231117-axi-spi-engine-series-1-v1-8-cc59db999b87@baylibre.com Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -532,6 +532,9 @@ static int spi_engine_probe(struct platform_device *pdev)
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host->transfer_one_message = spi_engine_transfer_one_message;
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host->num_chipselect = 8;
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if (host->max_speed_hz == 0)
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return dev_err_probe(&pdev->dev, -EINVAL, "spi_clk rate is 0");
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ret = devm_spi_register_controller(&pdev->dev, host);
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if (ret)
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return ret;
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