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phy: for 5.4

Browse Source 
*) Add a new PHY driver for Lantiq VRX200/ARX300 PCIe PHY
   *) Add missing of_node_put() to a bunch of drivers using
      for_each_available_child_of_node()
   *) Add RXAUI/PCIe/SATA/USB3 support in Marvell's Armada
      CP110 COMPHY
   *) Other misc fixes and cleanup
 
 Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Merge tag 'phy-for-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy into char-misc-next

Kishon writes:

phy: for 5.4

  *) Add a new PHY driver for Lantiq VRX200/ARX300 PCIe PHY
  *) Add missing of_node_put() to a bunch of drivers using
     for_each_available_child_of_node()
  *) Add RXAUI/PCIe/SATA/USB3 support in Marvell's Armada
     CP110 COMPHY
  *) Other misc fixes and cleanup

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>

* tag 'phy-for-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy: (30 commits)
  phy: marvell: phy-mvebu-cp110-comphy: rename instances of DLT
  phy: marvell: phy-mvebu-cp110-comphy: implement RXAUI support
  dt-bindings: pci: add PHY properties to Armada 7K/8K controller bindings
  dt-bindings: phy: Add Marvell COMPHY clocks
  phy: mvebu-cp110-comphy: Update comment about powering off all lanes at boot
  phy: mvebu-cp110-comphy: Add PCIe support
  phy: mvebu-cp110-comphy: Cosmetic change in a helper
  phy: mvebu-cp110-comphy: Add SATA support
  phy: mvebu-cp110-comphy: Add USB3 host/device support
  phy: mvebu-cp110-comphy: Allow non-Ethernet modes to be configured
  phy: mvebu-cp110-comphy: Rename the macro handling only Ethernet modes
  phy: mvebu-cp110-comphy: Add RXAUI support
  phy: mvebu-cp110-comphy: List already supported Ethernet modes
  phy: mvebu-cp110-comphy: Add SMC call support
  phy: mvebu-cp110-comphy: Explicitly initialize the lane submode
  phy: mvebu-cp110-comphy: Add clocks support
  phy-rockchip-inno-hdmi: Fix RK3328_TERM_RESISTOR_CALIB_SPEED_7_0's third value
  phy: qcom-qmp: Correct ready status, again
  phy: qualcomm: phy-qcom-qmp: Add of_node_put() before return
  phy: renesas: rcar-gen3-usb2: Disable clearing VBUS in over-current
  ...
This commit is contained in:
Greg Kroah-Hartman 2019-09-03 21:49:11 +02:00
commit e6508c7efa
23 changed files with 1188 additions and 90 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
Documentation/devicetree/bindings/pci/pci-armada8k.txt
View File

@ -17,6 +17,14 @@ Required properties:
name must be "core" for the first clock and "reg" for the second
one
Optional properties:
- phys: phandle(s) to PHY node(s) following the generic PHY bindings.
Either 1, 2 or 4 PHYs might be needed depending on the number of
PCIe lanes.
- phy-names: names of the PHYs corresponding to the number of lanes.
Must be "cp0-pcie0-x4-lane0-phy", "cp0-pcie0-x4-lane1-phy" for
2 PHYs.
Example:
pcie@f2600000 {

95
Documentation/devicetree/bindings/phy/lantiq,vrx200-pcie-phy.yaml Normal file
View File

@ -0,0 +1,95 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/lantiq,vrx200-pcie-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Lantiq VRX200 and ARX300 PCIe PHY Device Tree Bindings
maintainers:
- Martin Blumenstingl <martin.blumenstingl@googlemail.com>
properties:
"#phy-cells":
const: 1
description: selects the PHY mode as defined in <dt-bindings/phy/phy-lantiq-vrx200-pcie.h>
compatible:
enum:
- lantiq,vrx200-pcie-phy
- lantiq,arx300-pcie-phy
reg:
maxItems: 1
clocks:
items:
- description: PHY module clock
- description: PDI register clock
clock-names:
items:
- const: phy
- const: pdi
resets:
items:
- description: exclusive PHY reset line
- description: shared reset line between the PCIe PHY and PCIe controller
resets-names:
items:
- const: phy
- const: pcie
lantiq,rcu:
$ref: /schemas/types.yaml#/definitions/phandle
description: phandle to the RCU syscon
lantiq,rcu-endian-offset:
$ref: /schemas/types.yaml#/definitions/uint32
description: the offset of the endian registers for this PHY instance in the RCU syscon
lantiq,rcu-big-endian-mask:
$ref: /schemas/types.yaml#/definitions/uint32
description: the mask to set the PDI (PHY) registers for this PHY instance to big endian
big-endian:
description: Configures the PDI (PHY) registers in big-endian mode
type: boolean
little-endian:
description: Configures the PDI (PHY) registers in big-endian mode
type: boolean
required:
- "#phy-cells"
- compatible
- reg
- clocks
- clock-names
- resets
- reset-names
- lantiq,rcu
- lantiq,rcu-endian-offset
- lantiq,rcu-big-endian-mask
additionalProperties: false
examples:
- |
pcie0_phy: phy@106800 {
compatible = "lantiq,vrx200-pcie-phy";
reg = <0x106800 0x100>;
lantiq,rcu = <&rcu0>;
lantiq,rcu-endian-offset = <0x4c>;
lantiq,rcu-big-endian-mask = <0x80>; /* bit 7 */
big-endian;
clocks = <&pmu 32>, <&pmu 36>;
clock-names = "phy", "pdi";
resets = <&reset0 12 24>, <&reset0 22 22>;
reset-names = "phy", "pcie";
#phy-cells = <1>;
};
...

10
Documentation/devicetree/bindings/phy/phy-mvebu-comphy.txt
View File

@ -25,6 +25,13 @@ Required properties:
- #address-cells: should be 1.
- #size-cells: should be 0.
Optional properlties:
- clocks: pointers to the reference clocks for this device (CP110 only),
consequently: MG clock, MG Core clock, AXI clock.
- clock-names: names of used clocks for CP110 only, must be :
"mg_clk", "mg_core_clk" and "axi_clk".
A sub-node is required for each comphy lane provided by the comphy.
Required properties (child nodes):
@ -39,6 +46,9 @@ Examples:
compatible = "marvell,comphy-cp110";
reg = <0x120000 0x6000>;
marvell,system-controller = <&cpm_syscon0>;
clocks = <&CP110_LABEL(clk) 1 5>, <&CP110_LABEL(clk) 1 6>,
<&CP110_LABEL(clk) 1 18>;
clock-names = "mg_clk", "mg_core_clk", "axi_clk";
#address-cells = <1>;
#size-cells = <0>;

2
drivers/phy/Makefile
View File

@ -10,7 +10,6 @@ obj-$(CONFIG_PHY_XGENE) += phy-xgene.o
obj-$(CONFIG_PHY_PISTACHIO_USB) += phy-pistachio-usb.o
obj-$(CONFIG_ARCH_SUNXI) += allwinner/
obj-$(CONFIG_ARCH_MESON) += amlogic/
obj-$(CONFIG_LANTIQ) += lantiq/
obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
obj-$(CONFIG_ARCH_RENESAS) += renesas/
obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
@ -19,6 +18,7 @@ obj-y += broadcom/ \
cadence/ \
freescale/ \
hisilicon/ \
lantiq/ \
marvell/ \
motorola/ \
mscc/ \

11
drivers/phy/lantiq/Kconfig
View File

@ -2,6 +2,17 @@
#
# Phy drivers for Lantiq / Intel platforms
#
config PHY_LANTIQ_VRX200_PCIE
tristate "Lantiq VRX200/ARX300 PCIe PHY"
depends on SOC_TYPE_XWAY || COMPILE_TEST
depends on OF && HAS_IOMEM
select GENERIC_PHY
select REGMAP_MMIO
help
Support for the PCIe PHY(s) on the Lantiq / Intel VRX200 and ARX300
family SoCs.
If unsure, say N.
config PHY_LANTIQ_RCU_USB2
tristate "Lantiq XWAY SoC RCU based USB PHY"
depends on OF && (SOC_TYPE_XWAY || COMPILE_TEST)

1
drivers/phy/lantiq/Makefile
View File

@ -1,2 +1,3 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_PHY_LANTIQ_RCU_USB2) += phy-lantiq-rcu-usb2.o
obj-$(CONFIG_PHY_LANTIQ_VRX200_PCIE) += phy-lantiq-vrx200-pcie.o

494
drivers/phy/lantiq/phy-lantiq-vrx200-pcie.c Normal file
View File

@ -0,0 +1,494 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* PCIe PHY driver for Lantiq VRX200 and ARX300 SoCs.
*
* Copyright (C) 2019 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
*
* Based on the BSP (called "UGW") driver:
* Copyright (C) 2009-2015 Lei Chuanhua <chuanhua.lei@lantiq.com>
* Copyright (C) 2016 Intel Corporation
*
* TODO: PHY modes other than 36MHz (without "SSC")
*/
#include <linux/bitfield.h>
#include <linux/bits.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/property.h>
#include <linux/regmap.h>
#include <linux/reset.h>
#include <dt-bindings/phy/phy-lantiq-vrx200-pcie.h>
#define PCIE_PHY_PLL_CTRL1 0x44
#define PCIE_PHY_PLL_CTRL2 0x46
#define PCIE_PHY_PLL_CTRL2_CONST_SDM_MASK GENMASK(7, 0)
#define PCIE_PHY_PLL_CTRL2_CONST_SDM_EN BIT(8)
#define PCIE_PHY_PLL_CTRL2_PLL_SDM_EN BIT(9)
#define PCIE_PHY_PLL_CTRL3 0x48
#define PCIE_PHY_PLL_CTRL3_EXT_MMD_DIV_RATIO_EN BIT(1)
#define PCIE_PHY_PLL_CTRL3_EXT_MMD_DIV_RATIO_MASK GENMASK(6, 4)
#define PCIE_PHY_PLL_CTRL4 0x4a
#define PCIE_PHY_PLL_CTRL5 0x4c
#define PCIE_PHY_PLL_CTRL6 0x4e
#define PCIE_PHY_PLL_CTRL7 0x50
#define PCIE_PHY_PLL_A_CTRL1 0x52
#define PCIE_PHY_PLL_A_CTRL2 0x54
#define PCIE_PHY_PLL_A_CTRL2_LF_MODE_EN BIT(14)
#define PCIE_PHY_PLL_A_CTRL3 0x56
#define PCIE_PHY_PLL_A_CTRL3_MMD_MASK GENMASK(15, 13)
#define PCIE_PHY_PLL_STATUS 0x58
#define PCIE_PHY_TX1_CTRL1 0x60
#define PCIE_PHY_TX1_CTRL1_FORCE_EN BIT(3)
#define PCIE_PHY_TX1_CTRL1_LOAD_EN BIT(4)
#define PCIE_PHY_TX1_CTRL2 0x62
#define PCIE_PHY_TX1_CTRL3 0x64
#define PCIE_PHY_TX1_A_CTRL1 0x66
#define PCIE_PHY_TX1_A_CTRL2 0x68
#define PCIE_PHY_TX1_MOD1 0x6a
#define PCIE_PHY_TX1_MOD2 0x6c
#define PCIE_PHY_TX1_MOD3 0x6e
#define PCIE_PHY_TX2_CTRL1 0x70
#define PCIE_PHY_TX2_CTRL1_LOAD_EN BIT(4)
#define PCIE_PHY_TX2_CTRL2 0x72
#define PCIE_PHY_TX2_A_CTRL1 0x76
#define PCIE_PHY_TX2_A_CTRL2 0x78
#define PCIE_PHY_TX2_MOD1 0x7a
#define PCIE_PHY_TX2_MOD2 0x7c
#define PCIE_PHY_TX2_MOD3 0x7e
#define PCIE_PHY_RX1_CTRL1 0xa0
#define PCIE_PHY_RX1_CTRL1_LOAD_EN BIT(1)
#define PCIE_PHY_RX1_CTRL2 0xa2
#define PCIE_PHY_RX1_CDR 0xa4
#define PCIE_PHY_RX1_EI 0xa6
#define PCIE_PHY_RX1_A_CTRL 0xaa
struct ltq_vrx200_pcie_phy_priv {
struct phy *phy;
unsigned int mode;
struct device *dev;
struct regmap *phy_regmap;
struct regmap *rcu_regmap;
struct clk *pdi_clk;
struct clk *phy_clk;
struct reset_control *phy_reset;
struct reset_control *pcie_reset;
u32 rcu_ahb_endian_offset;
u32 rcu_ahb_endian_big_endian_mask;
};
static void ltq_vrx200_pcie_phy_common_setup(struct phy *phy)
{
struct ltq_vrx200_pcie_phy_priv *priv = phy_get_drvdata(phy);
/* PLL Setting */
regmap_write(priv->phy_regmap, PCIE_PHY_PLL_A_CTRL1, 0x120e);
/* increase the bias reference voltage */
regmap_write(priv->phy_regmap, PCIE_PHY_PLL_A_CTRL2, 0x39d7);
regmap_write(priv->phy_regmap, PCIE_PHY_PLL_A_CTRL3, 0x0900);
/* Endcnt */
regmap_write(priv->phy_regmap, PCIE_PHY_RX1_EI, 0x0004);
regmap_write(priv->phy_regmap, PCIE_PHY_RX1_A_CTRL, 0x6803);
regmap_update_bits(priv->phy_regmap, PCIE_PHY_TX1_CTRL1,
PCIE_PHY_TX1_CTRL1_FORCE_EN,
PCIE_PHY_TX1_CTRL1_FORCE_EN);
/* predrv_ser_en */
regmap_write(priv->phy_regmap, PCIE_PHY_TX1_A_CTRL2, 0x0706);
/* ctrl_lim */
regmap_write(priv->phy_regmap, PCIE_PHY_TX1_CTRL3, 0x1fff);
/* ctrl */
regmap_write(priv->phy_regmap, PCIE_PHY_TX1_A_CTRL1, 0x0810);
/* predrv_ser_en */
regmap_update_bits(priv->phy_regmap, PCIE_PHY_TX2_A_CTRL2, 0x7f00,
0x4700);
/* RTERM */
regmap_write(priv->phy_regmap, PCIE_PHY_TX1_CTRL2, 0x2e00);
/* Improved 100MHz clock output */
regmap_write(priv->phy_regmap, PCIE_PHY_TX2_CTRL2, 0x3096);
regmap_write(priv->phy_regmap, PCIE_PHY_TX2_A_CTRL2, 0x4707);
/* Reduced CDR BW to avoid glitches */
regmap_write(priv->phy_regmap, PCIE_PHY_RX1_CDR, 0x0235);
}
static void pcie_phy_36mhz_mode_setup(struct phy *phy)
{
struct ltq_vrx200_pcie_phy_priv *priv = phy_get_drvdata(phy);
regmap_update_bits(priv->phy_regmap, PCIE_PHY_PLL_CTRL3,
PCIE_PHY_PLL_CTRL3_EXT_MMD_DIV_RATIO_EN, 0x0000);
regmap_update_bits(priv->phy_regmap, PCIE_PHY_PLL_CTRL3,
PCIE_PHY_PLL_CTRL3_EXT_MMD_DIV_RATIO_MASK, 0x0000);
regmap_update_bits(priv->phy_regmap, PCIE_PHY_PLL_CTRL2,
PCIE_PHY_PLL_CTRL2_PLL_SDM_EN,
PCIE_PHY_PLL_CTRL2_PLL_SDM_EN);
regmap_update_bits(priv->phy_regmap, PCIE_PHY_PLL_CTRL2,
PCIE_PHY_PLL_CTRL2_CONST_SDM_EN,
PCIE_PHY_PLL_CTRL2_CONST_SDM_EN);
regmap_update_bits(priv->phy_regmap, PCIE_PHY_PLL_A_CTRL3,
PCIE_PHY_PLL_A_CTRL3_MMD_MASK,
FIELD_PREP(PCIE_PHY_PLL_A_CTRL3_MMD_MASK, 0x1));
regmap_update_bits(priv->phy_regmap, PCIE_PHY_PLL_A_CTRL2,
PCIE_PHY_PLL_A_CTRL2_LF_MODE_EN, 0x0000);
/* const_sdm */
regmap_write(priv->phy_regmap, PCIE_PHY_PLL_CTRL1, 0x38e4);
regmap_update_bits(priv->phy_regmap, PCIE_PHY_PLL_CTRL2,
PCIE_PHY_PLL_CTRL2_CONST_SDM_MASK,
FIELD_PREP(PCIE_PHY_PLL_CTRL2_CONST_SDM_MASK,
0xee));
/* pllmod */
regmap_write(priv->phy_regmap, PCIE_PHY_PLL_CTRL7, 0x0002);
regmap_write(priv->phy_regmap, PCIE_PHY_PLL_CTRL6, 0x3a04);
regmap_write(priv->phy_regmap, PCIE_PHY_PLL_CTRL5, 0xfae3);
regmap_write(priv->phy_regmap, PCIE_PHY_PLL_CTRL4, 0x1b72);
}
static int ltq_vrx200_pcie_phy_wait_for_pll(struct phy *phy)
{
struct ltq_vrx200_pcie_phy_priv *priv = phy_get_drvdata(phy);
unsigned int tmp;
int ret;
ret = regmap_read_poll_timeout(priv->phy_regmap, PCIE_PHY_PLL_STATUS,
tmp, ((tmp & 0x0070) == 0x0070), 10,
10000);
if (ret) {
dev_err(priv->dev, "PLL Link timeout, PLL status = 0x%04x\n",
tmp);
return ret;
}
return 0;
}
static void ltq_vrx200_pcie_phy_apply_workarounds(struct phy *phy)
{
struct ltq_vrx200_pcie_phy_priv *priv = phy_get_drvdata(phy);
static const struct reg_default slices[] = {
{
.reg = PCIE_PHY_TX1_CTRL1,
.def = PCIE_PHY_TX1_CTRL1_LOAD_EN,
},
{
.reg = PCIE_PHY_TX2_CTRL1,
.def = PCIE_PHY_TX2_CTRL1_LOAD_EN,
},
{
.reg = PCIE_PHY_RX1_CTRL1,
.def = PCIE_PHY_RX1_CTRL1_LOAD_EN,
}
};
int i;
for (i = 0; i < ARRAY_SIZE(slices); i++) {
/* enable load_en */
regmap_update_bits(priv->phy_regmap, slices[i].reg,
slices[i].def, slices[i].def);
udelay(1);
/* disable load_en */
regmap_update_bits(priv->phy_regmap, slices[i].reg,
slices[i].def, 0x0);
}
for (i = 0; i < 5; i++) {
/* TX2 modulation */
regmap_write(priv->phy_regmap, PCIE_PHY_TX2_MOD1, 0x1ffe);
regmap_write(priv->phy_regmap, PCIE_PHY_TX2_MOD2, 0xfffe);
regmap_write(priv->phy_regmap, PCIE_PHY_TX2_MOD3, 0x0601);
usleep_range(1000, 2000);
regmap_write(priv->phy_regmap, PCIE_PHY_TX2_MOD3, 0x0001);
/* TX1 modulation */
regmap_write(priv->phy_regmap, PCIE_PHY_TX1_MOD1, 0x1ffe);
regmap_write(priv->phy_regmap, PCIE_PHY_TX1_MOD2, 0xfffe);
regmap_write(priv->phy_regmap, PCIE_PHY_TX1_MOD3, 0x0601);
usleep_range(1000, 2000);
regmap_write(priv->phy_regmap, PCIE_PHY_TX1_MOD3, 0x0001);
}
}
static int ltq_vrx200_pcie_phy_init(struct phy *phy)
{
struct ltq_vrx200_pcie_phy_priv *priv = phy_get_drvdata(phy);
int ret;
if (of_device_is_big_endian(priv->dev->of_node))
regmap_update_bits(priv->rcu_regmap,
priv->rcu_ahb_endian_offset,
priv->rcu_ahb_endian_big_endian_mask,
priv->rcu_ahb_endian_big_endian_mask);
else
regmap_update_bits(priv->rcu_regmap,
priv->rcu_ahb_endian_offset,
priv->rcu_ahb_endian_big_endian_mask, 0x0);
ret = reset_control_assert(priv->phy_reset);
if (ret)
goto err;
udelay(1);
ret = reset_control_deassert(priv->phy_reset);
if (ret)
goto err;
udelay(1);
ret = reset_control_deassert(priv->pcie_reset);
if (ret)
goto err_assert_phy_reset;
/* Make sure PHY PLL is stable */
usleep_range(20, 40);
return 0;
err_assert_phy_reset:
reset_control_assert(priv->phy_reset);
err:
return ret;
}
static int ltq_vrx200_pcie_phy_exit(struct phy *phy)
{
struct ltq_vrx200_pcie_phy_priv *priv = phy_get_drvdata(phy);
int ret;
ret = reset_control_assert(priv->pcie_reset);
if (ret)
return ret;
ret = reset_control_assert(priv->phy_reset);
if (ret)
return ret;
return 0;
}
static int ltq_vrx200_pcie_phy_power_on(struct phy *phy)
{
struct ltq_vrx200_pcie_phy_priv *priv = phy_get_drvdata(phy);
int ret;
/* Enable PDI to access PCIe PHY register */
ret = clk_prepare_enable(priv->pdi_clk);
if (ret)
goto err;
/* Configure PLL and PHY clock */
ltq_vrx200_pcie_phy_common_setup(phy);
pcie_phy_36mhz_mode_setup(phy);
/* Enable the PCIe PHY and make PLL setting take effect */
ret = clk_prepare_enable(priv->phy_clk);
if (ret)
goto err_disable_pdi_clk;
/* Check if we are in "startup ready" status */
if (ltq_vrx200_pcie_phy_wait_for_pll(phy) != 0)
goto err_disable_phy_clk;
ltq_vrx200_pcie_phy_apply_workarounds(phy);
return 0;
err_disable_phy_clk:
clk_disable_unprepare(priv->phy_clk);
err_disable_pdi_clk:
clk_disable_unprepare(priv->pdi_clk);
err:
return ret;
}
static int ltq_vrx200_pcie_phy_power_off(struct phy *phy)
{
struct ltq_vrx200_pcie_phy_priv *priv = phy_get_drvdata(phy);
clk_disable_unprepare(priv->phy_clk);
clk_disable_unprepare(priv->pdi_clk);
return 0;
}
static struct phy_ops ltq_vrx200_pcie_phy_ops = {
.init = ltq_vrx200_pcie_phy_init,
.exit = ltq_vrx200_pcie_phy_exit,
.power_on = ltq_vrx200_pcie_phy_power_on,
.power_off = ltq_vrx200_pcie_phy_power_off,
.owner = THIS_MODULE,
};
static struct phy *ltq_vrx200_pcie_phy_xlate(struct device *dev,
struct of_phandle_args *args)
{
struct ltq_vrx200_pcie_phy_priv *priv = dev_get_drvdata(dev);
unsigned int mode;
if (args->args_count != 1) {
dev_err(dev, "invalid number of arguments\n");
return ERR_PTR(-EINVAL);
}
mode = args->args[0];
switch (mode) {
case LANTIQ_PCIE_PHY_MODE_36MHZ:
priv->mode = mode;
break;
case LANTIQ_PCIE_PHY_MODE_25MHZ:
case LANTIQ_PCIE_PHY_MODE_25MHZ_SSC:
case LANTIQ_PCIE_PHY_MODE_36MHZ_SSC:
case LANTIQ_PCIE_PHY_MODE_100MHZ:
case LANTIQ_PCIE_PHY_MODE_100MHZ_SSC:
dev_err(dev, "PHY mode not implemented yet: %u\n", mode);
return ERR_PTR(-EINVAL);
default:
dev_err(dev, "invalid PHY mode %u\n", mode);
return ERR_PTR(-EINVAL);
};
return priv->phy;
}
static int ltq_vrx200_pcie_phy_probe(struct platform_device *pdev)
{
static const struct regmap_config regmap_config = {
.reg_bits = 8,
.val_bits = 16,
.reg_stride = 2,
.max_register = PCIE_PHY_RX1_A_CTRL,
};
struct ltq_vrx200_pcie_phy_priv *priv;
struct device *dev = &pdev->dev;
struct phy_provider *provider;
struct resource *res;
void __iomem *base;
int ret;
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
base = devm_ioremap_resource(dev, res);
if (IS_ERR(base))
return PTR_ERR(base);
priv->phy_regmap = devm_regmap_init_mmio(dev, base, &regmap_config);
if (IS_ERR(priv->phy_regmap))
return PTR_ERR(priv->phy_regmap);
priv->rcu_regmap = syscon_regmap_lookup_by_phandle(dev->of_node,
"lantiq,rcu");
if (IS_ERR(priv->rcu_regmap))
return PTR_ERR(priv->rcu_regmap);
ret = device_property_read_u32(dev, "lantiq,rcu-endian-offset",
&priv->rcu_ahb_endian_offset);
if (ret) {
dev_err(dev,
"failed to parse the 'lantiq,rcu-endian-offset' property\n");
return ret;
}
ret = device_property_read_u32(dev, "lantiq,rcu-big-endian-mask",
&priv->rcu_ahb_endian_big_endian_mask);
if (ret) {
dev_err(dev,
"failed to parse the 'lantiq,rcu-big-endian-mask' property\n");
return ret;
}
priv->pdi_clk = devm_clk_get(dev, "pdi");
if (IS_ERR(priv->pdi_clk))
return PTR_ERR(priv->pdi_clk);
priv->phy_clk = devm_clk_get(dev, "phy");
if (IS_ERR(priv->phy_clk))
return PTR_ERR(priv->phy_clk);
priv->phy_reset = devm_reset_control_get_exclusive(dev, "phy");
if (IS_ERR(priv->phy_reset))
return PTR_ERR(priv->phy_reset);
priv->pcie_reset = devm_reset_control_get_shared(dev, "pcie");
if (IS_ERR(priv->pcie_reset))
return PTR_ERR(priv->pcie_reset);
priv->dev = dev;
priv->phy = devm_phy_create(dev, dev->of_node,
&ltq_vrx200_pcie_phy_ops);
if (IS_ERR(priv->phy)) {
dev_err(dev, "failed to create PHY\n");
return PTR_ERR(priv->phy);
}
phy_set_drvdata(priv->phy, priv);
dev_set_drvdata(dev, priv);
provider = devm_of_phy_provider_register(dev,
ltq_vrx200_pcie_phy_xlate);
return PTR_ERR_OR_ZERO(provider);
}
static const struct of_device_id ltq_vrx200_pcie_phy_of_match[] = {
{ .compatible = "lantiq,vrx200-pcie-phy", },
{ .compatible = "lantiq,arx300-pcie-phy", },
{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, ltq_vrx200_pcie_phy_of_match);
static struct platform_driver ltq_vrx200_pcie_phy_driver = {
.probe = ltq_vrx200_pcie_phy_probe,
.driver = {
.name = "ltq-vrx200-pcie-phy",
.of_match_table = ltq_vrx200_pcie_phy_of_match,
}
};
module_platform_driver(ltq_vrx200_pcie_phy_driver);
MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
MODULE_DESCRIPTION("Lantiq VRX200 and ARX300 PCIe PHY driver");
MODULE_LICENSE("GPL v2");

1
drivers/phy/marvell/Kconfig
View File

@ -57,6 +57,7 @@ config PHY_MVEBU_CP110_COMPHY
tristate "Marvell CP110 comphy driver"
depends on ARCH_MVEBU || COMPILE_TEST
depends on OF
depends on HAVE_ARM_SMCCC
select GENERIC_PHY
help
This driver allows to control the comphy, an hardware block providing

4
drivers/phy/marvell/phy-armada38x-comphy.c
View File

@ -200,8 +200,10 @@ static int a38x_comphy_probe(struct platform_device *pdev)
}
phy = devm_phy_create(&pdev->dev, child, &a38x_comphy_ops);
if (IS_ERR(phy))
if (IS_ERR(phy)) {
of_node_put(child);
return PTR_ERR(phy);
}
priv->lane[val].base = base + 0x28 * val;
priv->lane[val].priv = priv;

17
drivers/phy/marvell/phy-mvebu-a3700-comphy.c
View File

@ -26,6 +26,7 @@
#define COMPHY_SIP_POWER_ON 0x82000001
#define COMPHY_SIP_POWER_OFF 0x82000002
#define COMPHY_SIP_PLL_LOCK 0x82000003
#define COMPHY_FW_NOT_SUPPORTED (-1)
#define COMPHY_FW_MODE_SATA 0x1
#define COMPHY_FW_MODE_SGMII 0x2
@ -169,6 +170,7 @@ static int mvebu_a3700_comphy_power_on(struct phy *phy)
struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy);
u32 fw_param;
int fw_mode;
int ret;
fw_mode = mvebu_a3700_comphy_get_fw_mode(lane->id, lane->port,
lane->mode, lane->submode);
@ -217,7 +219,12 @@ static int mvebu_a3700_comphy_power_on(struct phy *phy)
return -ENOTSUPP;
}
return mvebu_a3700_comphy_smc(COMPHY_SIP_POWER_ON, lane->id, fw_param);
ret = mvebu_a3700_comphy_smc(COMPHY_SIP_POWER_ON, lane->id, fw_param);
if (ret == COMPHY_FW_NOT_SUPPORTED)
dev_err(lane->dev,
"unsupported SMC call, try updating your firmware\n");
return ret;
}
static int mvebu_a3700_comphy_power_off(struct phy *phy)
@ -277,13 +284,17 @@ static int mvebu_a3700_comphy_probe(struct platform_device *pdev)
}
lane = devm_kzalloc(&pdev->dev, sizeof(*lane), GFP_KERNEL);
if (!lane)
if (!lane) {
of_node_put(child);
return -ENOMEM;
}
phy = devm_phy_create(&pdev->dev, child,
&mvebu_a3700_comphy_ops);
if (IS_ERR(phy))
if (IS_ERR(phy)) {
of_node_put(child);
return PTR_ERR(phy);
}
lane->dev = &pdev->dev;
lane->mode = PHY_MODE_INVALID;

527
drivers/phy/marvell/phy-mvebu-cp110-comphy.c
View File

@ -5,6 +5,8 @@
* Antoine Tenart <antoine.tenart@free-electrons.com>
*/
#include <linux/arm-smccc.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/mfd/syscon.h>
@ -22,6 +24,7 @@
#define MVEBU_COMPHY_SERDES_CFG0_PU_RX BIT(11)
#define MVEBU_COMPHY_SERDES_CFG0_PU_TX BIT(12)
#define MVEBU_COMPHY_SERDES_CFG0_HALF_BUS BIT(14)
#define MVEBU_COMPHY_SERDES_CFG0_RXAUI_MODE BIT(15)
#define MVEBU_COMPHY_SERDES_CFG1(n) (0x4 + (n) * 0x1000)
#define MVEBU_COMPHY_SERDES_CFG1_RESET BIT(3)
#define MVEBU_COMPHY_SERDES_CFG1_RX_INIT BIT(4)
@ -77,8 +80,8 @@
#define MVEBU_COMPHY_TX_SLEW_RATE(n) (0x974 + (n) * 0x1000)
#define MVEBU_COMPHY_TX_SLEW_RATE_EMPH(n) ((n) << 5)
#define MVEBU_COMPHY_TX_SLEW_RATE_SLC(n) ((n) << 10)
#define MVEBU_COMPHY_DLT_CTRL(n) (0x984 + (n) * 0x1000)
#define MVEBU_COMPHY_DLT_CTRL_DTL_FLOOP_EN BIT(2)
#define MVEBU_COMPHY_DTL_CTRL(n) (0x984 + (n) * 0x1000)
#define MVEBU_COMPHY_DTL_CTRL_DTL_FLOOP_EN BIT(2)
#define MVEBU_COMPHY_FRAME_DETECT0(n) (0xa14 + (n) * 0x1000)
#define MVEBU_COMPHY_FRAME_DETECT0_PATN(n) ((n) << 7)
#define MVEBU_COMPHY_FRAME_DETECT3(n) (0xa20 + (n) * 0x1000)
@ -111,55 +114,151 @@
#define MVEBU_COMPHY_SELECTOR_PHY(n) ((n) * 0x4)
#define MVEBU_COMPHY_PIPE_SELECTOR 0x1144
#define MVEBU_COMPHY_PIPE_SELECTOR_PIPE(n) ((n) * 0x4)
#define MVEBU_COMPHY_SD1_CTRL1 0x1148
#define MVEBU_COMPHY_SD1_CTRL1_RXAUI1_EN BIT(26)
#define MVEBU_COMPHY_SD1_CTRL1_RXAUI0_EN BIT(27)
#define MVEBU_COMPHY_LANES 6
#define MVEBU_COMPHY_PORTS 3
#define COMPHY_SIP_POWER_ON 0x82000001
#define COMPHY_SIP_POWER_OFF 0x82000002
#define COMPHY_FW_NOT_SUPPORTED (-1)
/*
* A lane is described by the following bitfields:
* [ 1- 0]: COMPHY polarity invertion
* [ 2- 7]: COMPHY speed
* [ 5-11]: COMPHY port index
* [12-16]: COMPHY mode
* [17]: Clock source
* [18-20]: PCIe width (x1, x2, x4)
*/
#define COMPHY_FW_POL_OFFSET 0
#define COMPHY_FW_POL_MASK GENMASK(1, 0)
#define COMPHY_FW_SPEED_OFFSET 2
#define COMPHY_FW_SPEED_MASK GENMASK(7, 2)
#define COMPHY_FW_SPEED_MAX COMPHY_FW_SPEED_MASK
#define COMPHY_FW_SPEED_1250 0
#define COMPHY_FW_SPEED_3125 2
#define COMPHY_FW_SPEED_5000 3
#define COMPHY_FW_SPEED_103125 6
#define COMPHY_FW_PORT_OFFSET 8
#define COMPHY_FW_PORT_MASK GENMASK(11, 8)
#define COMPHY_FW_MODE_OFFSET 12
#define COMPHY_FW_MODE_MASK GENMASK(16, 12)
#define COMPHY_FW_WIDTH_OFFSET 18
#define COMPHY_FW_WIDTH_MASK GENMASK(20, 18)
#define COMPHY_FW_PARAM_FULL(mode, port, speed, pol, width) \
((((pol) << COMPHY_FW_POL_OFFSET) & COMPHY_FW_POL_MASK) | \
(((mode) << COMPHY_FW_MODE_OFFSET) & COMPHY_FW_MODE_MASK) | \
(((port) << COMPHY_FW_PORT_OFFSET) & COMPHY_FW_PORT_MASK) | \
(((speed) << COMPHY_FW_SPEED_OFFSET) & COMPHY_FW_SPEED_MASK) | \
(((width) << COMPHY_FW_WIDTH_OFFSET) & COMPHY_FW_WIDTH_MASK))
#define COMPHY_FW_PARAM(mode, port) \
COMPHY_FW_PARAM_FULL(mode, port, COMPHY_FW_SPEED_MAX, 0, 0)
#define COMPHY_FW_PARAM_ETH(mode, port, speed) \
COMPHY_FW_PARAM_FULL(mode, port, speed, 0, 0)
#define COMPHY_FW_PARAM_PCIE(mode, port, width) \
COMPHY_FW_PARAM_FULL(mode, port, COMPHY_FW_SPEED_5000, 0, width)
#define COMPHY_FW_MODE_SATA 0x1
#define COMPHY_FW_MODE_SGMII 0x2 /* SGMII 1G */
#define COMPHY_FW_MODE_HS_SGMII 0x3 /* SGMII 2.5G */
#define COMPHY_FW_MODE_USB3H 0x4
#define COMPHY_FW_MODE_USB3D 0x5
#define COMPHY_FW_MODE_PCIE 0x6
#define COMPHY_FW_MODE_RXAUI 0x7
#define COMPHY_FW_MODE_XFI 0x8 /* SFI: 0x9 (is treated like XFI) */
struct mvebu_comphy_conf {
enum phy_mode mode;
int submode;
unsigned lane;
unsigned port;
u32 mux;
u32 fw_mode;
};
#define MVEBU_COMPHY_CONF(_lane, _port, _submode, _mux) \
#define ETH_CONF(_lane, _port, _submode, _mux, _fw) \
{ \
.lane = _lane, \
.port = _port, \
.mode = PHY_MODE_ETHERNET, \
.submode = _submode, \
.mux = _mux, \
.fw_mode = _fw, \
}
#define GEN_CONF(_lane, _port, _mode, _fw) \
{ \
.lane = _lane, \
.port = _port, \
.mode = _mode, \
.submode = PHY_INTERFACE_MODE_NA, \
.mux = -1, \
.fw_mode = _fw, \
}
static const struct mvebu_comphy_conf mvebu_comphy_cp110_modes[] = {
/* lane 0 */
MVEBU_COMPHY_CONF(0, 1, PHY_INTERFACE_MODE_SGMII, 0x1),
MVEBU_COMPHY_CONF(0, 1, PHY_INTERFACE_MODE_2500BASEX, 0x1),
GEN_CONF(0, 0, PHY_MODE_PCIE, COMPHY_FW_MODE_PCIE),
ETH_CONF(0, 1, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
ETH_CONF(0, 1, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_HS_SGMII),
GEN_CONF(0, 1, PHY_MODE_SATA, COMPHY_FW_MODE_SATA),
/* lane 1 */
MVEBU_COMPHY_CONF(1, 2, PHY_INTERFACE_MODE_SGMII, 0x1),
MVEBU_COMPHY_CONF(1, 2, PHY_INTERFACE_MODE_2500BASEX, 0x1),
GEN_CONF(1, 0, PHY_MODE_USB_HOST_SS, COMPHY_FW_MODE_USB3H),
GEN_CONF(1, 0, PHY_MODE_USB_DEVICE_SS, COMPHY_FW_MODE_USB3D),
GEN_CONF(1, 0, PHY_MODE_SATA, COMPHY_FW_MODE_SATA),
GEN_CONF(1, 0, PHY_MODE_PCIE, COMPHY_FW_MODE_PCIE),
ETH_CONF(1, 2, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
ETH_CONF(1, 2, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_HS_SGMII),
/* lane 2 */
MVEBU_COMPHY_CONF(2, 0, PHY_INTERFACE_MODE_SGMII, 0x1),
MVEBU_COMPHY_CONF(2, 0, PHY_INTERFACE_MODE_2500BASEX, 0x1),
MVEBU_COMPHY_CONF(2, 0, PHY_INTERFACE_MODE_10GKR, 0x1),
ETH_CONF(2, 0, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
ETH_CONF(2, 0, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_HS_SGMII),
ETH_CONF(2, 0, PHY_INTERFACE_MODE_RXAUI, 0x1, COMPHY_FW_MODE_RXAUI),
ETH_CONF(2, 0, PHY_INTERFACE_MODE_10GKR, 0x1, COMPHY_FW_MODE_XFI),
GEN_CONF(2, 0, PHY_MODE_USB_HOST_SS, COMPHY_FW_MODE_USB3H),
GEN_CONF(2, 0, PHY_MODE_SATA, COMPHY_FW_MODE_SATA),
GEN_CONF(2, 0, PHY_MODE_PCIE, COMPHY_FW_MODE_PCIE),
/* lane 3 */
MVEBU_COMPHY_CONF(3, 1, PHY_INTERFACE_MODE_SGMII, 0x2),
MVEBU_COMPHY_CONF(3, 1, PHY_INTERFACE_MODE_2500BASEX, 0x2),
GEN_CONF(3, 0, PHY_MODE_PCIE, COMPHY_FW_MODE_PCIE),
ETH_CONF(3, 1, PHY_INTERFACE_MODE_SGMII, 0x2, COMPHY_FW_MODE_SGMII),
ETH_CONF(3, 1, PHY_INTERFACE_MODE_2500BASEX, 0x2, COMPHY_FW_MODE_HS_SGMII),
ETH_CONF(3, 1, PHY_INTERFACE_MODE_RXAUI, 0x1, COMPHY_FW_MODE_RXAUI),
GEN_CONF(3, 1, PHY_MODE_USB_HOST_SS, COMPHY_FW_MODE_USB3H),
GEN_CONF(3, 1, PHY_MODE_SATA, COMPHY_FW_MODE_SATA),
/* lane 4 */
MVEBU_COMPHY_CONF(4, 0, PHY_INTERFACE_MODE_SGMII, 0x2),
MVEBU_COMPHY_CONF(4, 0, PHY_INTERFACE_MODE_2500BASEX, 0x2),
MVEBU_COMPHY_CONF(4, 0, PHY_INTERFACE_MODE_10GKR, 0x2),
MVEBU_COMPHY_CONF(4, 1, PHY_INTERFACE_MODE_SGMII, 0x1),
ETH_CONF(4, 0, PHY_INTERFACE_MODE_SGMII, 0x2, COMPHY_FW_MODE_SGMII),
ETH_CONF(4, 0, PHY_INTERFACE_MODE_2500BASEX, 0x2, COMPHY_FW_MODE_HS_SGMII),
ETH_CONF(4, 0, PHY_INTERFACE_MODE_10GKR, 0x2, COMPHY_FW_MODE_XFI),
ETH_CONF(4, 0, PHY_INTERFACE_MODE_RXAUI, 0x2, COMPHY_FW_MODE_RXAUI),
GEN_CONF(4, 0, PHY_MODE_USB_DEVICE_SS, COMPHY_FW_MODE_USB3D),
GEN_CONF(4, 1, PHY_MODE_USB_HOST_SS, COMPHY_FW_MODE_USB3H),
GEN_CONF(4, 1, PHY_MODE_PCIE, COMPHY_FW_MODE_PCIE),
ETH_CONF(4, 1, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
ETH_CONF(4, 1, PHY_INTERFACE_MODE_2500BASEX, -1, COMPHY_FW_MODE_HS_SGMII),
ETH_CONF(4, 1, PHY_INTERFACE_MODE_10GKR, -1, COMPHY_FW_MODE_XFI),
/* lane 5 */
MVEBU_COMPHY_CONF(5, 2, PHY_INTERFACE_MODE_SGMII, 0x1),
MVEBU_COMPHY_CONF(5, 2, PHY_INTERFACE_MODE_2500BASEX, 0x1),
ETH_CONF(5, 1, PHY_INTERFACE_MODE_RXAUI, 0x2, COMPHY_FW_MODE_RXAUI),
GEN_CONF(5, 1, PHY_MODE_SATA, COMPHY_FW_MODE_SATA),
ETH_CONF(5, 2, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
ETH_CONF(5, 2, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_HS_SGMII),
GEN_CONF(5, 2, PHY_MODE_PCIE, COMPHY_FW_MODE_PCIE),
};
struct mvebu_comphy_priv {
void __iomem *base;
struct regmap *regmap;
struct device *dev;
struct clk *mg_domain_clk;
struct clk *mg_core_clk;
struct clk *axi_clk;
unsigned long cp_phys;
};
struct mvebu_comphy_lane {
@ -170,30 +269,59 @@ struct mvebu_comphy_lane {
int port;
};
static int mvebu_comphy_get_mux(int lane, int port,
enum phy_mode mode, int submode)
static int mvebu_comphy_smc(unsigned long function, unsigned long phys,
unsigned long lane, unsigned long mode)
{
struct arm_smccc_res res;
arm_smccc_smc(function, phys, lane, mode, 0, 0, 0, 0, &res);
return res.a0;
}
static int mvebu_comphy_get_mode(bool fw_mode, int lane, int port,
enum phy_mode mode, int submode)
{
int i, n = ARRAY_SIZE(mvebu_comphy_cp110_modes);
/* Ignore PCIe submode: it represents the width */
bool ignore_submode = (mode == PHY_MODE_PCIE);
const struct mvebu_comphy_conf *conf;
/* Unused PHY mux value is 0x0 */
if (mode == PHY_MODE_INVALID)
return 0;
for (i = 0; i < n; i++) {
if (mvebu_comphy_cp110_modes[i].lane == lane &&
mvebu_comphy_cp110_modes[i].port == port &&
mvebu_comphy_cp110_modes[i].mode == mode &&
mvebu_comphy_cp110_modes[i].submode == submode)
conf = &mvebu_comphy_cp110_modes[i];
if (conf->lane == lane &&
conf->port == port &&
conf->mode == mode &&
(conf->submode == submode || ignore_submode))
break;
}
if (i == n)
return -EINVAL;
return mvebu_comphy_cp110_modes[i].mux;
if (fw_mode)
return conf->fw_mode;
else
return conf->mux;
}
static void mvebu_comphy_ethernet_init_reset(struct mvebu_comphy_lane *lane)
static inline int mvebu_comphy_get_mux(int lane, int port,
enum phy_mode mode, int submode)
{
return mvebu_comphy_get_mode(false, lane, port, mode, submode);
}
static inline int mvebu_comphy_get_fw_mode(int lane, int port,
enum phy_mode mode, int submode)
{
return mvebu_comphy_get_mode(true, lane, port, mode, submode);
}
static int mvebu_comphy_ethernet_init_reset(struct mvebu_comphy_lane *lane)
{
struct mvebu_comphy_priv *priv = lane->priv;
u32 val;
@ -210,20 +338,61 @@ static void mvebu_comphy_ethernet_init_reset(struct mvebu_comphy_lane *lane)
MVEBU_COMPHY_SERDES_CFG0_PU_TX |
MVEBU_COMPHY_SERDES_CFG0_HALF_BUS |
MVEBU_COMPHY_SERDES_CFG0_GEN_RX(0xf) |
MVEBU_COMPHY_SERDES_CFG0_GEN_TX(0xf));
if (lane->submode == PHY_INTERFACE_MODE_10GKR)
MVEBU_COMPHY_SERDES_CFG0_GEN_TX(0xf) |
MVEBU_COMPHY_SERDES_CFG0_RXAUI_MODE);
switch (lane->submode) {
case PHY_INTERFACE_MODE_10GKR:
val |= MVEBU_COMPHY_SERDES_CFG0_GEN_RX(0xe) |
MVEBU_COMPHY_SERDES_CFG0_GEN_TX(0xe);
else if (lane->submode == PHY_INTERFACE_MODE_2500BASEX)
break;
case PHY_INTERFACE_MODE_RXAUI:
val |= MVEBU_COMPHY_SERDES_CFG0_GEN_RX(0xb) |
MVEBU_COMPHY_SERDES_CFG0_GEN_TX(0xb) |
MVEBU_COMPHY_SERDES_CFG0_RXAUI_MODE;
break;
case PHY_INTERFACE_MODE_2500BASEX:
val |= MVEBU_COMPHY_SERDES_CFG0_GEN_RX(0x8) |
MVEBU_COMPHY_SERDES_CFG0_GEN_TX(0x8) |
MVEBU_COMPHY_SERDES_CFG0_HALF_BUS;
else if (lane->submode == PHY_INTERFACE_MODE_SGMII)
break;
case PHY_INTERFACE_MODE_SGMII:
val |= MVEBU_COMPHY_SERDES_CFG0_GEN_RX(0x6) |
MVEBU_COMPHY_SERDES_CFG0_GEN_TX(0x6) |
MVEBU_COMPHY_SERDES_CFG0_HALF_BUS;
break;
default:
dev_err(priv->dev,
"unsupported comphy submode (%d) on lane %d\n",
lane->submode,
lane->id);
return -ENOTSUPP;
}
writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG0(lane->id));
if (lane->submode == PHY_INTERFACE_MODE_RXAUI) {
regmap_read(priv->regmap, MVEBU_COMPHY_SD1_CTRL1, &val);
switch (lane->id) {
case 2:
case 3:
val |= MVEBU_COMPHY_SD1_CTRL1_RXAUI0_EN;
break;
case 4:
case 5:
val |= MVEBU_COMPHY_SD1_CTRL1_RXAUI1_EN;
break;
default:
dev_err(priv->dev,
"RXAUI is not supported on comphy lane %d\n",
lane->id);
return -EINVAL;
}
regmap_write(priv->regmap, MVEBU_COMPHY_SD1_CTRL1, val);
}
/* reset */
val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));
val &= ~(MVEBU_COMPHY_SERDES_CFG1_RESET |
@ -264,6 +433,8 @@ static void mvebu_comphy_ethernet_init_reset(struct mvebu_comphy_lane *lane)
val &= ~MVEBU_COMPHY_LOOPBACK_DBUS_WIDTH(0x7);
val |= MVEBU_COMPHY_LOOPBACK_DBUS_WIDTH(0x1);
writel(val, priv->base + MVEBU_COMPHY_LOOPBACK(lane->id));
return 0;
}
static int mvebu_comphy_init_plls(struct mvebu_comphy_lane *lane)
@ -312,17 +483,20 @@ static int mvebu_comphy_set_mode_sgmii(struct phy *phy)
struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);
struct mvebu_comphy_priv *priv = lane->priv;
u32 val;
int err;
mvebu_comphy_ethernet_init_reset(lane);
err = mvebu_comphy_ethernet_init_reset(lane);
if (err)
return err;
val = readl(priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id));
val &= ~MVEBU_COMPHY_RX_CTRL1_CLK8T_EN;
val |= MVEBU_COMPHY_RX_CTRL1_RXCLK2X_SEL;
writel(val, priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id));
val = readl(priv->base + MVEBU_COMPHY_DLT_CTRL(lane->id));
val &= ~MVEBU_COMPHY_DLT_CTRL_DTL_FLOOP_EN;
writel(val, priv->base + MVEBU_COMPHY_DLT_CTRL(lane->id));
val = readl(priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id));
val &= ~MVEBU_COMPHY_DTL_CTRL_DTL_FLOOP_EN;
writel(val, priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id));
regmap_read(priv->regmap, MVEBU_COMPHY_CONF1(lane->id), &val);
val &= ~MVEBU_COMPHY_CONF1_USB_PCIE;
@ -337,22 +511,78 @@ static int mvebu_comphy_set_mode_sgmii(struct phy *phy)
return mvebu_comphy_init_plls(lane);
}
static int mvebu_comphy_set_mode_10gkr(struct phy *phy)
static int mvebu_comphy_set_mode_rxaui(struct phy *phy)
{
struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);
struct mvebu_comphy_priv *priv = lane->priv;
u32 val;
int err;
mvebu_comphy_ethernet_init_reset(lane);
err = mvebu_comphy_ethernet_init_reset(lane);
if (err)
return err;
val = readl(priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id));
val |= MVEBU_COMPHY_RX_CTRL1_RXCLK2X_SEL |
MVEBU_COMPHY_RX_CTRL1_CLK8T_EN;
writel(val, priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id));
val = readl(priv->base + MVEBU_COMPHY_DLT_CTRL(lane->id));
val |= MVEBU_COMPHY_DLT_CTRL_DTL_FLOOP_EN;
writel(val, priv->base + MVEBU_COMPHY_DLT_CTRL(lane->id));
val = readl(priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id));
val |= MVEBU_COMPHY_DTL_CTRL_DTL_FLOOP_EN;
writel(val, priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id));
val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG2(lane->id));
val |= MVEBU_COMPHY_SERDES_CFG2_DFE_EN;
writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG2(lane->id));
val = readl(priv->base + MVEBU_COMPHY_DFE_RES(lane->id));
val |= MVEBU_COMPHY_DFE_RES_FORCE_GEN_TBL;
writel(val, priv->base + MVEBU_COMPHY_DFE_RES(lane->id));
val = readl(priv->base + MVEBU_COMPHY_GEN1_S0(lane->id));
val &= ~MVEBU_COMPHY_GEN1_S0_TX_EMPH(0xf);
val |= MVEBU_COMPHY_GEN1_S0_TX_EMPH(0xd);
writel(val, priv->base + MVEBU_COMPHY_GEN1_S0(lane->id));
val = readl(priv->base + MVEBU_COMPHY_GEN1_S1(lane->id));
val &= ~(MVEBU_COMPHY_GEN1_S1_RX_MUL_PI(0x7) |
MVEBU_COMPHY_GEN1_S1_RX_MUL_PF(0x7));
val |= MVEBU_COMPHY_GEN1_S1_RX_MUL_PI(0x1) |
MVEBU_COMPHY_GEN1_S1_RX_MUL_PF(0x1) |
MVEBU_COMPHY_GEN1_S1_RX_DFE_EN;
writel(val, priv->base + MVEBU_COMPHY_GEN1_S1(lane->id));
val = readl(priv->base + MVEBU_COMPHY_COEF(lane->id));
val &= ~(MVEBU_COMPHY_COEF_DFE_EN | MVEBU_COMPHY_COEF_DFE_CTRL);
writel(val, priv->base + MVEBU_COMPHY_COEF(lane->id));
val = readl(priv->base + MVEBU_COMPHY_GEN1_S4(lane->id));
val &= ~MVEBU_COMPHY_GEN1_S4_DFE_RES(0x3);
val |= MVEBU_COMPHY_GEN1_S4_DFE_RES(0x1);
writel(val, priv->base + MVEBU_COMPHY_GEN1_S4(lane->id));
return mvebu_comphy_init_plls(lane);
}
static int mvebu_comphy_set_mode_10gkr(struct phy *phy)
{
struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);
struct mvebu_comphy_priv *priv = lane->priv;
u32 val;
int err;
err = mvebu_comphy_ethernet_init_reset(lane);
if (err)
return err;
val = readl(priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id));
val |= MVEBU_COMPHY_RX_CTRL1_RXCLK2X_SEL |
MVEBU_COMPHY_RX_CTRL1_CLK8T_EN;
writel(val, priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id));
val = readl(priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id));
val |= MVEBU_COMPHY_DTL_CTRL_DTL_FLOOP_EN;
writel(val, priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id));
/* Speed divider */
val = readl(priv->base + MVEBU_COMPHY_SPEED_DIV(lane->id));
@ -476,7 +706,7 @@ static int mvebu_comphy_set_mode_10gkr(struct phy *phy)
return mvebu_comphy_init_plls(lane);
}
static int mvebu_comphy_power_on(struct phy *phy)
static int mvebu_comphy_power_on_legacy(struct phy *phy)
{
struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);
struct mvebu_comphy_priv *priv = lane->priv;
@ -502,6 +732,9 @@ static int mvebu_comphy_power_on(struct phy *phy)
case PHY_INTERFACE_MODE_2500BASEX:
ret = mvebu_comphy_set_mode_sgmii(phy);
break;
case PHY_INTERFACE_MODE_RXAUI:
ret = mvebu_comphy_set_mode_rxaui(phy);
break;
case PHY_INTERFACE_MODE_10GKR:
ret = mvebu_comphy_set_mode_10gkr(phy);
break;
@ -517,26 +750,110 @@ static int mvebu_comphy_power_on(struct phy *phy)
return ret;
}
static int mvebu_comphy_power_on(struct phy *phy)
{
struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);
struct mvebu_comphy_priv *priv = lane->priv;
int fw_mode, fw_speed;
u32 fw_param = 0;
int ret;
fw_mode = mvebu_comphy_get_fw_mode(lane->id, lane->port,
lane->mode, lane->submode);
if (fw_mode < 0)
goto try_legacy;
/* Try SMC flow first */
switch (lane->mode) {
case PHY_MODE_ETHERNET:
switch (lane->submode) {
case PHY_INTERFACE_MODE_RXAUI:
dev_dbg(priv->dev, "set lane %d to RXAUI mode\n",
lane->id);
fw_speed = 0;
break;
case PHY_INTERFACE_MODE_SGMII:
dev_dbg(priv->dev, "set lane %d to 1000BASE-X mode\n",
lane->id);
fw_speed = COMPHY_FW_SPEED_1250;
break;
case PHY_INTERFACE_MODE_2500BASEX:
dev_dbg(priv->dev, "set lane %d to 2500BASE-X mode\n",
lane->id);
fw_speed = COMPHY_FW_SPEED_3125;
break;
case PHY_INTERFACE_MODE_10GKR:
dev_dbg(priv->dev, "set lane %d to 10G-KR mode\n",
lane->id);
fw_speed = COMPHY_FW_SPEED_103125;
break;
default:
dev_err(priv->dev, "unsupported Ethernet mode (%d)\n",
lane->submode);
return -ENOTSUPP;
}
fw_param = COMPHY_FW_PARAM_ETH(fw_mode, lane->port, fw_speed);
break;
case PHY_MODE_USB_HOST_SS:
case PHY_MODE_USB_DEVICE_SS:
dev_dbg(priv->dev, "set lane %d to USB3 mode\n", lane->id);
fw_param = COMPHY_FW_PARAM(fw_mode, lane->port);
break;
case PHY_MODE_SATA:
dev_dbg(priv->dev, "set lane %d to SATA mode\n", lane->id);
fw_param = COMPHY_FW_PARAM(fw_mode, lane->port);
break;
case PHY_MODE_PCIE:
dev_dbg(priv->dev, "set lane %d to PCIe mode (x%d)\n", lane->id,
lane->submode);
fw_param = COMPHY_FW_PARAM_PCIE(fw_mode, lane->port,
lane->submode);
break;
default:
dev_err(priv->dev, "unsupported PHY mode (%d)\n", lane->mode);
return -ENOTSUPP;
}
ret = mvebu_comphy_smc(COMPHY_SIP_POWER_ON, priv->cp_phys, lane->id,
fw_param);
if (!ret)
return ret;
if (ret == COMPHY_FW_NOT_SUPPORTED)
dev_err(priv->dev,
"unsupported SMC call, try updating your firmware\n");
dev_warn(priv->dev,
"Firmware could not configure PHY %d with mode %d (ret: %d), trying legacy method\n",
lane->id, lane->mode, ret);
try_legacy:
/* Fallback to Linux's implementation */
return mvebu_comphy_power_on_legacy(phy);
}
static int mvebu_comphy_set_mode(struct phy *phy,
enum phy_mode mode, int submode)
{
struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);
if (mode != PHY_MODE_ETHERNET)
return -EINVAL;
if (submode == PHY_INTERFACE_MODE_1000BASEX)
submode = PHY_INTERFACE_MODE_SGMII;
if (mvebu_comphy_get_mux(lane->id, lane->port, mode, submode) < 0)
if (mvebu_comphy_get_fw_mode(lane->id, lane->port, mode, submode) < 0)
return -EINVAL;
lane->mode = mode;
lane->submode = submode;
/* PCIe submode represents the width */
if (mode == PHY_MODE_PCIE && !lane->submode)
lane->submode = 1;
return 0;
}
static int mvebu_comphy_power_off(struct phy *phy)
static int mvebu_comphy_power_off_legacy(struct phy *phy)
{
struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);
struct mvebu_comphy_priv *priv = lane->priv;
@ -559,6 +876,21 @@ static int mvebu_comphy_power_off(struct phy *phy)
return 0;
}
static int mvebu_comphy_power_off(struct phy *phy)
{
struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);
struct mvebu_comphy_priv *priv = lane->priv;
int ret;
ret = mvebu_comphy_smc(COMPHY_SIP_POWER_OFF, priv->cp_phys,
lane->id, 0);
if (!ret)
return ret;
/* Fallback to Linux's implementation */
return mvebu_comphy_power_off_legacy(phy);
}
static const struct phy_ops mvebu_comphy_ops = {
.power_on = mvebu_comphy_power_on,
.power_off = mvebu_comphy_power_off,
@ -585,12 +917,72 @@ static struct phy *mvebu_comphy_xlate(struct device *dev,
return phy;
}
static int mvebu_comphy_init_clks(struct mvebu_comphy_priv *priv)
{
int ret;
priv->mg_domain_clk = devm_clk_get(priv->dev, "mg_clk");
if (IS_ERR(priv->mg_domain_clk))
return PTR_ERR(priv->mg_domain_clk);
ret = clk_prepare_enable(priv->mg_domain_clk);
if (ret < 0)
return ret;
priv->mg_core_clk = devm_clk_get(priv->dev, "mg_core_clk");
if (IS_ERR(priv->mg_core_clk)) {
ret = PTR_ERR(priv->mg_core_clk);
goto dis_mg_domain_clk;
}
ret = clk_prepare_enable(priv->mg_core_clk);
if (ret < 0)
goto dis_mg_domain_clk;
priv->axi_clk = devm_clk_get(priv->dev, "axi_clk");
if (IS_ERR(priv->axi_clk)) {
ret = PTR_ERR(priv->axi_clk);
goto dis_mg_core_clk;
}
ret = clk_prepare_enable(priv->axi_clk);
if (ret < 0)
goto dis_mg_core_clk;
return 0;
dis_mg_core_clk:
clk_disable_unprepare(priv->mg_core_clk);
dis_mg_domain_clk:
clk_disable_unprepare(priv->mg_domain_clk);
priv->mg_domain_clk = NULL;
priv->mg_core_clk = NULL;
priv->axi_clk = NULL;
return ret;
};
static void mvebu_comphy_disable_unprepare_clks(struct mvebu_comphy_priv *priv)
{
if (priv->axi_clk)
clk_disable_unprepare(priv->axi_clk);
if (priv->mg_core_clk)
clk_disable_unprepare(priv->mg_core_clk);
if (priv->mg_domain_clk)
clk_disable_unprepare(priv->mg_domain_clk);
}
static int mvebu_comphy_probe(struct platform_device *pdev)
{
struct mvebu_comphy_priv *priv;
struct phy_provider *provider;
struct device_node *child;
struct resource *res;
int ret;
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
@ -607,10 +999,26 @@ static int mvebu_comphy_probe(struct platform_device *pdev)
if (IS_ERR(priv->base))
return PTR_ERR(priv->base);
/*
* Ignore error if clocks have not been initialized properly for DT
* compatibility reasons.
*/
ret = mvebu_comphy_init_clks(priv);
if (ret) {
if (ret == -EPROBE_DEFER)
return ret;
dev_warn(&pdev->dev, "cannot initialize clocks\n");
}
/*
* Hack to retrieve a physical offset relative to this CP that will be
* given to the firmware
*/
priv->cp_phys = res->start;
for_each_available_child_of_node(pdev->dev.of_node, child) {
struct mvebu_comphy_lane *lane;
struct phy *phy;
int ret;
u32 val;
ret = of_property_read_u32(child, "reg", &val);
@ -626,30 +1034,45 @@ static int mvebu_comphy_probe(struct platform_device *pdev)
}
lane = devm_kzalloc(&pdev->dev, sizeof(*lane), GFP_KERNEL);
if (!lane)
return -ENOMEM;
if (!lane) {
of_node_put(child);
ret = -ENOMEM;
goto disable_clks;
}
phy = devm_phy_create(&pdev->dev, child, &mvebu_comphy_ops);
if (IS_ERR(phy))
return PTR_ERR(phy);
if (IS_ERR(phy)) {
of_node_put(child);
ret = PTR_ERR(phy);
goto disable_clks;
}
lane->priv = priv;
lane->mode = PHY_MODE_INVALID;
lane->submode = PHY_INTERFACE_MODE_NA;
lane->id = val;
lane->port = -1;
phy_set_drvdata(phy, lane);
/*
* Once all modes are supported in this driver we should call
* All modes are supported in this driver so we could call
* mvebu_comphy_power_off(phy) here to avoid relying on the
* bootloader/firmware configuration.
* bootloader/firmware configuration, but for compatibility
* reasons we cannot de-configure the COMPHY without being sure
* that the firmware is up-to-date and fully-featured.
*/
}
dev_set_drvdata(&pdev->dev, priv);
provider = devm_of_phy_provider_register(&pdev->dev,
mvebu_comphy_xlate);
return PTR_ERR_OR_ZERO(provider);
disable_clks:
mvebu_comphy_disable_unprepare_clks(priv);
return ret;
}
static const struct of_device_id mvebu_comphy_of_match_table[] = {

10
drivers/phy/phy-core.c
View File

@ -394,6 +394,16 @@ int phy_reset(struct phy *phy)
}
EXPORT_SYMBOL_GPL(phy_reset);
/**
* phy_calibrate() - Tunes the phy hw parameters for current configuration
* @phy: the phy returned by phy_get()
*
* Used to calibrate phy hardware, typically by adjusting some parameters in
* runtime, which are otherwise lost after host controller reset and cannot
* be applied in phy_init() or phy_power_on().
*
* Returns: 0 if successful, an negative error code otherwise
*/
int phy_calibrate(struct phy *phy)
{
int ret;

44
drivers/phy/qualcomm/phy-qcom-qmp.c
View File

@ -35,7 +35,7 @@
#define PLL_READY_GATE_EN BIT(3)
/* QPHY_PCS_STATUS bit */
#define PHYSTATUS BIT(6)
/* QPHY_COM_PCS_READY_STATUS bit */
/* QPHY_PCS_READY_STATUS & QPHY_COM_PCS_READY_STATUS bit */
#define PCS_READY BIT(0)
/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
@ -115,6 +115,7 @@ enum qphy_reg_layout {
QPHY_SW_RESET,
QPHY_START_CTRL,
QPHY_PCS_READY_STATUS,
QPHY_PCS_STATUS,
QPHY_PCS_AUTONOMOUS_MODE_CTRL,
QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
@ -133,7 +134,7 @@ static const unsigned int pciephy_regs_layout[] = {
[QPHY_FLL_MAN_CODE] = 0xd4,
[QPHY_SW_RESET] = 0x00,
[QPHY_START_CTRL] = 0x08,
[QPHY_PCS_READY_STATUS] = 0x174,
[QPHY_PCS_STATUS] = 0x174,
};
static const unsigned int usb3phy_regs_layout[] = {
@ -144,7 +145,7 @@ static const unsigned int usb3phy_regs_layout[] = {
[QPHY_FLL_MAN_CODE] = 0xd0,
[QPHY_SW_RESET] = 0x00,
[QPHY_START_CTRL] = 0x08,
[QPHY_PCS_READY_STATUS] = 0x17c,
[QPHY_PCS_STATUS] = 0x17c,
[QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4,
[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0d8,
[QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178,
@ -153,7 +154,7 @@ static const unsigned int usb3phy_regs_layout[] = {
static const unsigned int qmp_v3_usb3phy_regs_layout[] = {
[QPHY_SW_RESET] = 0x00,
[QPHY_START_CTRL] = 0x08,
[QPHY_PCS_READY_STATUS] = 0x174,
[QPHY_PCS_STATUS] = 0x174,
[QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8,
[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0dc,
[QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170,
@ -911,7 +912,6 @@ struct qmp_phy_cfg {
unsigned int start_ctrl;
unsigned int pwrdn_ctrl;
unsigned int mask_pcs_ready;
unsigned int mask_com_pcs_ready;
/* true, if PHY has a separate PHY_COM control block */
@ -1074,7 +1074,6 @@ static const struct qmp_phy_cfg msm8996_pciephy_cfg = {
.start_ctrl = PCS_START | PLL_READY_GATE_EN,
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
.mask_pcs_ready = PHYSTATUS,
.mask_com_pcs_ready = PCS_READY,
.has_phy_com_ctrl = true,
@ -1106,7 +1105,6 @@ static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
.start_ctrl = SERDES_START | PCS_START,
.pwrdn_ctrl = SW_PWRDN,
.mask_pcs_ready = PHYSTATUS,
};
/* list of resets */
@ -1136,7 +1134,6 @@ static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
.start_ctrl = SERDES_START | PCS_START,
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
.mask_pcs_ready = PHYSTATUS,
.has_phy_com_ctrl = false,
.has_lane_rst = false,
@ -1167,7 +1164,6 @@ static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
.start_ctrl = SERDES_START | PCS_START,
.pwrdn_ctrl = SW_PWRDN,
.mask_pcs_ready = PHYSTATUS,
.has_pwrdn_delay = true,
.pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
@ -1199,7 +1195,6 @@ static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
.start_ctrl = SERDES_START | PCS_START,
.pwrdn_ctrl = SW_PWRDN,
.mask_pcs_ready = PHYSTATUS,
.has_pwrdn_delay = true,
.pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
@ -1226,7 +1221,6 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
.start_ctrl = SERDES_START,
.pwrdn_ctrl = SW_PWRDN,
.mask_pcs_ready = PCS_READY,
.is_dual_lane_phy = true,
.no_pcs_sw_reset = true,
@ -1254,7 +1248,6 @@ static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
.start_ctrl = SERDES_START | PCS_START,
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
.mask_pcs_ready = PHYSTATUS,
};
static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
@ -1279,7 +1272,6 @@ static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
.start_ctrl = SERDES_START | PCS_START,
.pwrdn_ctrl = SW_PWRDN,
.mask_pcs_ready = PHYSTATUS,
.is_dual_lane_phy = true,
};
@ -1457,7 +1449,7 @@ static int qcom_qmp_phy_enable(struct phy *phy)
void __iomem *pcs = qphy->pcs;
void __iomem *dp_com = qmp->dp_com;
void __iomem *status;
unsigned int mask, val;
unsigned int mask, val, ready;
int ret;
dev_vdbg(qmp->dev, "Initializing QMP phy\n");
@ -1545,10 +1537,17 @@ static int qcom_qmp_phy_enable(struct phy *phy)
/* start SerDes and Phy-Coding-Sublayer */
qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
mask = cfg->mask_pcs_ready;
if (cfg->type == PHY_TYPE_UFS) {
status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
mask = PCS_READY;
ready = PCS_READY;
} else {
status = pcs + cfg->regs[QPHY_PCS_STATUS];
mask = PHYSTATUS;
ready = 0;
}
ret = readl_poll_timeout(status, val, val & mask, 10,
ret = readl_poll_timeout(status, val, (val & mask) == ready, 10,
PHY_INIT_COMPLETE_TIMEOUT);
if (ret) {
dev_err(qmp->dev, "phy initialization timed-out\n");
@ -2093,8 +2092,7 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev)
if (ret) {
dev_err(dev, "failed to create lane%d phy, %d\n",
id, ret);
pm_runtime_disable(dev);
return ret;
goto err_node_put;
}
/*
@ -2105,8 +2103,7 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev)
if (ret) {
dev_err(qmp->dev,
"failed to register pipe clock source\n");
pm_runtime_disable(dev);
return ret;
goto err_node_put;
}
id++;
}
@ -2118,6 +2115,11 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev)
pm_runtime_disable(dev);
return PTR_ERR_OR_ZERO(phy_provider);
err_node_put:
pm_runtime_disable(dev);
of_node_put(child);
return ret;
}
static struct platform_driver qcom_qmp_phy_driver = {

2
drivers/phy/renesas/phy-rcar-gen3-usb2.c
View File

@ -61,6 +61,7 @@
USB2_OBINT_IDDIGCHG)
/* VBCTRL */
#define USB2_VBCTRL_OCCLREN BIT(16)
#define USB2_VBCTRL_DRVVBUSSEL BIT(8)
/* LINECTRL1 */
@ -374,6 +375,7 @@ static void rcar_gen3_init_otg(struct rcar_gen3_chan *ch)
writel(val, usb2_base + USB2_LINECTRL1);
val = readl(usb2_base + USB2_VBCTRL);
val &= ~USB2_VBCTRL_OCCLREN;
writel(val | USB2_VBCTRL_DRVVBUSSEL, usb2_base + USB2_VBCTRL);
val = readl(usb2_base + USB2_ADPCTRL);
writel(val | USB2_ADPCTRL_IDPULLUP, usb2_base + USB2_ADPCTRL);

2
drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
View File

@ -198,7 +198,7 @@
#define RK3328_BYPASS_TERM_RESISTOR_CALIB BIT(7)
#define RK3328_TERM_RESISTOR_CALIB_SPEED_14_8(x) UPDATE((x) >> 8, 6, 0)
/* REG:0xc6 */
#define RK3328_TERM_RESISTOR_CALIB_SPEED_7_0(x) UPDATE(x, 7, 9)
#define RK3328_TERM_RESISTOR_CALIB_SPEED_7_0(x) UPDATE(x, 7, 0)
/* REG:0xc7 */
#define RK3328_TERM_RESISTOR_50 UPDATE(0, 2, 1)
#define RK3328_TERM_RESISTOR_62_5 UPDATE(1, 2, 1)

1
drivers/phy/samsung/phy-exynos-dp-video.c
View File

@ -109,6 +109,7 @@ static struct platform_driver exynos_dp_video_phy_driver = {
.driver = {
.name = "exynos-dp-video-phy",
.of_match_table = exynos_dp_video_phy_of_match,
.suppress_bind_attrs = true,
}
};
module_platform_driver(exynos_dp_video_phy_driver);

1
drivers/phy/samsung/phy-exynos-mipi-video.c
View File

@ -359,6 +359,7 @@ static struct platform_driver exynos_mipi_video_phy_driver = {
.driver = {
.of_match_table = exynos_mipi_video_phy_of_match,
.name = "exynos-mipi-video-phy",
.suppress_bind_attrs = true,
}
};
module_platform_driver(exynos_mipi_video_phy_driver);

1
drivers/phy/samsung/phy-exynos-pcie.c
View File

@ -272,6 +272,7 @@ static struct platform_driver exynos_pcie_phy_driver = {
.driver = {
.of_match_table = exynos_pcie_phy_match,
.name = "exynos_pcie_phy",
.suppress_bind_attrs = true,
}
};

1
drivers/phy/samsung/phy-exynos5-usbdrd.c
View File

@ -953,6 +953,7 @@ static struct platform_driver exynos5_usb3drd_phy = {
.driver = {
.of_match_table = exynos5_usbdrd_phy_of_match,
.name = "exynos5_usb3drd_phy",
.suppress_bind_attrs = true,
}
};

1
drivers/phy/samsung/phy-exynos5250-sata.c
View File

@ -237,6 +237,7 @@ static struct platform_driver exynos_sata_phy_driver = {
.driver = {
.of_match_table = exynos_sata_phy_of_match,
.name = "samsung,sata-phy",
.suppress_bind_attrs = true,
}
};
module_platform_driver(exynos_sata_phy_driver);

1
drivers/phy/samsung/phy-samsung-usb2.c
View File

@ -250,6 +250,7 @@ static struct platform_driver samsung_usb2_phy_driver = {
.driver = {
.of_match_table = samsung_usb2_phy_of_match,
.name = "samsung-usb2-phy",
.suppress_bind_attrs = true,
}
};

33
drivers/phy/ti/phy-am654-serdes.c
View File

@ -405,6 +405,7 @@ static int serdes_am654_clk_register(struct serdes_am654 *am654_phy,
const __be32 *addr;
unsigned int reg;
struct clk *clk;
int ret = 0;
mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
if (!mux)
@ -413,34 +414,40 @@ static int serdes_am654_clk_register(struct serdes_am654 *am654_phy,
init = &mux->clk_data;
regmap_node = of_parse_phandle(node, "ti,serdes-clk", 0);
of_node_put(regmap_node);
if (!regmap_node) {
dev_err(dev, "Fail to get serdes-clk node\n");
return -ENODEV;
ret = -ENODEV;
goto out_put_node;
}
regmap = syscon_node_to_regmap(regmap_node->parent);
if (IS_ERR(regmap)) {
dev_err(dev, "Fail to get Syscon regmap\n");
return PTR_ERR(regmap);
ret = PTR_ERR(regmap);
goto out_put_node;
}
num_parents = of_clk_get_parent_count(node);
if (num_parents < 2) {
dev_err(dev, "SERDES clock must have parents\n");
return -EINVAL;
ret = -EINVAL;
goto out_put_node;
}
parent_names = devm_kzalloc(dev, (sizeof(char *) * num_parents),
GFP_KERNEL);
if (!parent_names)
return -ENOMEM;
if (!parent_names) {
ret = -ENOMEM;
goto out_put_node;
}
of_clk_parent_fill(node, parent_names, num_parents);
addr = of_get_address(regmap_node, 0, NULL, NULL);
if (!addr)
return -EINVAL;
if (!addr) {
ret = -EINVAL;
goto out_put_node;
}
reg = be32_to_cpu(*addr);
@ -456,12 +463,16 @@ static int serdes_am654_clk_register(struct serdes_am654 *am654_phy,
mux->hw.init = init;
clk = devm_clk_register(dev, &mux->hw);
if (IS_ERR(clk))
return PTR_ERR(clk);
if (IS_ERR(clk)) {
ret = PTR_ERR(clk);
goto out_put_node;
}
am654_phy->clks[clock_num] = clk;
return 0;
out_put_node:
of_node_put(regmap_node);
return ret;
}
static const struct of_device_id serdes_am654_id_table[] = {

11
include/dt-bindings/phy/phy-lantiq-vrx200-pcie.h Normal file
View File

@ -0,0 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) 2019 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
*/
#define LANTIQ_PCIE_PHY_MODE_25MHZ 0
#define LANTIQ_PCIE_PHY_MODE_25MHZ_SSC 1
#define LANTIQ_PCIE_PHY_MODE_36MHZ 2
#define LANTIQ_PCIE_PHY_MODE_36MHZ_SSC 3
#define LANTIQ_PCIE_PHY_MODE_100MHZ 4
#define LANTIQ_PCIE_PHY_MODE_100MHZ_SSC 5