Minki/linux
1
0
Fork 1
mirror of https://github.com/torvalds/linux.git synced 2024-11-11 06:31:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

ASoC: codecs: jz4725b: use right control for Master Playback

Browse Source 
At the moment DAC control is used as Master Playback control, this is
incorrect as DAC's output goes to a Mixer.

The Mixer couples analog input from 4 sources (DAC, Line In, Mic 1,
 Mic 2) each input has its own gain & mute controls.

Output of the Mixer goes to Output Stage control which is the best suite
for the new Playback Master. However, it doesn't have mute capability.

The patch implements Output Stage control as a new master and renames
old Master to DAC. Rest of mixer inputs will be implemented in the next
patch in the series.

Manual states that Output stage control (16.6.3.5 Programmable output
amplifier: PGAT) gain varies from -33.5dB to +4.5dB, gain step isn't
fixed and has 3 opts.

Signed-off-by: Siarhei Volkau <lis8215@gmail.com>
Link: https://lore.kernel.org/r/20221016132648.3011729-6-lis8215@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Siarhei Volkau 2022-10-16 16:26:46 +03:00 committed by Mark Brown
parent 80852f8268
commit e6233ee250
No known key found for this signature in database
GPG Key ID: 24D68B725D5487D0
1 changed files with 19 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

21
sound/soc/codecs/jz4725b.c
View File

@ -136,6 +136,12 @@ enum {
#define REG_CGR3_GO1L_OFFSET 0 #define REG_CGR3_GO1L_OFFSET 0
#define REG_CGR3_GO1L_MASK (0x1f << REG_CGR3_GO1L_OFFSET) #define REG_CGR3_GO1L_MASK (0x1f << REG_CGR3_GO1L_OFFSET)
#define REG_CGR8_GOR_OFFSET 0
#define REG_CGR8_GOR_MASK (0x1f << REG_CGR8_GOR_OFFSET)
#define REG_CGR9_GOL_OFFSET 0
#define REG_CGR9_GOL_MASK (0x1f << REG_CGR9_GOL_OFFSET)
#define REG_CGR10_GIL_OFFSET 0 #define REG_CGR10_GIL_OFFSET 0
#define REG_CGR10_GIR_OFFSET 4 #define REG_CGR10_GIR_OFFSET 4
@ -147,9 +153,14 @@ struct jz_icdc {
static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(jz4725b_adc_tlv, 0, 150, 0); static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(jz4725b_adc_tlv, 0, 150, 0);
static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(jz4725b_dac_tlv, -2250, 150, 0); static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(jz4725b_dac_tlv, -2250, 150, 0);
static const SNDRV_CTL_TLVD_DECLARE_DB_RANGE(jz4725b_out_tlv,
0, 11, TLV_DB_SCALE_ITEM(-3350, 200, 0),
12, 23, TLV_DB_SCALE_ITEM(-1050, 100, 0),
24, 31, TLV_DB_SCALE_ITEM( 100, 50, 0),
);
static const struct snd_kcontrol_new jz4725b_codec_controls[] = { static const struct snd_kcontrol_new jz4725b_codec_controls[] = {
SOC_DOUBLE_TLV("Master Playback Volume", SOC_DOUBLE_TLV("DAC Playback Volume",
JZ4725B_CODEC_REG_CGR1, JZ4725B_CODEC_REG_CGR1,
REG_CGR1_GODL_OFFSET, REG_CGR1_GODL_OFFSET,
REG_CGR1_GODR_OFFSET, REG_CGR1_GODR_OFFSET,
@ -160,7 +171,13 @@ static const struct snd_kcontrol_new jz4725b_codec_controls[] = {
REG_CGR10_GIR_OFFSET, REG_CGR10_GIR_OFFSET,
0xf, 0, jz4725b_adc_tlv), 0xf, 0, jz4725b_adc_tlv),
SOC_SINGLE("Master Playback Switch", JZ4725B_CODEC_REG_CR1, SOC_DOUBLE_R_TLV("Master Playback Volume",
JZ4725B_CODEC_REG_CGR9,
JZ4725B_CODEC_REG_CGR8,
REG_CGR8_GOR_OFFSET,
0x1f, 1, jz4725b_out_tlv),
SOC_SINGLE("DAC Playback Switch", JZ4725B_CODEC_REG_CR1,
REG_CR1_DAC_MUTE_OFFSET, 1, 1), REG_CR1_DAC_MUTE_OFFSET, 1, 1),
SOC_SINGLE("Deemphasize Filter Playback Switch", SOC_SINGLE("Deemphasize Filter Playback Switch",