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spi: sh-msiof: Enforce fixed DTDL for R-Car H3
Documentation says only DTDL of 200 is allowed for this SoC.
Fixes: 4286db8456
("spi: sh-msiof: Add R-Car Gen 2 and 3 fallback bindings")
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://msgid.link/r/20231212081239.14254-1-wsa+renesas@sang-engineering.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
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@ -29,12 +29,15 @@
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#include <asm/unaligned.h>
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#include <asm/unaligned.h>
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#define SH_MSIOF_FLAG_FIXED_DTDL_200 BIT(0)
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struct sh_msiof_chipdata {
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struct sh_msiof_chipdata {
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u32 bits_per_word_mask;
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u32 bits_per_word_mask;
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u16 tx_fifo_size;
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u16 tx_fifo_size;
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u16 rx_fifo_size;
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u16 rx_fifo_size;
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u16 ctlr_flags;
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u16 ctlr_flags;
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u16 min_div_pow;
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u16 min_div_pow;
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u32 flags;
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};
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};
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struct sh_msiof_spi_priv {
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struct sh_msiof_spi_priv {
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@ -1072,6 +1075,16 @@ static const struct sh_msiof_chipdata rcar_gen3_data = {
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.min_div_pow = 1,
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.min_div_pow = 1,
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};
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};
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static const struct sh_msiof_chipdata rcar_r8a7795_data = {
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.bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16) |
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SPI_BPW_MASK(24) | SPI_BPW_MASK(32),
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.tx_fifo_size = 64,
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.rx_fifo_size = 64,
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.ctlr_flags = SPI_CONTROLLER_MUST_TX,
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.min_div_pow = 1,
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.flags = SH_MSIOF_FLAG_FIXED_DTDL_200,
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};
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static const struct of_device_id sh_msiof_match[] __maybe_unused = {
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static const struct of_device_id sh_msiof_match[] __maybe_unused = {
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{ .compatible = "renesas,sh-mobile-msiof", .data = &sh_data },
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{ .compatible = "renesas,sh-mobile-msiof", .data = &sh_data },
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{ .compatible = "renesas,msiof-r8a7743", .data = &rcar_gen2_data },
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{ .compatible = "renesas,msiof-r8a7743", .data = &rcar_gen2_data },
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@ -1082,6 +1095,7 @@ static const struct of_device_id sh_msiof_match[] __maybe_unused = {
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{ .compatible = "renesas,msiof-r8a7793", .data = &rcar_gen2_data },
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{ .compatible = "renesas,msiof-r8a7793", .data = &rcar_gen2_data },
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{ .compatible = "renesas,msiof-r8a7794", .data = &rcar_gen2_data },
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{ .compatible = "renesas,msiof-r8a7794", .data = &rcar_gen2_data },
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{ .compatible = "renesas,rcar-gen2-msiof", .data = &rcar_gen2_data },
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{ .compatible = "renesas,rcar-gen2-msiof", .data = &rcar_gen2_data },
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{ .compatible = "renesas,msiof-r8a7795", .data = &rcar_r8a7795_data },
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{ .compatible = "renesas,msiof-r8a7796", .data = &rcar_gen3_data },
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{ .compatible = "renesas,msiof-r8a7796", .data = &rcar_gen3_data },
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{ .compatible = "renesas,rcar-gen3-msiof", .data = &rcar_gen3_data },
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{ .compatible = "renesas,rcar-gen3-msiof", .data = &rcar_gen3_data },
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{ .compatible = "renesas,rcar-gen4-msiof", .data = &rcar_gen3_data },
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{ .compatible = "renesas,rcar-gen4-msiof", .data = &rcar_gen3_data },
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@ -1279,6 +1293,9 @@ static int sh_msiof_spi_probe(struct platform_device *pdev)
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return -ENXIO;
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return -ENXIO;
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}
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}
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if (chipdata->flags & SH_MSIOF_FLAG_FIXED_DTDL_200)
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info->dtdl = 200;
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if (info->mode == MSIOF_SPI_TARGET)
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if (info->mode == MSIOF_SPI_TARGET)
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ctlr = spi_alloc_target(&pdev->dev,
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ctlr = spi_alloc_target(&pdev->dev,
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sizeof(struct sh_msiof_spi_priv));
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sizeof(struct sh_msiof_spi_priv));
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