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Clock Fixes for the Allwinner SoCs, 4.8 Edition
The usual bunch of fixes to the our clock drivers, mostly targetted to the brand new sunxi-ng drivers. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJX0GrSAAoJEBx+YmzsjxAg6skP/2Q/7rpL92sKten40JB3Lbsd H34VIytVAur3TjBHdQh9JMcIAAenEfyCf2rF0bolstesJsuWWKF9PcJl+yYb5CWK X9uy5tGQiR2//kmiXVXiSYfQa661SVF0eOEIPzjCaXNTVzfrFNN92RINoJkDmg7Q gNphHxzjHkjxVLaDUYyTWje8h9qYlaEu0Blt1TA1+q4NqVvLkWIrVF4e68unKkqb 6oj7Acvj0B0EqGxXEh5xI9StGFWDMMKAZfTbqPpt+2mFlH5yP4CPVt9/3NlHUaoC 3k9Z1wER+dgkjaDj2Z0s6UBMchm+NUJ6gWRYrAUOUsOhqMk523kjVxqG/bm8ZYGu u0TTD0kehTGFAMh8gE/IbLx649kbGsg0Fn9XGtajfs1WLnOs3jsIQcrEruPa8z+u 86Zc6Ruikb/Llecr1aUbLpa4s7yZASmLWOH516My8oXIMe8k+JoOJvnBq0IM7+LB VeD3cV5KD5d4HBCGdnXtMN4pN9xcw4uIKNXXOgM5MSR/E3lxq9HhxNyYUK9I9/1x FKLGdJ1Z6tl+5osW0QjkhKCf7R4w6Rwib9f0MDR6NrsI4qMJFx5BhABKOfuHwXWq CtxxM2Ktz0WLYaA9faxG7G8mAwYDqaR8MseQ8bqOeE8cXleVoWupGAUrvwQmiqaw o4nfXYUwDJ6J42qfhNRj =axNZ -----END PGP SIGNATURE----- Merge tag 'sunxi-clk-fixes-for-4.8' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-fixes Clock Fixes for the Allwinner SoCs, 4.8 Edition The usual bunch of fixes to the our clock drivers, mostly targetted to the brand new sunxi-ng drivers. * tag 'sunxi-clk-fixes-for-4.8' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux: clk: sunxi-ng: Fix wrong reset register offsets clk: sunxi-ng: nk: Make ccu_nk_find_best static clk: sunxi-ng: Fix inverted test condition in ccu_helper_wait_for_lock clk: sunxi: Fix return value check in sun8i_a23_mbus_setup() clk: sunxi: pll2: Fix return value check in sun4i_pll2_setup()
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@ -783,14 +783,14 @@ static struct ccu_reset_map sun8i_h3_ccu_resets[] = {
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[RST_BUS_I2S1] = { 0x2d0, BIT(13) },
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[RST_BUS_I2S2] = { 0x2d0, BIT(14) },
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[RST_BUS_I2C0] = { 0x2d4, BIT(0) },
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[RST_BUS_I2C1] = { 0x2d4, BIT(1) },
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[RST_BUS_I2C2] = { 0x2d4, BIT(2) },
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[RST_BUS_UART0] = { 0x2d4, BIT(16) },
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[RST_BUS_UART1] = { 0x2d4, BIT(17) },
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[RST_BUS_UART2] = { 0x2d4, BIT(18) },
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[RST_BUS_UART3] = { 0x2d4, BIT(19) },
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[RST_BUS_SCR] = { 0x2d4, BIT(20) },
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[RST_BUS_I2C0] = { 0x2d8, BIT(0) },
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[RST_BUS_I2C1] = { 0x2d8, BIT(1) },
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[RST_BUS_I2C2] = { 0x2d8, BIT(2) },
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[RST_BUS_UART0] = { 0x2d8, BIT(16) },
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[RST_BUS_UART1] = { 0x2d8, BIT(17) },
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[RST_BUS_UART2] = { 0x2d8, BIT(18) },
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[RST_BUS_UART3] = { 0x2d8, BIT(19) },
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[RST_BUS_SCR] = { 0x2d8, BIT(20) },
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};
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static const struct sunxi_ccu_desc sun8i_h3_ccu_desc = {
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@ -14,9 +14,9 @@
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#include "ccu_gate.h"
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#include "ccu_nk.h"
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void ccu_nk_find_best(unsigned long parent, unsigned long rate,
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unsigned int max_n, unsigned int max_k,
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unsigned int *n, unsigned int *k)
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static void ccu_nk_find_best(unsigned long parent, unsigned long rate,
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unsigned int max_n, unsigned int max_k,
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unsigned int *n, unsigned int *k)
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{
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unsigned long best_rate = 0;
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unsigned int best_k = 0, best_n = 0;
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@ -73,7 +73,7 @@ static void __init sun4i_pll2_setup(struct device_node *node,
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SUN4I_PLL2_PRE_DIV_WIDTH,
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CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
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&sun4i_a10_pll2_lock);
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if (!prediv_clk) {
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if (IS_ERR(prediv_clk)) {
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pr_err("Couldn't register the prediv clock\n");
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goto err_free_array;
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}
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@ -106,7 +106,7 @@ static void __init sun4i_pll2_setup(struct device_node *node,
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&mult->hw, &clk_multiplier_ops,
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&gate->hw, &clk_gate_ops,
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CLK_SET_RATE_PARENT);
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if (!base_clk) {
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if (IS_ERR(base_clk)) {
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pr_err("Couldn't register the base multiplier clock\n");
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goto err_free_multiplier;
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}
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@ -48,7 +48,7 @@ static void __init sun8i_a23_mbus_setup(struct device_node *node)
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return;
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reg = of_io_request_and_map(node, 0, of_node_full_name(node));
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if (!reg) {
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if (IS_ERR(reg)) {
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pr_err("Could not get registers for sun8i-mbus-clk\n");
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goto err_free_parents;
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}
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