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drm/i915/dp_mst: Ensure link parameters are up-to-date for a disabled link

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As explained in the previous patch, the MST link BW reported by branch
devices during topology probing/path resources enumeration depends on
the link parameters programmed to DPCD to be up-to-date. After a sink is
plugged this is not ensured, as those DPCD values start out zeroed. The
target link parameters (for a subsequent modeset) are the maximum that
is supported, so make sure these maximum values are programmed before the
topology probing.

Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240722165503.2084999-14-imre.deak@intel.com
This commit is contained in:
Imre Deak 2024-07-22 19:55:02 +03:00
parent e40fbf6166
commit e44bc451aa
3 changed files with 35 additions and 0 deletions
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3
drivers/gpu/drm/i915/display/intel_dp.c
View File

@ -4254,6 +4254,9 @@ intel_dp_mst_configure(struct intel_dp *intel_dp)
intel_dp->is_mst = intel_dp->mst_detect != DRM_DP_SST;
if (intel_dp->is_mst)
intel_dp_mst_prepare_probe(intel_dp);
drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
/* Avoid stale info on the next detect cycle. */

31
drivers/gpu/drm/i915/display/intel_dp_mst.c
View File

@ -43,6 +43,7 @@
#include "intel_dp_hdcp.h"
#include "intel_dp_mst.h"
#include "intel_dp_tunnel.h"
#include "intel_dp_link_training.h"
#include "intel_dpio_phy.h"
#include "intel_hdcp.h"
#include "intel_hotplug.h"
@ -2031,3 +2032,33 @@ bool intel_dp_mst_crtc_needs_modeset(struct intel_atomic_state *state,
return false;
}
/**
* intel_dp_mst_prepare_probe - Prepare an MST link for topology probing
* @intel_dp: DP port object
*
* Prepare an MST link for topology probing, programming the target
* link parameters to DPCD. This step is a requirement of the enumaration
* of path resources during probing.
*/
void intel_dp_mst_prepare_probe(struct intel_dp *intel_dp)
{
int link_rate = intel_dp_max_link_rate(intel_dp);
int lane_count = intel_dp_max_lane_count(intel_dp);
u8 rate_select;
u8 link_bw;
if (intel_dp->link_trained)
return;
if (intel_mst_probed_link_params_valid(intel_dp, link_rate, lane_count))
return;
intel_dp_compute_rate(intel_dp, link_rate, &link_bw, &rate_select);
intel_dp_link_training_set_mode(intel_dp, link_rate, false);
intel_dp_link_training_set_bw(intel_dp, link_bw, rate_select, lane_count,
drm_dp_enhanced_frame_cap(intel_dp->dpcd));
intel_mst_set_probed_link_params(intel_dp, link_rate, lane_count);
}

1
drivers/gpu/drm/i915/display/intel_dp_mst.h
View File

@ -27,5 +27,6 @@ int intel_dp_mst_atomic_check_link(struct intel_atomic_state *state,
struct intel_link_bw_limits *limits);
bool intel_dp_mst_crtc_needs_modeset(struct intel_atomic_state *state,
struct intel_crtc *crtc);
void intel_dp_mst_prepare_probe(struct intel_dp *intel_dp);
#endif /* __INTEL_DP_MST_H__ */