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clk: ti: add generic support for clock latching

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Certain clocks require latching to be done, so that the actual
settings get updated on the HW that generates the clock signal.
One example of such a clock is the dra76x GMAC DPLL H14 output,
which requires its divider settings to be latched when updated.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
This commit is contained in:
Tero Kristo 2017-07-26 16:47:28 +03:00
parent 4902c2025b
commit e31922eda1
2 changed files with 16 additions and 0 deletions
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14
drivers/clk/ti/clk.c
View File

@ -275,6 +275,20 @@ int ti_clk_get_reg_addr(struct device_node *node, int index,
return 0;
}
void ti_clk_latch(struct clk_omap_reg *reg, s8 shift)
{
u32 latch;
if (shift < 0)
return;
latch = 1 << shift;
ti_clk_ll_ops->clk_rmw(latch, latch, reg);
ti_clk_ll_ops->clk_rmw(0, latch, reg);
ti_clk_ll_ops->clk_readl(reg); /* OCP barrier */
}
/**
* omap2_clk_provider_init - init master clock provider
* @parent: master node

2
drivers/clk/ti/clock.h
View File

@ -194,6 +194,8 @@ struct clk *ti_clk_register(struct device *dev, struct clk_hw *hw,
int ti_clk_add_alias(struct device *dev, struct clk *clk, const char *con);
void ti_clk_add_aliases(void);
void ti_clk_latch(struct clk_omap_reg *reg, s8 shift);
struct clk_hw *ti_clk_build_component_mux(struct ti_clk_mux *setup);
int ti_clk_parse_divider_data(int *div_table, int num_dividers, int max_div,