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gma500: CodingStyle pass
Start the style cleanup Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Alan Cox
Greg Kroah-Hartman
parent
2cf10d23df
commit
e2e88603c8
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@ -25,7 +25,7 @@ struct mrst_vbt {
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u8 size;
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u8 checksum;
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void *mrst_gct;
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} __attribute__ ((packed));
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} __packed;
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struct mrst_timing_info {
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u16 pixel_clock;
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@ -58,7 +58,7 @@ struct mrst_timing_info {
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u8 stereo:1;
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u8 unknown6:1;
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u8 interlaced:1;
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} __attribute__((packed));
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} __packed;
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struct gct_r10_timing_info {
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u16 pixel_clock;
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@ -82,7 +82,7 @@ struct gct_r10_timing_info {
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u16 vsync_pulse_width_hi:2;
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u16 vsync_positive:1;
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u16 rsvd_2:3;
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} __attribute__((packed));
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} __packed;
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struct mrst_panel_descriptor_v1 {
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u32 Panel_Port_Control; /* 1 dword, Register 0x61180 if LVDS */
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@ -111,7 +111,7 @@ struct mrst_panel_descriptor_v1 {
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/* Bit 6, Reserved, 2 bits, 00b */
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/* Bit 8, Minimum Supported Frame Rate, 6 bits, 0 - 63Hz */
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/* Bit 14, Reserved, 2 bits, 00b */
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} __attribute__ ((packed));
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} __packed;
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struct mrst_panel_descriptor_v2 {
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u32 Panel_Port_Control; /* 1 dword, Register 0x61180 if LVDS */
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@ -141,10 +141,10 @@ struct mrst_panel_descriptor_v2 {
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/* Bit 6, Reserved, 2 bits, 00b */
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/* Bit 8, Minimum Supported Frame Rate, 6 bits, 0 - 63Hz */
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/* Bit 14, Reserved, 2 bits, 00b */
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} __attribute__ ((packed));
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} __packed;
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union mrst_panel_rx {
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struct{
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struct {
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u16 NumberOfLanes:2; /*Num of Lanes, 2 bits,0 = 1 lane,*/
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/* 1 = 2 lanes, 2 = 3 lanes, 3 = 4 lanes. */
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u16 MaxLaneFreq:3; /* 0: 100MHz, 1: 200MHz, 2: 300MHz, */
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@ -159,10 +159,10 @@ union mrst_panel_rx {
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u16 Rsvd:5;/*5 bits,00000b */
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} panelrx;
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u16 panel_receiver;
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} __attribute__ ((packed));
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} __packed;
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struct mrst_gct_v1 {
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union{ /*8 bits,Defined as follows: */
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union { /*8 bits,Defined as follows: */
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struct {
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u8 PanelType:4; /*4 bits, Bit field for panels*/
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/* 0 - 3: 0 = LVDS, 1 = MIPI*/
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@ -176,10 +176,10 @@ struct mrst_gct_v1 {
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};
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struct mrst_panel_descriptor_v1 panel[4];/*panel descrs,38 bytes each*/
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union mrst_panel_rx panelrx[4]; /* panel receivers*/
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} __attribute__ ((packed));
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} __packed;
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struct mrst_gct_v2 {
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union{ /*8 bits,Defined as follows: */
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union { /*8 bits,Defined as follows: */
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struct {
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u8 PanelType:4; /*4 bits, Bit field for panels*/
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/* 0 - 3: 0 = LVDS, 1 = MIPI*/
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@ -193,7 +193,7 @@ struct mrst_gct_v2 {
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};
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struct mrst_panel_descriptor_v2 panel[4];/*panel descrs,38 bytes each*/
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union mrst_panel_rx panelrx[4]; /* panel receivers*/
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} __attribute__ ((packed));
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} __packed;
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struct mrst_gct_data {
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u8 bpi; /* boot panel index, number of panel used during boot */
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@ -205,13 +205,13 @@ struct mrst_gct_data {
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u32 PP_Cycle_Delay;
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u16 Panel_Backlight_Inverter_Descriptor;
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u16 Panel_MIPI_Display_Descriptor;
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} __attribute__ ((packed));
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} __packed;
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#define MODE_SETTING_IN_CRTC 0x1
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#define MODE_SETTING_IN_ENCODER 0x2
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#define MODE_SETTING_ON_GOING 0x3
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#define MODE_SETTING_IN_DSR 0x4
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#define MODE_SETTING_ENCODER_DONE 0x8
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#define GCT_R10_HEADER_SIZE 16
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#define MODE_SETTING_IN_CRTC 0x1
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#define MODE_SETTING_IN_ENCODER 0x2
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#define MODE_SETTING_ON_GOING 0x3
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#define MODE_SETTING_IN_DSR 0x4
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#define MODE_SETTING_ENCODER_DONE 0x8
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#define GCT_R10_HEADER_SIZE 16
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#define GCT_R10_DISPLAY_DESC_SIZE 28
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@ -298,10 +298,10 @@ void mrst_lvds_init(struct drm_device *dev,
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/* This ifdef can go once the cpu ident stuff is cleaned up in arch */
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#if defined(CONFIG_X86_MRST)
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if (mrst_identify_cpu())
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i2c_adap = i2c_get_adapter(2);
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else /* Oaktrail uses I2C 1 */
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#endif
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i2c_adap = i2c_get_adapter(1);
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i2c_adap = i2c_get_adapter(2);
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else /* Oaktrail uses I2C 1 */
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#endif
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i2c_adap = i2c_get_adapter(1);
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if (i2c_adap == NULL)
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printk(KERN_ALERT "No ddc adapter available!\n");
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@ -43,11 +43,11 @@
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void psb_spank(struct drm_psb_private *dev_priv)
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{
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PSB_WSGX32(_PSB_CS_RESET_BIF_RESET | _PSB_CS_RESET_DPM_RESET |
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PSB_WSGX32(_PSB_CS_RESET_BIF_RESET | _PSB_CS_RESET_DPM_RESET |
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_PSB_CS_RESET_TA_RESET | _PSB_CS_RESET_USE_RESET |
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_PSB_CS_RESET_ISP_RESET | _PSB_CS_RESET_TSP_RESET |
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_PSB_CS_RESET_TWOD_RESET, PSB_CR_SOFT_RESET);
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(void) PSB_RSGX32(PSB_CR_SOFT_RESET);
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PSB_RSGX32(PSB_CR_SOFT_RESET);
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msleep(1);
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@ -71,7 +71,7 @@ static int psb_2d_wait_available(struct drm_psb_private *dev_priv,
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uint32_t avail = PSB_RSGX32(PSB_CR_2D_SOCIF);
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unsigned long t = jiffies + HZ;
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while(avail < size) {
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while (avail < size) {
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avail = PSB_RSGX32(PSB_CR_2D_SOCIF);
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if (time_after(jiffies, t)) {
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psb_spank(dev_priv);
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@ -85,7 +85,7 @@ static int psb_2d_wait_available(struct drm_psb_private *dev_priv,
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it with console use */
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int psbfb_2d_submit(struct drm_psb_private *dev_priv, uint32_t *cmdbuf,
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unsigned size)
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unsigned size)
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{
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int ret = 0;
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int i;
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@ -99,9 +99,10 @@ int psbfb_2d_submit(struct drm_psb_private *dev_priv, uint32_t *cmdbuf,
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return ret;
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submit_size <<= 2;
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for (i = 0; i < submit_size; i += 4) {
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for (i = 0; i < submit_size; i += 4)
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PSB_WSGX32(*cmdbuf++, PSB_SGX_2D_SLAVE_PORT + i);
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}
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(void)PSB_RSGX32(PSB_SGX_2D_SLAVE_PORT + i - 4);
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}
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return 0;
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@ -209,10 +210,10 @@ static u32 psb_accel_2d_copy_direction(int xdir, int ydir)
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{
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if (xdir < 0)
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return (ydir < 0) ? PSB_2D_COPYORDER_BR2TL :
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PSB_2D_COPYORDER_TR2BL;
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PSB_2D_COPYORDER_TR2BL;
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else
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return (ydir < 0) ? PSB_2D_COPYORDER_BL2TR :
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PSB_2D_COPYORDER_TL2BR;
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PSB_2D_COPYORDER_TL2BR;
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}
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/*
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@ -350,9 +351,9 @@ void psbfb_copyarea(struct fb_info *info,
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if (unlikely(info->state != FBINFO_STATE_RUNNING))
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return;
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/* Avoid the 8 pixel erratum */
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/* Avoid the 8 pixel erratum */
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if (region->width == 8 || region->height == 8 ||
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(info->flags & FBINFO_HWACCEL_DISABLED))
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(info->flags & FBINFO_HWACCEL_DISABLED))
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return cfb_copyarea(info, region);
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psbfb_copyarea_accel(info, region);
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@ -360,7 +361,7 @@ void psbfb_copyarea(struct fb_info *info,
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void psbfb_imageblit(struct fb_info *info, const struct fb_image *image)
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{
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/* For now */
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/* For now */
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cfb_imageblit(info, image);
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}
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@ -118,10 +118,10 @@ struct drm_psb_register_rw_arg {
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u32 OGAMC3;
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u32 OGAMC4;
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u32 OGAMC5;
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u32 IEP_ENABLED;
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u32 IEP_BLE_MINMAX;
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u32 IEP_BSSCC_CONTROL;
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u32 b_wait_vblank;
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u32 IEP_ENABLED;
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u32 IEP_BLE_MINMAX;
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u32 IEP_BSSCC_CONTROL;
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u32 b_wait_vblank;
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} overlay;
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u32 sprite_enable_mask;
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@ -47,7 +47,7 @@ module_param_named(no_fb, drm_psb_no_fb, int, 0600);
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module_param_named(trap_pagefaults, drm_psb_trap_pagefaults, int, 0600);
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static struct pci_device_id pciidlist[] = {
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static DEFINE_PCI_DEVICE_TABLE(pciidlist) = {
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{ 0x8086, 0x8108, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PSB_8108 },
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{ 0x8086, 0x8109, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PSB_8109 },
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{ 0x8086, 0x4100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MRST_4100},
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@ -185,8 +185,7 @@ void mrst_get_fuse_settings(struct drm_device *dev)
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if (dev_priv->iLVDS_enable) {
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dev_priv->is_lvds_on = true;
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dev_priv->is_mipi_on = false;
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}
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else {
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} else {
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dev_priv->is_mipi_on = true;
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dev_priv->is_lvds_on = false;
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}
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@ -196,7 +195,7 @@ void mrst_get_fuse_settings(struct drm_device *dev)
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pci_write_config_dword(pci_root, 0xD0, FB_REG09);
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pci_read_config_dword(pci_root, 0xD4, &fuse_value);
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DRM_INFO("SKU values is 0x%x. \n", fuse_value);
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DRM_INFO("SKU values is 0x%x.\n", fuse_value);
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fuse_value_tmp = (fuse_value & FB_SKU_MASK) >> FB_SKU_SHIFT;
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dev_priv->fuse_reg_value = fuse_value;
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@ -220,7 +219,7 @@ void mrst_get_fuse_settings(struct drm_device *dev)
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pci_dev_put(pci_root);
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}
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void mid_get_pci_revID (struct drm_psb_private *dev_priv)
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void mid_get_pci_revID(struct drm_psb_private *dev_priv)
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{
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uint32_t platform_rev_id = 0;
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struct pci_dev *pci_gfx_root = pci_get_bus_and_slot(0, PCI_DEVFN(2, 0));
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@ -230,7 +229,7 @@ void mid_get_pci_revID (struct drm_psb_private *dev_priv)
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dev_priv->platform_rev_id = (uint8_t) platform_rev_id;
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pci_dev_put(pci_gfx_root);
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dev_info(dev_priv->dev->dev, "platform_rev_id is %x\n",
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dev_priv->platform_rev_id);
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dev_priv->platform_rev_id);
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}
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void mrst_get_vbt_data(struct drm_psb_private *dev_priv)
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@ -285,7 +284,7 @@ void mrst_get_vbt_data(struct drm_psb_private *dev_priv)
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dev_priv->gct_data.Panel_Port_Control =
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((struct mrst_gct_v1 *)pGCT)->panel[bpi].Panel_Port_Control;
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dev_priv->gct_data.Panel_MIPI_Display_Descriptor =
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((struct mrst_gct_v1 *)pGCT)->panel[bpi].Panel_MIPI_Display_Descriptor;
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((struct mrst_gct_v1 *)pGCT)->panel[bpi].Panel_MIPI_Display_Descriptor;
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break;
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case 1:
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vbt->mrst_gct = NULL;
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@ -303,7 +302,7 @@ void mrst_get_vbt_data(struct drm_psb_private *dev_priv)
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dev_priv->gct_data.Panel_Port_Control =
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((struct mrst_gct_v2 *)pGCT)->panel[bpi].Panel_Port_Control;
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dev_priv->gct_data.Panel_MIPI_Display_Descriptor =
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((struct mrst_gct_v2 *)pGCT)->panel[bpi].Panel_MIPI_Display_Descriptor;
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((struct mrst_gct_v2 *)pGCT)->panel[bpi].Panel_MIPI_Display_Descriptor;
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break;
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case 0x10:
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/*header definition changed from rev 01 (v2) to rev 10h. */
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@ -449,13 +448,12 @@ static int psb_do_init(struct drm_device *dev)
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PSB_WSGX32(0x00000000, PSB_CR_BIF_BANK0);
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PSB_WSGX32(0x00000000, PSB_CR_BIF_BANK1);
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PSB_RSGX32(PSB_CR_BIF_BANK1);
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PSB_WSGX32(PSB_RSGX32(PSB_CR_BIF_CTRL) | _PSB_MMU_ER_MASK,
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PSB_WSGX32(PSB_RSGX32(PSB_CR_BIF_CTRL) | _PSB_MMU_ER_MASK,
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PSB_CR_BIF_CTRL);
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psb_spank(dev_priv);
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/* mmu_gatt ?? */
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PSB_WSGX32(pg->gatt_start, PSB_CR_BIF_TWOD_REQ_BASE);
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PSB_WSGX32(pg->gatt_start, PSB_CR_BIF_TWOD_REQ_BASE);
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return 0;
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out_err:
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psb_do_takedown(dev);
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@ -1335,7 +1333,6 @@ static long psb_unlocked_ioctl(struct file *filp, unsigned int cmd,
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dev_priv->rpm_enabled = 1;
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}
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return drm_ioctl(filp, cmd, arg);
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/* FIXME: do we need to wrap the other side of this */
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}
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@ -1367,7 +1364,7 @@ static struct vm_operations_struct psb_gem_vm_ops = {
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static struct drm_driver driver = {
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.driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | \
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DRIVER_IRQ_VBL | DRIVER_MODESET| DRIVER_GEM ,
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DRIVER_IRQ_VBL | DRIVER_MODESET | DRIVER_GEM ,
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.load = psb_driver_load,
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.unload = psb_driver_unload,
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@ -1428,7 +1425,7 @@ static int psb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
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{
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/* MLD Added this from Inaky's patch */
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if (pci_enable_msi(pdev))
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dev_warn(&pdev->dev, "Enable MSI failed!\n");
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dev_warn(&pdev->dev, "Enable MSI failed!\n");
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return drm_get_pci_dev(pdev, ent, &driver);
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}
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@ -25,6 +25,7 @@
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#include <drm/drmP.h>
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#include "drm_global.h"
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#include "gem_glue.h"
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#include "psb_drm.h"
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#include "psb_reg.h"
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#include "psb_intel_drv.h"
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@ -132,8 +133,12 @@ enum {
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#define _LNC_IRQ_TOPAZ_FLAG (1<<20)
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/* This flag includes all the display IRQ bits excepts the vblank irqs. */
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#define _MDFLD_DISP_ALL_IRQ_FLAG (_MDFLD_PIPEC_EVENT_FLAG | _MDFLD_PIPEB_EVENT_FLAG | \
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_PSB_PIPEA_EVENT_FLAG | _PSB_VSYNC_PIPEA_FLAG | _MDFLD_MIPIA_FLAG | _MDFLD_MIPIC_FLAG)
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#define _MDFLD_DISP_ALL_IRQ_FLAG (_MDFLD_PIPEC_EVENT_FLAG | \
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_MDFLD_PIPEB_EVENT_FLAG | \
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_PSB_PIPEA_EVENT_FLAG | \
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_PSB_VSYNC_PIPEA_FLAG | \
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_MDFLD_MIPIA_FLAG | \
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_MDFLD_MIPIC_FLAG)
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#define PSB_INT_IDENTITY_R 0x20A4
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#define PSB_INT_MASK_R 0x20A8
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#define PSB_INT_ENABLE_R 0x20A0
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@ -273,7 +278,7 @@ struct drm_psb_private {
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/*
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* Power
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*/
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*/
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bool suspended;
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bool display_power;
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@ -480,7 +485,7 @@ struct drm_psb_private {
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uint32_t blc_adj1;
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uint32_t blc_adj2;
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void * fbdev;
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void *fbdev;
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};
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@ -550,7 +555,7 @@ extern void psb_irq_turn_on_dpst(struct drm_device *dev);
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extern void psb_irq_turn_off_dpst(struct drm_device *dev);
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extern void psb_irq_uninstall_islands(struct drm_device *dev, int hw_islands);
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extern int psb_vblank_wait2(struct drm_device *dev,unsigned int *sequence);
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extern int psb_vblank_wait2(struct drm_device *dev, unsigned int *sequence);
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extern int psb_vblank_wait(struct drm_device *dev, unsigned int *sequence);
|
||||
extern int psb_enable_vblank(struct drm_device *dev, int crtc);
|
||||
extern void psb_disable_vblank(struct drm_device *dev, int crtc);
|
||||
|
|
@ -593,7 +598,7 @@ extern int psbfb_sync(struct fb_info *info);
|
|||
extern void psb_spank(struct drm_psb_private *dev_priv);
|
||||
|
||||
extern int psbfb_2d_submit(struct drm_psb_private *dev_priv, uint32_t *cmdbuf,
|
||||
unsigned size);
|
||||
unsigned size);
|
||||
|
||||
/*
|
||||
* psb_reset.c
|
||||
|
|
@ -606,14 +611,14 @@ extern void psb_print_pagefault(struct drm_psb_private *dev_priv);
|
|||
/* modesetting */
|
||||
extern void psb_modeset_init(struct drm_device *dev);
|
||||
extern void psb_modeset_cleanup(struct drm_device *dev);
|
||||
extern int psb_fbdev_init(struct drm_device * dev);
|
||||
extern int psb_fbdev_init(struct drm_device *dev);
|
||||
|
||||
/* psb_bl.c */
|
||||
int psb_backlight_init(struct drm_device *dev);
|
||||
void psb_backlight_exit(void);
|
||||
int psb_set_brightness(struct backlight_device *bd);
|
||||
int psb_get_brightness(struct backlight_device *bd);
|
||||
struct backlight_device * psb_get_backlight_device(void);
|
||||
struct backlight_device *psb_get_backlight_device(void);
|
||||
|
||||
/* mrst_crtc.c */
|
||||
extern const struct drm_crtc_helper_funcs mrst_helper_funcs;
|
||||
|
|
@ -662,7 +667,6 @@ extern int psb_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
|
|||
extern int drm_psb_no_fb;
|
||||
extern int drm_idle_check_interval;
|
||||
|
||||
|
||||
/*
|
||||
* Utilities
|
||||
*/
|
||||
|
|
@ -671,36 +675,36 @@ static inline u32 MRST_MSG_READ32(uint port, uint offset)
|
|||
{
|
||||
int mcr = (0xD0<<24) | (port << 16) | (offset << 8);
|
||||
uint32_t ret_val = 0;
|
||||
struct pci_dev *pci_root = pci_get_bus_and_slot (0, 0);
|
||||
pci_write_config_dword (pci_root, 0xD0, mcr);
|
||||
pci_read_config_dword (pci_root, 0xD4, &ret_val);
|
||||
struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
|
||||
pci_write_config_dword(pci_root, 0xD0, mcr);
|
||||
pci_read_config_dword(pci_root, 0xD4, &ret_val);
|
||||
pci_dev_put(pci_root);
|
||||
return ret_val;
|
||||
}
|
||||
static inline void MRST_MSG_WRITE32(uint port, uint offset, u32 value)
|
||||
{
|
||||
int mcr = (0xE0<<24) | (port << 16) | (offset << 8) | 0xF0;
|
||||
struct pci_dev *pci_root = pci_get_bus_and_slot (0, 0);
|
||||
pci_write_config_dword (pci_root, 0xD4, value);
|
||||
pci_write_config_dword (pci_root, 0xD0, mcr);
|
||||
struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
|
||||
pci_write_config_dword(pci_root, 0xD4, value);
|
||||
pci_write_config_dword(pci_root, 0xD0, mcr);
|
||||
pci_dev_put(pci_root);
|
||||
}
|
||||
static inline u32 MDFLD_MSG_READ32(uint port, uint offset)
|
||||
{
|
||||
int mcr = (0x10<<24) | (port << 16) | (offset << 8);
|
||||
uint32_t ret_val = 0;
|
||||
struct pci_dev *pci_root = pci_get_bus_and_slot (0, 0);
|
||||
pci_write_config_dword (pci_root, 0xD0, mcr);
|
||||
pci_read_config_dword (pci_root, 0xD4, &ret_val);
|
||||
struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
|
||||
pci_write_config_dword(pci_root, 0xD0, mcr);
|
||||
pci_read_config_dword(pci_root, 0xD4, &ret_val);
|
||||
pci_dev_put(pci_root);
|
||||
return ret_val;
|
||||
}
|
||||
static inline void MDFLD_MSG_WRITE32(uint port, uint offset, u32 value)
|
||||
{
|
||||
int mcr = (0x11<<24) | (port << 16) | (offset << 8) | 0xF0;
|
||||
struct pci_dev *pci_root = pci_get_bus_and_slot (0, 0);
|
||||
pci_write_config_dword (pci_root, 0xD4, value);
|
||||
pci_write_config_dword (pci_root, 0xD0, mcr);
|
||||
struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
|
||||
pci_write_config_dword(pci_root, 0xD4, value);
|
||||
pci_write_config_dword(pci_root, 0xD0, mcr);
|
||||
pci_dev_put(pci_root);
|
||||
}
|
||||
|
||||
|
|
@ -744,14 +748,15 @@ static inline void REGISTER_WRITE8(struct drm_device *dev,
|
|||
|
||||
/* #define TRAP_SGX_PM_FAULT 1 */
|
||||
#ifdef TRAP_SGX_PM_FAULT
|
||||
#define PSB_RSGX32(_offs) \
|
||||
({ \
|
||||
if (inl(dev_priv->apm_base + PSB_APM_STS) & 0x3) { \
|
||||
printk(KERN_ERR "access sgx when it's off!! (READ) %s, %d\n", \
|
||||
__FILE__, __LINE__); \
|
||||
mdelay(1000); \
|
||||
} \
|
||||
ioread32(dev_priv->sgx_reg + (_offs)); \
|
||||
#define PSB_RSGX32(_offs) \
|
||||
({ \
|
||||
if (inl(dev_priv->apm_base + PSB_APM_STS) & 0x3) { \
|
||||
printk(KERN_ERR \
|
||||
"access sgx when it's off!! (READ) %s, %d\n", \
|
||||
__FILE__, __LINE__); \
|
||||
melay(1000); \
|
||||
} \
|
||||
ioread32(dev_priv->sgx_reg + (_offs)); \
|
||||
})
|
||||
#else
|
||||
#define PSB_RSGX32(_offs) ioread32(dev_priv->sgx_reg + (_offs))
|
||||
|
|
|
|||
|
|
@ -244,9 +244,11 @@ static int psbfb_mmap(struct fb_info *info, struct vm_area_struct *vma)
|
|||
|
||||
fb_screen_base = (char *)info->screen_base;
|
||||
|
||||
/* If this is a GEM object then info->screen_base is the virtual
|
||||
kernel remapping of the object. FIXME: Review if this is
|
||||
suitable for our mmap work */
|
||||
/*
|
||||
* If this is a GEM object then info->screen_base is the virtual
|
||||
* kernel remapping of the object. FIXME: Review if this is
|
||||
* suitable for our mmap work
|
||||
*/
|
||||
vma->vm_ops = &psbfb_vm_ops;
|
||||
vma->vm_private_data = (void *)psbfb;
|
||||
vma->vm_flags |= VM_RESERVED | VM_IO |
|
||||
|
|
@ -254,7 +256,8 @@ static int psbfb_mmap(struct fb_info *info, struct vm_area_struct *vma)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int psbfb_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg)
|
||||
static int psbfb_ioctl(struct fb_info *info, unsigned int cmd,
|
||||
unsigned long arg)
|
||||
{
|
||||
struct psb_fbdev *fbdev = info->par;
|
||||
struct psb_framebuffer *psbfb = &fbdev->pfb;
|
||||
|
|
@ -305,33 +308,33 @@ static struct fb_ops psbfb_ops = {
|
|||
* 0 on success or an error code if we fail.
|
||||
*/
|
||||
static int psb_framebuffer_init(struct drm_device *dev,
|
||||
struct psb_framebuffer *fb,
|
||||
struct drm_mode_fb_cmd *mode_cmd,
|
||||
struct gtt_range *gt)
|
||||
struct psb_framebuffer *fb,
|
||||
struct drm_mode_fb_cmd *mode_cmd,
|
||||
struct gtt_range *gt)
|
||||
{
|
||||
int ret;
|
||||
int ret;
|
||||
|
||||
if (mode_cmd->pitch & 63)
|
||||
return -EINVAL;
|
||||
switch (mode_cmd->bpp) {
|
||||
case 8:
|
||||
case 16:
|
||||
case 24:
|
||||
case 32:
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
ret = drm_framebuffer_init(dev, &fb->base, &psb_fb_funcs);
|
||||
if (ret) {
|
||||
dev_err(dev->dev, "framebuffer init failed: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
drm_helper_mode_fill_fb_struct(&fb->base, mode_cmd);
|
||||
fb->gtt = gt;
|
||||
return 0;
|
||||
if (mode_cmd->pitch & 63)
|
||||
return -EINVAL;
|
||||
switch (mode_cmd->bpp) {
|
||||
case 8:
|
||||
case 16:
|
||||
case 24:
|
||||
case 32:
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
ret = drm_framebuffer_init(dev, &fb->base, &psb_fb_funcs);
|
||||
if (ret) {
|
||||
dev_err(dev->dev, "framebuffer init failed: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
drm_helper_mode_fill_fb_struct(&fb->base, mode_cmd);
|
||||
fb->gtt = gt;
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* psb_framebuffer_create - create a framebuffer backed by gt
|
||||
* @dev: our DRM device
|
||||
|
|
@ -357,10 +360,10 @@ static struct drm_framebuffer *psb_framebuffer_create
|
|||
|
||||
ret = psb_framebuffer_init(dev, fb, mode_cmd, gt);
|
||||
if (ret) {
|
||||
kfree(fb);
|
||||
return ERR_PTR(ret);
|
||||
}
|
||||
return &fb->base;
|
||||
kfree(fb);
|
||||
return ERR_PTR(ret);
|
||||
}
|
||||
return &fb->base;
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -373,7 +376,7 @@ static struct drm_framebuffer *psb_framebuffer_create
|
|||
* stolen memory or the system has no stolen memory we allocate a range
|
||||
* and back it with a GEM object.
|
||||
*
|
||||
* In this case the GEM object has no handle.
|
||||
* In this case the GEM object has no handle.
|
||||
*
|
||||
* FIXME: console speed up - allocate twice the space if room and use
|
||||
* hardware scrolling for acceleration.
|
||||
|
|
@ -384,10 +387,11 @@ static struct gtt_range *psbfb_alloc(struct drm_device *dev, int aligned_size)
|
|||
/* Begin by trying to use stolen memory backing */
|
||||
backing = psb_gtt_alloc_range(dev, aligned_size, "fb", 1);
|
||||
if (backing) {
|
||||
if (drm_gem_private_object_init(dev, &backing->gem, aligned_size) == 0)
|
||||
return backing;
|
||||
psb_gtt_free_range(dev, backing);
|
||||
}
|
||||
if (drm_gem_private_object_init(dev,
|
||||
&backing->gem, aligned_size) == 0)
|
||||
return backing;
|
||||
psb_gtt_free_range(dev, backing);
|
||||
}
|
||||
/* Next try using GEM host memory */
|
||||
backing = psb_gtt_alloc_range(dev, aligned_size, "fb(gem)", 0);
|
||||
if (backing == NULL)
|
||||
|
|
@ -400,7 +404,7 @@ static struct gtt_range *psbfb_alloc(struct drm_device *dev, int aligned_size)
|
|||
}
|
||||
return backing;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* psbfb_create - create a framebuffer
|
||||
* @fbdev: the framebuffer device
|
||||
|
|
@ -428,7 +432,7 @@ static int psbfb_create(struct psb_fbdev *fbdev,
|
|||
|
||||
/* No 24bit packed */
|
||||
if (mode_cmd.bpp == 24)
|
||||
mode_cmd.bpp = 32;
|
||||
mode_cmd.bpp = 32;
|
||||
|
||||
/* HW requires pitch to be 64 byte aligned */
|
||||
mode_cmd.pitch = ALIGN(mode_cmd.width * ((mode_cmd.bpp + 7) / 8), 64);
|
||||
|
|
@ -440,7 +444,7 @@ static int psbfb_create(struct psb_fbdev *fbdev,
|
|||
/* Allocate the framebuffer in the GTT with stolen page backing */
|
||||
backing = psbfb_alloc(dev, size);
|
||||
if (backing == NULL)
|
||||
return -ENOMEM;
|
||||
return -ENOMEM;
|
||||
|
||||
mutex_lock(&dev->struct_mutex);
|
||||
|
||||
|
|
@ -455,7 +459,7 @@ static int psbfb_create(struct psb_fbdev *fbdev,
|
|||
if (ret)
|
||||
goto out_unref;
|
||||
|
||||
fb = &psbfb->base;
|
||||
fb = &psbfb->base;
|
||||
psbfb->fbdev = info;
|
||||
|
||||
fbdev->psb_fb_helper.fb = fb;
|
||||
|
|
@ -523,13 +527,13 @@ static int psbfb_create(struct psb_fbdev *fbdev,
|
|||
mutex_unlock(&dev->struct_mutex);
|
||||
return 0;
|
||||
out_unref:
|
||||
if (backing->stolen)
|
||||
psb_gtt_free_range(dev, backing);
|
||||
else {
|
||||
if (psbfb->vm_map)
|
||||
vm_unmap_ram(info->screen_base, backing->npage);
|
||||
drm_gem_object_unreference(&backing->gem);
|
||||
}
|
||||
if (backing->stolen)
|
||||
psb_gtt_free_range(dev, backing);
|
||||
else {
|
||||
if (psbfb->vm_map)
|
||||
vm_unmap_ram(info->screen_base, backing->npage);
|
||||
drm_gem_object_unreference(&backing->gem);
|
||||
}
|
||||
out_err1:
|
||||
mutex_unlock(&dev->struct_mutex);
|
||||
psb_gtt_free_range(dev, backing);
|
||||
|
|
@ -548,17 +552,19 @@ static struct drm_framebuffer *psb_user_framebuffer_create
|
|||
(struct drm_device *dev, struct drm_file *filp,
|
||||
struct drm_mode_fb_cmd *cmd)
|
||||
{
|
||||
struct gtt_range *r;
|
||||
struct drm_gem_object *obj;
|
||||
struct gtt_range *r;
|
||||
struct drm_gem_object *obj;
|
||||
|
||||
/* Find the GEM object and thus the gtt range object that is
|
||||
to back this space */
|
||||
/*
|
||||
* Find the GEM object and thus the gtt range object that is
|
||||
* to back this space
|
||||
*/
|
||||
obj = drm_gem_object_lookup(dev, filp, cmd->handle);
|
||||
if (obj == NULL)
|
||||
return ERR_PTR(-ENOENT);
|
||||
return ERR_PTR(-ENOENT);
|
||||
|
||||
/* Let the core code do all the work */
|
||||
r = container_of(obj, struct gtt_range, gem);
|
||||
/* Let the core code do all the work */
|
||||
r = container_of(obj, struct gtt_range, gem);
|
||||
return psb_framebuffer_create(dev, cmd, r);
|
||||
}
|
||||
|
||||
|
|
@ -610,12 +616,12 @@ int psb_fbdev_destroy(struct drm_device *dev, struct psb_fbdev *fbdev)
|
|||
}
|
||||
unregister_framebuffer(info);
|
||||
if (info->cmap.len)
|
||||
fb_dealloc_cmap(&info->cmap);
|
||||
fb_dealloc_cmap(&info->cmap);
|
||||
framebuffer_release(info);
|
||||
}
|
||||
drm_fb_helper_fini(&fbdev->psb_fb_helper);
|
||||
drm_framebuffer_cleanup(&psbfb->base);
|
||||
|
||||
|
||||
if (psbfb->gtt) {
|
||||
/* FIXME: this is a bit more inside knowledge than I'd like
|
||||
but I don't see how to make a fake GEM object of the
|
||||
|
|
@ -624,7 +630,7 @@ int psb_fbdev_destroy(struct drm_device *dev, struct psb_fbdev *fbdev)
|
|||
psb_gtt_free_range(dev, psbfb->gtt);
|
||||
else
|
||||
drm_gem_object_unreference(&psbfb->gtt->gem);
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -686,9 +692,9 @@ static int psb_user_framebuffer_create_handle(struct drm_framebuffer *fb,
|
|||
struct drm_file *file_priv,
|
||||
unsigned int *handle)
|
||||
{
|
||||
struct psb_framebuffer *psbfb = to_psb_fb(fb);
|
||||
struct gtt_range *r = psbfb->gtt;
|
||||
return drm_gem_handle_create(file_priv, &r->gem, handle);
|
||||
struct psb_framebuffer *psbfb = to_psb_fb(fb);
|
||||
struct gtt_range *r = psbfb->gtt;
|
||||
return drm_gem_handle_create(file_priv, &r->gem, handle);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -717,16 +723,17 @@ static void psb_user_framebuffer_destroy(struct drm_framebuffer *fb)
|
|||
reset = 1;
|
||||
|
||||
if (reset)
|
||||
/*
|
||||
* Now force a sane response before we permit the DRM crc layer to
|
||||
* do stupid things like blank the display. Instead we reset this
|
||||
* framebuffer as if the user had forced a reset. We must do this
|
||||
* before the cleanup so that the DRM layer doesn't get a chance
|
||||
* to stick its oar in where it isn't wanted.
|
||||
/*
|
||||
* Now force a sane response before we permit the DRM CRTC
|
||||
* layer to do stupid things like blank the display. Instead
|
||||
* we reset this framebuffer as if the user had forced a reset.
|
||||
* We must do this before the cleanup so that the DRM layer
|
||||
* doesn't get a chance to stick its oar in where it isn't
|
||||
* wanted.
|
||||
*/
|
||||
drm_fb_helper_restore_fbdev_mode(&fbdev->psb_fb_helper);
|
||||
|
||||
/* Let DRM do its clean up */
|
||||
/* Let DRM do its clean up */
|
||||
drm_framebuffer_cleanup(fb);
|
||||
/* We are no longer using the resource in GEM */
|
||||
drm_gem_object_unreference_unlocked(&r->gem);
|
||||
|
|
|
|||
|
|
@ -82,12 +82,13 @@ static int psb_gem_create_mmap_offset(struct drm_gem_object *obj)
|
|||
map = list->map;
|
||||
map->type = _DRM_GEM;
|
||||
map->size = obj->size;
|
||||
map->handle =obj;
|
||||
map->handle = obj;
|
||||
|
||||
list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
|
||||
obj->size / PAGE_SIZE, 0, 0);
|
||||
if (!list->file_offset_node) {
|
||||
dev_err(dev->dev, "failed to allocate offset for bo %d\n", obj->name);
|
||||
dev_err(dev->dev, "failed to allocate offset for bo %d\n",
|
||||
obj->name);
|
||||
ret = -ENOSPC;
|
||||
goto free_it;
|
||||
}
|
||||
|
|
@ -130,7 +131,7 @@ int psb_gem_dumb_map_gtt(struct drm_file *file, struct drm_device *dev,
|
|||
|
||||
if (!(dev->driver->driver_features & DRIVER_GEM))
|
||||
return -ENODEV;
|
||||
|
||||
|
||||
mutex_lock(&dev->struct_mutex);
|
||||
|
||||
/* GEM does all our handle to object mapping */
|
||||
|
|
@ -140,7 +141,7 @@ int psb_gem_dumb_map_gtt(struct drm_file *file, struct drm_device *dev,
|
|||
goto unlock;
|
||||
}
|
||||
/* What validation is needed here ? */
|
||||
|
||||
|
||||
/* Make it mmapable */
|
||||
if (!obj->map_list.map) {
|
||||
ret = psb_gem_create_mmap_offset(obj);
|
||||
|
|
@ -176,7 +177,7 @@ static int psb_gem_create(struct drm_file *file,
|
|||
|
||||
size = roundup(size, PAGE_SIZE);
|
||||
|
||||
/* Allocate our object - for now a direct gtt range which is not
|
||||
/* Allocate our object - for now a direct gtt range which is not
|
||||
stolen memory backed */
|
||||
r = psb_gtt_alloc_range(dev, size, "gem", 0);
|
||||
if (r == NULL) {
|
||||
|
|
@ -285,9 +286,9 @@ int psb_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
|
|||
if (r->mmapping == 0) {
|
||||
ret = psb_gtt_pin(r);
|
||||
if (ret < 0) {
|
||||
dev_err(dev->dev, "gma500: pin failed: %d\n", ret);
|
||||
goto fail;
|
||||
}
|
||||
dev_err(dev->dev, "gma500: pin failed: %d\n", ret);
|
||||
goto fail;
|
||||
}
|
||||
r->mmapping = 1;
|
||||
}
|
||||
|
||||
|
|
@ -304,7 +305,7 @@ int psb_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
|
|||
ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
|
||||
|
||||
fail:
|
||||
mutex_unlock(&dev->struct_mutex);
|
||||
mutex_unlock(&dev->struct_mutex);
|
||||
switch (ret) {
|
||||
case 0:
|
||||
case -ERESTARTSYS:
|
||||
|
|
|
|||
|
|
@ -52,7 +52,7 @@ static inline uint32_t psb_gtt_mask_pte(uint32_t pfn, int type)
|
|||
* psb_gtt_entry - find the GTT entries for a gtt_range
|
||||
* @dev: our DRM device
|
||||
* @r: our GTT range
|
||||
*
|
||||
*
|
||||
* Given a gtt_range object return the GTT offset of the page table
|
||||
* entries for this gtt_range
|
||||
*/
|
||||
|
|
@ -102,7 +102,6 @@ static int psb_gtt_insert(struct drm_device *dev, struct gtt_range *r)
|
|||
}
|
||||
/* Make sure all the entries are set before we return */
|
||||
ioread32(gtt_slot - 1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -257,7 +256,7 @@ void psb_gtt_unpin(struct gtt_range *gt)
|
|||
}
|
||||
mutex_unlock(&dev_priv->gtt_mutex);
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* GTT resource allocator - allocate and manage GTT address space
|
||||
*/
|
||||
|
|
@ -289,11 +288,11 @@ struct gtt_range *psb_gtt_alloc_range(struct drm_device *dev, int len,
|
|||
/* The start of the GTT is the stolen pages */
|
||||
start = r->start;
|
||||
end = r->start + dev_priv->pg->stolen_size - 1;
|
||||
} else {
|
||||
/* The rest we will use for GEM backed objects */
|
||||
start = r->start + dev_priv->pg->stolen_size;
|
||||
end = r->end;
|
||||
}
|
||||
} else {
|
||||
/* The rest we will use for GEM backed objects */
|
||||
start = r->start + dev_priv->pg->stolen_size;
|
||||
end = r->end;
|
||||
}
|
||||
|
||||
gt = kzalloc(sizeof(struct gtt_range), GFP_KERNEL);
|
||||
if (gt == NULL)
|
||||
|
|
@ -318,8 +317,8 @@ struct gtt_range *psb_gtt_alloc_range(struct drm_device *dev, int len,
|
|||
* @dev: our DRM device
|
||||
* @gt: a mapping created with psb_gtt_alloc_range
|
||||
*
|
||||
* Release a resource that was allocated with psb_gtt_alloc_range. If the object
|
||||
* has been pinned by mmap users we clean this up here currently.
|
||||
* Release a resource that was allocated with psb_gtt_alloc_range. If the
|
||||
* object has been pinned by mmap users we clean this up here currently.
|
||||
*/
|
||||
void psb_gtt_free_range(struct drm_device *dev, struct gtt_range *gt)
|
||||
{
|
||||
|
|
@ -386,7 +385,7 @@ int psb_gtt_init(struct drm_device *dev, int resume)
|
|||
if (pg == NULL)
|
||||
return -ENOMEM;
|
||||
|
||||
/* Enable the GTT */
|
||||
/* Enable the GTT */
|
||||
pci_read_config_word(dev->pdev, PSB_GMCH_CTRL, &dev_priv->gmch_ctrl);
|
||||
pci_write_config_word(dev->pdev, PSB_GMCH_CTRL,
|
||||
dev_priv->gmch_ctrl | _PSB_GMCH_ENABLED);
|
||||
|
|
@ -402,18 +401,21 @@ int psb_gtt_init(struct drm_device *dev, int resume)
|
|||
pg->gtt_phys_start = dev_priv->pge_ctl & PAGE_MASK;
|
||||
|
||||
pg->gatt_start = pci_resource_start(dev->pdev, PSB_GATT_RESOURCE);
|
||||
/*
|
||||
/*
|
||||
* FIXME: video mmu has hw bug to access 0x0D0000000,
|
||||
* then make gatt start at 0x0e000,0000
|
||||
*/
|
||||
pg->mmu_gatt_start = 0xE0000000;
|
||||
|
||||
pg->gtt_start = pci_resource_start(dev->pdev, PSB_GTT_RESOURCE);
|
||||
gtt_pages = pci_resource_len(dev->pdev, PSB_GTT_RESOURCE) >> PAGE_SHIFT;
|
||||
pg->gatt_pages = pci_resource_len(dev->pdev, PSB_GATT_RESOURCE) >> PAGE_SHIFT;
|
||||
gtt_pages = pci_resource_len(dev->pdev, PSB_GTT_RESOURCE)
|
||||
>> PAGE_SHIFT;
|
||||
pg->gatt_pages = pci_resource_len(dev->pdev, PSB_GATT_RESOURCE)
|
||||
>> PAGE_SHIFT;
|
||||
|
||||
pci_read_config_dword(dev->pdev, PSB_BSM, &dev_priv->stolen_base);
|
||||
vram_stolen_size = pg->gtt_phys_start - dev_priv->stolen_base - PAGE_SIZE;
|
||||
vram_stolen_size = pg->gtt_phys_start - dev_priv->stolen_base
|
||||
- PAGE_SIZE;
|
||||
|
||||
stolen_size = vram_stolen_size;
|
||||
|
||||
|
|
@ -439,7 +441,8 @@ int psb_gtt_init(struct drm_device *dev, int resume)
|
|||
/*
|
||||
* Map the GTT and the stolen memory area
|
||||
*/
|
||||
dev_priv->gtt_map = ioremap_nocache(pg->gtt_phys_start, gtt_pages << PAGE_SHIFT);
|
||||
dev_priv->gtt_map = ioremap_nocache(pg->gtt_phys_start,
|
||||
gtt_pages << PAGE_SHIFT);
|
||||
if (!dev_priv->gtt_map) {
|
||||
dev_err(dev->dev, "Failure to map gtt.\n");
|
||||
ret = -ENOMEM;
|
||||
|
|
|
|||
|
|
@ -388,7 +388,7 @@ int psb_intel_pipe_set_base(struct drm_crtc *crtc,
|
|||
dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
|
||||
break;
|
||||
default:
|
||||
dev_err(dev->dev, "Unknown color depth\n");
|
||||
dev_err(dev->dev, "Unknown color depth\n");
|
||||
ret = -EINVAL;
|
||||
psb_gtt_unpin(psbfb->gtt);
|
||||
goto psb_intel_pipe_set_base_exit;
|
||||
|
|
@ -611,9 +611,9 @@ static int psb_intel_crtc_mode_set(struct drm_crtc *crtc,
|
|||
|
||||
/* No scan out no play */
|
||||
if (crtc->fb == NULL) {
|
||||
crtc_funcs->mode_set_base(crtc, x, y, old_fb);
|
||||
return 0;
|
||||
}
|
||||
crtc_funcs->mode_set_base(crtc, x, y, old_fb);
|
||||
return 0;
|
||||
}
|
||||
|
||||
list_for_each_entry(connector, &mode_config->connector_list, head) {
|
||||
struct psb_intel_output *psb_intel_output =
|
||||
|
|
@ -728,8 +728,8 @@ static int psb_intel_crtc_mode_set(struct drm_crtc *crtc,
|
|||
u32 lvds = REG_READ(LVDS);
|
||||
|
||||
lvds &= ~LVDS_PIPEB_SELECT;
|
||||
if (pipe == 1)
|
||||
lvds |= LVDS_PIPEB_SELECT;
|
||||
if (pipe == 1)
|
||||
lvds |= LVDS_PIPEB_SELECT;
|
||||
|
||||
lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
|
||||
/* Set the B0-B3 data pairs corresponding to
|
||||
|
|
|
|||
|
|
@ -33,19 +33,19 @@ struct opregion_header {
|
|||
u8 driver_ver[16];
|
||||
u32 mboxes;
|
||||
u8 reserved[164];
|
||||
} __attribute__((packed));
|
||||
} __packed;
|
||||
|
||||
struct opregion_apci {
|
||||
/*FIXME: add it later*/
|
||||
} __attribute__((packed));
|
||||
} __packed;
|
||||
|
||||
struct opregion_swsci {
|
||||
/*FIXME: add it later*/
|
||||
} __attribute__((packed));
|
||||
} __packed;
|
||||
|
||||
struct opregion_acpi {
|
||||
/*FIXME: add it later*/
|
||||
} __attribute__((packed));
|
||||
} __packed;
|
||||
|
||||
int psb_intel_opregion_init(struct drm_device *dev)
|
||||
{
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -211,7 +211,8 @@ static void psb_intel_sdvo_write_cmd(struct psb_intel_output *psb_intel_output,
|
|||
sizeof(sdvo_cmd_names) / sizeof(sdvo_cmd_names[0]);
|
||||
i++) {
|
||||
if (cmd == sdvo_cmd_names[i].cmd) {
|
||||
printk(KERN_CONT "(%s)", sdvo_cmd_names[i].name);
|
||||
printk(KERN_CONT
|
||||
"(%s)", sdvo_cmd_names[i].name);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -51,7 +51,7 @@ struct psb_intel_sdvo_caps {
|
|||
unsigned int stall_support:1;
|
||||
unsigned int pad:1;
|
||||
u16 output_flags;
|
||||
} __attribute__ ((packed));
|
||||
} __packed;
|
||||
|
||||
/** This matches the EDID DTD structure, more or less */
|
||||
struct psb_intel_sdvo_dtd {
|
||||
|
|
@ -82,18 +82,18 @@ struct psb_intel_sdvo_dtd {
|
|||
u8 v_sync_off_high;
|
||||
u8 reserved;
|
||||
} part2;
|
||||
} __attribute__ ((packed));
|
||||
} __packed;
|
||||
|
||||
struct psb_intel_sdvo_pixel_clock_range {
|
||||
u16 min; /**< pixel clock, in 10kHz units */
|
||||
u16 max; /**< pixel clock, in 10kHz units */
|
||||
} __attribute__ ((packed));
|
||||
} __packed;
|
||||
|
||||
struct psb_intel_sdvo_preferred_input_timing_args {
|
||||
u16 clock;
|
||||
u16 width;
|
||||
u16 height;
|
||||
} __attribute__ ((packed));
|
||||
} __packed;
|
||||
|
||||
/* I2C registers for SDVO */
|
||||
#define SDVO_I2C_ARG_0 0x07
|
||||
|
|
@ -147,7 +147,7 @@ struct psb_intel_sdvo_get_trained_inputs_response {
|
|||
unsigned int input0_trained:1;
|
||||
unsigned int input1_trained:1;
|
||||
unsigned int pad:6;
|
||||
} __attribute__ ((packed));
|
||||
} __packed;
|
||||
|
||||
/** Returns a struct psb_intel_sdvo_output_flags of active outputs. */
|
||||
#define SDVO_CMD_GET_ACTIVE_OUTPUTS 0x04
|
||||
|
|
@ -201,7 +201,7 @@ struct psb_intel_sdvo_get_interrupt_event_source_response {
|
|||
u16 interrupt_status;
|
||||
unsigned int ambient_light_interrupt:1;
|
||||
unsigned int pad:7;
|
||||
} __attribute__ ((packed));
|
||||
} __packed;
|
||||
|
||||
/**
|
||||
* Selects which input is affected by future input commands.
|
||||
|
|
@ -214,7 +214,7 @@ struct psb_intel_sdvo_get_interrupt_event_source_response {
|
|||
struct psb_intel_sdvo_set_target_input_args {
|
||||
unsigned int target_1:1;
|
||||
unsigned int pad:7;
|
||||
} __attribute__ ((packed));
|
||||
} __packed;
|
||||
|
||||
/**
|
||||
* Takes a struct psb_intel_sdvo_output_flags of which outputs are targeted by
|
||||
|
|
|
|||
|
|
@ -22,161 +22,157 @@
|
|||
#ifndef _PSB_REG_H_
|
||||
#define _PSB_REG_H_
|
||||
|
||||
#define PSB_CR_CLKGATECTL 0x0000
|
||||
#define _PSB_C_CLKGATECTL_AUTO_MAN_REG (1 << 24)
|
||||
#define _PSB_C_CLKGATECTL_USE_CLKG_SHIFT (20)
|
||||
#define _PSB_C_CLKGATECTL_USE_CLKG_MASK (0x3 << 20)
|
||||
#define _PSB_C_CLKGATECTL_DPM_CLKG_SHIFT (16)
|
||||
#define _PSB_C_CLKGATECTL_DPM_CLKG_MASK (0x3 << 16)
|
||||
#define _PSB_C_CLKGATECTL_TA_CLKG_SHIFT (12)
|
||||
#define _PSB_C_CLKGATECTL_TA_CLKG_MASK (0x3 << 12)
|
||||
#define _PSB_C_CLKGATECTL_TSP_CLKG_SHIFT (8)
|
||||
#define _PSB_C_CLKGATECTL_TSP_CLKG_MASK (0x3 << 8)
|
||||
#define _PSB_C_CLKGATECTL_ISP_CLKG_SHIFT (4)
|
||||
#define _PSB_C_CLKGATECTL_ISP_CLKG_MASK (0x3 << 4)
|
||||
#define _PSB_C_CLKGATECTL_2D_CLKG_SHIFT (0)
|
||||
#define _PSB_C_CLKGATECTL_2D_CLKG_MASK (0x3 << 0)
|
||||
#define _PSB_C_CLKGATECTL_CLKG_ENABLED (0)
|
||||
#define _PSB_C_CLKGATECTL_CLKG_DISABLED (1)
|
||||
#define _PSB_C_CLKGATECTL_CLKG_AUTO (2)
|
||||
#define PSB_CR_CLKGATECTL 0x0000
|
||||
#define _PSB_C_CLKGATECTL_AUTO_MAN_REG (1 << 24)
|
||||
#define _PSB_C_CLKGATECTL_USE_CLKG_SHIFT (20)
|
||||
#define _PSB_C_CLKGATECTL_USE_CLKG_MASK (0x3 << 20)
|
||||
#define _PSB_C_CLKGATECTL_DPM_CLKG_SHIFT (16)
|
||||
#define _PSB_C_CLKGATECTL_DPM_CLKG_MASK (0x3 << 16)
|
||||
#define _PSB_C_CLKGATECTL_TA_CLKG_SHIFT (12)
|
||||
#define _PSB_C_CLKGATECTL_TA_CLKG_MASK (0x3 << 12)
|
||||
#define _PSB_C_CLKGATECTL_TSP_CLKG_SHIFT (8)
|
||||
#define _PSB_C_CLKGATECTL_TSP_CLKG_MASK (0x3 << 8)
|
||||
#define _PSB_C_CLKGATECTL_ISP_CLKG_SHIFT (4)
|
||||
#define _PSB_C_CLKGATECTL_ISP_CLKG_MASK (0x3 << 4)
|
||||
#define _PSB_C_CLKGATECTL_2D_CLKG_SHIFT (0)
|
||||
#define _PSB_C_CLKGATECTL_2D_CLKG_MASK (0x3 << 0)
|
||||
#define _PSB_C_CLKGATECTL_CLKG_ENABLED (0)
|
||||
#define _PSB_C_CLKGATECTL_CLKG_DISABLED (1)
|
||||
#define _PSB_C_CLKGATECTL_CLKG_AUTO (2)
|
||||
|
||||
#define PSB_CR_CORE_ID 0x0010
|
||||
#define _PSB_CC_ID_ID_SHIFT (16)
|
||||
#define _PSB_CC_ID_ID_MASK (0xFFFF << 16)
|
||||
#define _PSB_CC_ID_CONFIG_SHIFT (0)
|
||||
#define _PSB_CC_ID_CONFIG_MASK (0xFFFF << 0)
|
||||
#define PSB_CR_CORE_ID 0x0010
|
||||
#define _PSB_CC_ID_ID_SHIFT (16)
|
||||
#define _PSB_CC_ID_ID_MASK (0xFFFF << 16)
|
||||
#define _PSB_CC_ID_CONFIG_SHIFT (0)
|
||||
#define _PSB_CC_ID_CONFIG_MASK (0xFFFF << 0)
|
||||
|
||||
#define PSB_CR_CORE_REVISION 0x0014
|
||||
#define _PSB_CC_REVISION_DESIGNER_SHIFT (24)
|
||||
#define _PSB_CC_REVISION_DESIGNER_MASK (0xFF << 24)
|
||||
#define _PSB_CC_REVISION_MAJOR_SHIFT (16)
|
||||
#define _PSB_CC_REVISION_MAJOR_MASK (0xFF << 16)
|
||||
#define _PSB_CC_REVISION_MINOR_SHIFT (8)
|
||||
#define _PSB_CC_REVISION_MINOR_MASK (0xFF << 8)
|
||||
#define _PSB_CC_REVISION_MAINTENANCE_SHIFT (0)
|
||||
#define _PSB_CC_REVISION_MAINTENANCE_MASK (0xFF << 0)
|
||||
#define PSB_CR_CORE_REVISION 0x0014
|
||||
#define _PSB_CC_REVISION_DESIGNER_SHIFT (24)
|
||||
#define _PSB_CC_REVISION_DESIGNER_MASK (0xFF << 24)
|
||||
#define _PSB_CC_REVISION_MAJOR_SHIFT (16)
|
||||
#define _PSB_CC_REVISION_MAJOR_MASK (0xFF << 16)
|
||||
#define _PSB_CC_REVISION_MINOR_SHIFT (8)
|
||||
#define _PSB_CC_REVISION_MINOR_MASK (0xFF << 8)
|
||||
#define _PSB_CC_REVISION_MAINTENANCE_SHIFT (0)
|
||||
#define _PSB_CC_REVISION_MAINTENANCE_MASK (0xFF << 0)
|
||||
|
||||
#define PSB_CR_DESIGNER_REV_FIELD1 0x0018
|
||||
#define PSB_CR_DESIGNER_REV_FIELD1 0x0018
|
||||
|
||||
#define PSB_CR_SOFT_RESET 0x0080
|
||||
#define _PSB_CS_RESET_TSP_RESET (1 << 6)
|
||||
#define _PSB_CS_RESET_ISP_RESET (1 << 5)
|
||||
#define _PSB_CS_RESET_USE_RESET (1 << 4)
|
||||
#define _PSB_CS_RESET_TA_RESET (1 << 3)
|
||||
#define _PSB_CS_RESET_DPM_RESET (1 << 2)
|
||||
#define _PSB_CS_RESET_TWOD_RESET (1 << 1)
|
||||
#define _PSB_CS_RESET_BIF_RESET (1 << 0)
|
||||
#define PSB_CR_SOFT_RESET 0x0080
|
||||
#define _PSB_CS_RESET_TSP_RESET (1 << 6)
|
||||
#define _PSB_CS_RESET_ISP_RESET (1 << 5)
|
||||
#define _PSB_CS_RESET_USE_RESET (1 << 4)
|
||||
#define _PSB_CS_RESET_TA_RESET (1 << 3)
|
||||
#define _PSB_CS_RESET_DPM_RESET (1 << 2)
|
||||
#define _PSB_CS_RESET_TWOD_RESET (1 << 1)
|
||||
#define _PSB_CS_RESET_BIF_RESET (1 << 0)
|
||||
|
||||
#define PSB_CR_DESIGNER_REV_FIELD2 0x001C
|
||||
#define PSB_CR_DESIGNER_REV_FIELD2 0x001C
|
||||
|
||||
#define PSB_CR_EVENT_HOST_ENABLE2 0x0110
|
||||
#define PSB_CR_EVENT_HOST_ENABLE2 0x0110
|
||||
|
||||
#define PSB_CR_EVENT_STATUS2 0x0118
|
||||
#define PSB_CR_EVENT_STATUS2 0x0118
|
||||
|
||||
#define PSB_CR_EVENT_HOST_CLEAR2 0x0114
|
||||
#define _PSB_CE2_BIF_REQUESTER_FAULT (1 << 4)
|
||||
#define PSB_CR_EVENT_HOST_CLEAR2 0x0114
|
||||
#define _PSB_CE2_BIF_REQUESTER_FAULT (1 << 4)
|
||||
|
||||
#define PSB_CR_EVENT_STATUS 0x012C
|
||||
#define PSB_CR_EVENT_STATUS 0x012C
|
||||
|
||||
#define PSB_CR_EVENT_HOST_ENABLE 0x0130
|
||||
#define PSB_CR_EVENT_HOST_ENABLE 0x0130
|
||||
|
||||
#define PSB_CR_EVENT_HOST_CLEAR 0x0134
|
||||
#define _PSB_CE_MASTER_INTERRUPT (1 << 31)
|
||||
#define _PSB_CE_TA_DPM_FAULT (1 << 28)
|
||||
#define _PSB_CE_TWOD_COMPLETE (1 << 27)
|
||||
#define _PSB_CE_DPM_OUT_OF_MEMORY_ZLS (1 << 25)
|
||||
#define _PSB_CE_DPM_TA_MEM_FREE (1 << 24)
|
||||
#define _PSB_CE_PIXELBE_END_RENDER (1 << 18)
|
||||
#define _PSB_CE_SW_EVENT (1 << 14)
|
||||
#define _PSB_CE_TA_FINISHED (1 << 13)
|
||||
#define _PSB_CE_TA_TERMINATE (1 << 12)
|
||||
#define _PSB_CE_DPM_REACHED_MEM_THRESH (1 << 3)
|
||||
#define _PSB_CE_DPM_OUT_OF_MEMORY_GBL (1 << 2)
|
||||
#define _PSB_CE_DPM_OUT_OF_MEMORY_MT (1 << 1)
|
||||
#define _PSB_CE_DPM_3D_MEM_FREE (1 << 0)
|
||||
#define PSB_CR_EVENT_HOST_CLEAR 0x0134
|
||||
#define _PSB_CE_MASTER_INTERRUPT (1 << 31)
|
||||
#define _PSB_CE_TA_DPM_FAULT (1 << 28)
|
||||
#define _PSB_CE_TWOD_COMPLETE (1 << 27)
|
||||
#define _PSB_CE_DPM_OUT_OF_MEMORY_ZLS (1 << 25)
|
||||
#define _PSB_CE_DPM_TA_MEM_FREE (1 << 24)
|
||||
#define _PSB_CE_PIXELBE_END_RENDER (1 << 18)
|
||||
#define _PSB_CE_SW_EVENT (1 << 14)
|
||||
#define _PSB_CE_TA_FINISHED (1 << 13)
|
||||
#define _PSB_CE_TA_TERMINATE (1 << 12)
|
||||
#define _PSB_CE_DPM_REACHED_MEM_THRESH (1 << 3)
|
||||
#define _PSB_CE_DPM_OUT_OF_MEMORY_GBL (1 << 2)
|
||||
#define _PSB_CE_DPM_OUT_OF_MEMORY_MT (1 << 1)
|
||||
#define _PSB_CE_DPM_3D_MEM_FREE (1 << 0)
|
||||
|
||||
|
||||
#define PSB_USE_OFFSET_MASK 0x0007FFFF
|
||||
#define PSB_USE_OFFSET_SIZE (PSB_USE_OFFSET_MASK + 1)
|
||||
#define PSB_CR_USE_CODE_BASE0 0x0A0C
|
||||
#define PSB_CR_USE_CODE_BASE1 0x0A10
|
||||
#define PSB_CR_USE_CODE_BASE2 0x0A14
|
||||
#define PSB_CR_USE_CODE_BASE3 0x0A18
|
||||
#define PSB_CR_USE_CODE_BASE4 0x0A1C
|
||||
#define PSB_CR_USE_CODE_BASE5 0x0A20
|
||||
#define PSB_CR_USE_CODE_BASE6 0x0A24
|
||||
#define PSB_CR_USE_CODE_BASE7 0x0A28
|
||||
#define PSB_CR_USE_CODE_BASE8 0x0A2C
|
||||
#define PSB_CR_USE_CODE_BASE9 0x0A30
|
||||
#define PSB_CR_USE_CODE_BASE10 0x0A34
|
||||
#define PSB_CR_USE_CODE_BASE11 0x0A38
|
||||
#define PSB_CR_USE_CODE_BASE12 0x0A3C
|
||||
#define PSB_CR_USE_CODE_BASE13 0x0A40
|
||||
#define PSB_CR_USE_CODE_BASE14 0x0A44
|
||||
#define PSB_CR_USE_CODE_BASE15 0x0A48
|
||||
#define PSB_CR_USE_CODE_BASE(_i) (0x0A0C + ((_i) << 2))
|
||||
#define _PSB_CUC_BASE_DM_SHIFT (25)
|
||||
#define _PSB_CUC_BASE_DM_MASK (0x3 << 25)
|
||||
#define _PSB_CUC_BASE_ADDR_SHIFT (0) /* 1024-bit aligned address? */
|
||||
#define _PSB_CUC_BASE_ADDR_ALIGNSHIFT (7)
|
||||
#define _PSB_CUC_BASE_ADDR_MASK (0x1FFFFFF << 0)
|
||||
#define _PSB_CUC_DM_VERTEX (0)
|
||||
#define _PSB_CUC_DM_PIXEL (1)
|
||||
#define _PSB_CUC_DM_RESERVED (2)
|
||||
#define _PSB_CUC_DM_EDM (3)
|
||||
#define PSB_USE_OFFSET_MASK 0x0007FFFF
|
||||
#define PSB_USE_OFFSET_SIZE (PSB_USE_OFFSET_MASK + 1)
|
||||
#define PSB_CR_USE_CODE_BASE0 0x0A0C
|
||||
#define PSB_CR_USE_CODE_BASE1 0x0A10
|
||||
#define PSB_CR_USE_CODE_BASE2 0x0A14
|
||||
#define PSB_CR_USE_CODE_BASE3 0x0A18
|
||||
#define PSB_CR_USE_CODE_BASE4 0x0A1C
|
||||
#define PSB_CR_USE_CODE_BASE5 0x0A20
|
||||
#define PSB_CR_USE_CODE_BASE6 0x0A24
|
||||
#define PSB_CR_USE_CODE_BASE7 0x0A28
|
||||
#define PSB_CR_USE_CODE_BASE8 0x0A2C
|
||||
#define PSB_CR_USE_CODE_BASE9 0x0A30
|
||||
#define PSB_CR_USE_CODE_BASE10 0x0A34
|
||||
#define PSB_CR_USE_CODE_BASE11 0x0A38
|
||||
#define PSB_CR_USE_CODE_BASE12 0x0A3C
|
||||
#define PSB_CR_USE_CODE_BASE13 0x0A40
|
||||
#define PSB_CR_USE_CODE_BASE14 0x0A44
|
||||
#define PSB_CR_USE_CODE_BASE15 0x0A48
|
||||
#define PSB_CR_USE_CODE_BASE(_i) (0x0A0C + ((_i) << 2))
|
||||
#define _PSB_CUC_BASE_DM_SHIFT (25)
|
||||
#define _PSB_CUC_BASE_DM_MASK (0x3 << 25)
|
||||
#define _PSB_CUC_BASE_ADDR_SHIFT (0) /* 1024-bit aligned address? */
|
||||
#define _PSB_CUC_BASE_ADDR_ALIGNSHIFT (7)
|
||||
#define _PSB_CUC_BASE_ADDR_MASK (0x1FFFFFF << 0)
|
||||
#define _PSB_CUC_DM_VERTEX (0)
|
||||
#define _PSB_CUC_DM_PIXEL (1)
|
||||
#define _PSB_CUC_DM_RESERVED (2)
|
||||
#define _PSB_CUC_DM_EDM (3)
|
||||
|
||||
#define PSB_CR_PDS_EXEC_BASE 0x0AB8
|
||||
#define _PSB_CR_PDS_EXEC_BASE_ADDR_SHIFT (20) /* 1MB aligned address */
|
||||
#define _PSB_CR_PDS_EXEC_BASE_ADDR_ALIGNSHIFT (20)
|
||||
#define PSB_CR_PDS_EXEC_BASE 0x0AB8
|
||||
#define _PSB_CR_PDS_EXEC_BASE_ADDR_SHIFT (20) /* 1MB aligned address */
|
||||
#define _PSB_CR_PDS_EXEC_BASE_ADDR_ALIGNSHIFT (20)
|
||||
|
||||
#define PSB_CR_EVENT_KICKER 0x0AC4
|
||||
#define _PSB_CE_KICKER_ADDRESS_SHIFT (4) /* 128-bit aligned address */
|
||||
#define PSB_CR_EVENT_KICKER 0x0AC4
|
||||
#define _PSB_CE_KICKER_ADDRESS_SHIFT (4) /* 128-bit aligned address */
|
||||
|
||||
#define PSB_CR_EVENT_KICK 0x0AC8
|
||||
#define _PSB_CE_KICK_NOW (1 << 0)
|
||||
#define PSB_CR_EVENT_KICK 0x0AC8
|
||||
#define _PSB_CE_KICK_NOW (1 << 0)
|
||||
|
||||
#define PSB_CR_BIF_DIR_LIST_BASE1 0x0C38
|
||||
|
||||
#define PSB_CR_BIF_DIR_LIST_BASE1 0x0C38
|
||||
#define PSB_CR_BIF_CTRL 0x0C00
|
||||
#define _PSB_CB_CTRL_CLEAR_FAULT (1 << 4)
|
||||
#define _PSB_CB_CTRL_INVALDC (1 << 3)
|
||||
#define _PSB_CB_CTRL_FLUSH (1 << 2)
|
||||
|
||||
#define PSB_CR_BIF_CTRL 0x0C00
|
||||
#define _PSB_CB_CTRL_CLEAR_FAULT (1 << 4)
|
||||
#define _PSB_CB_CTRL_INVALDC (1 << 3)
|
||||
#define _PSB_CB_CTRL_FLUSH (1 << 2)
|
||||
#define PSB_CR_BIF_INT_STAT 0x0C04
|
||||
|
||||
#define PSB_CR_BIF_INT_STAT 0x0C04
|
||||
#define PSB_CR_BIF_FAULT 0x0C08
|
||||
#define _PSB_CBI_STAT_PF_N_RW (1 << 14)
|
||||
#define _PSB_CBI_STAT_FAULT_SHIFT (0)
|
||||
#define _PSB_CBI_STAT_FAULT_MASK (0x3FFF << 0)
|
||||
#define _PSB_CBI_STAT_FAULT_CACHE (1 << 1)
|
||||
#define _PSB_CBI_STAT_FAULT_TA (1 << 2)
|
||||
#define _PSB_CBI_STAT_FAULT_VDM (1 << 3)
|
||||
#define _PSB_CBI_STAT_FAULT_2D (1 << 4)
|
||||
#define _PSB_CBI_STAT_FAULT_PBE (1 << 5)
|
||||
#define _PSB_CBI_STAT_FAULT_TSP (1 << 6)
|
||||
#define _PSB_CBI_STAT_FAULT_ISP (1 << 7)
|
||||
#define _PSB_CBI_STAT_FAULT_USSEPDS (1 << 8)
|
||||
#define _PSB_CBI_STAT_FAULT_HOST (1 << 9)
|
||||
|
||||
#define PSB_CR_BIF_FAULT 0x0C08
|
||||
#define _PSB_CBI_STAT_PF_N_RW (1 << 14)
|
||||
#define _PSB_CBI_STAT_FAULT_SHIFT (0)
|
||||
#define _PSB_CBI_STAT_FAULT_MASK (0x3FFF << 0)
|
||||
#define _PSB_CBI_STAT_FAULT_CACHE (1 << 1)
|
||||
#define _PSB_CBI_STAT_FAULT_TA (1 << 2)
|
||||
#define _PSB_CBI_STAT_FAULT_VDM (1 << 3)
|
||||
#define _PSB_CBI_STAT_FAULT_2D (1 << 4)
|
||||
#define _PSB_CBI_STAT_FAULT_PBE (1 << 5)
|
||||
#define _PSB_CBI_STAT_FAULT_TSP (1 << 6)
|
||||
#define _PSB_CBI_STAT_FAULT_ISP (1 << 7)
|
||||
#define _PSB_CBI_STAT_FAULT_USSEPDS (1 << 8)
|
||||
#define _PSB_CBI_STAT_FAULT_HOST (1 << 9)
|
||||
#define PSB_CR_BIF_BANK0 0x0C78
|
||||
#define PSB_CR_BIF_BANK1 0x0C7C
|
||||
#define PSB_CR_BIF_DIR_LIST_BASE0 0x0C84
|
||||
#define PSB_CR_BIF_TWOD_REQ_BASE 0x0C88
|
||||
#define PSB_CR_BIF_3D_REQ_BASE 0x0CAC
|
||||
|
||||
#define PSB_CR_BIF_BANK0 0x0C78
|
||||
#define PSB_CR_2D_SOCIF 0x0E18
|
||||
#define _PSB_C2_SOCIF_FREESPACE_SHIFT (0)
|
||||
#define _PSB_C2_SOCIF_FREESPACE_MASK (0xFF << 0)
|
||||
#define _PSB_C2_SOCIF_EMPTY (0x80 << 0)
|
||||
|
||||
#define PSB_CR_BIF_BANK1 0x0C7C
|
||||
|
||||
#define PSB_CR_BIF_DIR_LIST_BASE0 0x0C84
|
||||
|
||||
#define PSB_CR_BIF_TWOD_REQ_BASE 0x0C88
|
||||
#define PSB_CR_BIF_3D_REQ_BASE 0x0CAC
|
||||
|
||||
#define PSB_CR_2D_SOCIF 0x0E18
|
||||
#define _PSB_C2_SOCIF_FREESPACE_SHIFT (0)
|
||||
#define _PSB_C2_SOCIF_FREESPACE_MASK (0xFF << 0)
|
||||
#define _PSB_C2_SOCIF_EMPTY (0x80 << 0)
|
||||
|
||||
#define PSB_CR_2D_BLIT_STATUS 0x0E04
|
||||
#define _PSB_C2B_STATUS_BUSY (1 << 24)
|
||||
#define _PSB_C2B_STATUS_COMPLETE_SHIFT (0)
|
||||
#define _PSB_C2B_STATUS_COMPLETE_MASK (0xFFFFFF << 0)
|
||||
#define PSB_CR_2D_BLIT_STATUS 0x0E04
|
||||
#define _PSB_C2B_STATUS_BUSY (1 << 24)
|
||||
#define _PSB_C2B_STATUS_COMPLETE_SHIFT (0)
|
||||
#define _PSB_C2B_STATUS_COMPLETE_MASK (0xFFFFFF << 0)
|
||||
|
||||
/*
|
||||
* 2D defs.
|
||||
|
|
@ -186,121 +182,121 @@
|
|||
* 2D Slave Port Data : Block Header's Object Type
|
||||
*/
|
||||
|
||||
#define PSB_2D_CLIP_BH (0x00000000)
|
||||
#define PSB_2D_PAT_BH (0x10000000)
|
||||
#define PSB_2D_CTRL_BH (0x20000000)
|
||||
#define PSB_2D_SRC_OFF_BH (0x30000000)
|
||||
#define PSB_2D_MASK_OFF_BH (0x40000000)
|
||||
#define PSB_2D_RESERVED1_BH (0x50000000)
|
||||
#define PSB_2D_RESERVED2_BH (0x60000000)
|
||||
#define PSB_2D_FENCE_BH (0x70000000)
|
||||
#define PSB_2D_BLIT_BH (0x80000000)
|
||||
#define PSB_2D_SRC_SURF_BH (0x90000000)
|
||||
#define PSB_2D_DST_SURF_BH (0xA0000000)
|
||||
#define PSB_2D_PAT_SURF_BH (0xB0000000)
|
||||
#define PSB_2D_SRC_PAL_BH (0xC0000000)
|
||||
#define PSB_2D_PAT_PAL_BH (0xD0000000)
|
||||
#define PSB_2D_MASK_SURF_BH (0xE0000000)
|
||||
#define PSB_2D_FLUSH_BH (0xF0000000)
|
||||
#define PSB_2D_CLIP_BH (0x00000000)
|
||||
#define PSB_2D_PAT_BH (0x10000000)
|
||||
#define PSB_2D_CTRL_BH (0x20000000)
|
||||
#define PSB_2D_SRC_OFF_BH (0x30000000)
|
||||
#define PSB_2D_MASK_OFF_BH (0x40000000)
|
||||
#define PSB_2D_RESERVED1_BH (0x50000000)
|
||||
#define PSB_2D_RESERVED2_BH (0x60000000)
|
||||
#define PSB_2D_FENCE_BH (0x70000000)
|
||||
#define PSB_2D_BLIT_BH (0x80000000)
|
||||
#define PSB_2D_SRC_SURF_BH (0x90000000)
|
||||
#define PSB_2D_DST_SURF_BH (0xA0000000)
|
||||
#define PSB_2D_PAT_SURF_BH (0xB0000000)
|
||||
#define PSB_2D_SRC_PAL_BH (0xC0000000)
|
||||
#define PSB_2D_PAT_PAL_BH (0xD0000000)
|
||||
#define PSB_2D_MASK_SURF_BH (0xE0000000)
|
||||
#define PSB_2D_FLUSH_BH (0xF0000000)
|
||||
|
||||
/*
|
||||
* Clip Definition block (PSB_2D_CLIP_BH)
|
||||
*/
|
||||
#define PSB_2D_CLIPCOUNT_MAX (1)
|
||||
#define PSB_2D_CLIPCOUNT_MASK (0x00000000)
|
||||
#define PSB_2D_CLIPCOUNT_CLRMASK (0xFFFFFFFF)
|
||||
#define PSB_2D_CLIPCOUNT_SHIFT (0)
|
||||
#define PSB_2D_CLIPCOUNT_MAX (1)
|
||||
#define PSB_2D_CLIPCOUNT_MASK (0x00000000)
|
||||
#define PSB_2D_CLIPCOUNT_CLRMASK (0xFFFFFFFF)
|
||||
#define PSB_2D_CLIPCOUNT_SHIFT (0)
|
||||
/* clip rectangle min & max */
|
||||
#define PSB_2D_CLIP_XMAX_MASK (0x00FFF000)
|
||||
#define PSB_2D_CLIP_XMAX_CLRMASK (0xFF000FFF)
|
||||
#define PSB_2D_CLIP_XMAX_SHIFT (12)
|
||||
#define PSB_2D_CLIP_XMIN_MASK (0x00000FFF)
|
||||
#define PSB_2D_CLIP_XMIN_CLRMASK (0x00FFF000)
|
||||
#define PSB_2D_CLIP_XMIN_SHIFT (0)
|
||||
#define PSB_2D_CLIP_XMAX_MASK (0x00FFF000)
|
||||
#define PSB_2D_CLIP_XMAX_CLRMASK (0xFF000FFF)
|
||||
#define PSB_2D_CLIP_XMAX_SHIFT (12)
|
||||
#define PSB_2D_CLIP_XMIN_MASK (0x00000FFF)
|
||||
#define PSB_2D_CLIP_XMIN_CLRMASK (0x00FFF000)
|
||||
#define PSB_2D_CLIP_XMIN_SHIFT (0)
|
||||
/* clip rectangle offset */
|
||||
#define PSB_2D_CLIP_YMAX_MASK (0x00FFF000)
|
||||
#define PSB_2D_CLIP_YMAX_CLRMASK (0xFF000FFF)
|
||||
#define PSB_2D_CLIP_YMAX_SHIFT (12)
|
||||
#define PSB_2D_CLIP_YMIN_MASK (0x00000FFF)
|
||||
#define PSB_2D_CLIP_YMIN_CLRMASK (0x00FFF000)
|
||||
#define PSB_2D_CLIP_YMIN_SHIFT (0)
|
||||
#define PSB_2D_CLIP_YMAX_MASK (0x00FFF000)
|
||||
#define PSB_2D_CLIP_YMAX_CLRMASK (0xFF000FFF)
|
||||
#define PSB_2D_CLIP_YMAX_SHIFT (12)
|
||||
#define PSB_2D_CLIP_YMIN_MASK (0x00000FFF)
|
||||
#define PSB_2D_CLIP_YMIN_CLRMASK (0x00FFF000)
|
||||
#define PSB_2D_CLIP_YMIN_SHIFT (0)
|
||||
|
||||
/*
|
||||
* Pattern Control (PSB_2D_PAT_BH)
|
||||
*/
|
||||
#define PSB_2D_PAT_HEIGHT_MASK (0x0000001F)
|
||||
#define PSB_2D_PAT_HEIGHT_SHIFT (0)
|
||||
#define PSB_2D_PAT_WIDTH_MASK (0x000003E0)
|
||||
#define PSB_2D_PAT_WIDTH_SHIFT (5)
|
||||
#define PSB_2D_PAT_YSTART_MASK (0x00007C00)
|
||||
#define PSB_2D_PAT_YSTART_SHIFT (10)
|
||||
#define PSB_2D_PAT_XSTART_MASK (0x000F8000)
|
||||
#define PSB_2D_PAT_XSTART_SHIFT (15)
|
||||
#define PSB_2D_PAT_HEIGHT_MASK (0x0000001F)
|
||||
#define PSB_2D_PAT_HEIGHT_SHIFT (0)
|
||||
#define PSB_2D_PAT_WIDTH_MASK (0x000003E0)
|
||||
#define PSB_2D_PAT_WIDTH_SHIFT (5)
|
||||
#define PSB_2D_PAT_YSTART_MASK (0x00007C00)
|
||||
#define PSB_2D_PAT_YSTART_SHIFT (10)
|
||||
#define PSB_2D_PAT_XSTART_MASK (0x000F8000)
|
||||
#define PSB_2D_PAT_XSTART_SHIFT (15)
|
||||
|
||||
/*
|
||||
* 2D Control block (PSB_2D_CTRL_BH)
|
||||
*/
|
||||
/* Present Flags */
|
||||
#define PSB_2D_SRCCK_CTRL (0x00000001)
|
||||
#define PSB_2D_DSTCK_CTRL (0x00000002)
|
||||
#define PSB_2D_ALPHA_CTRL (0x00000004)
|
||||
#define PSB_2D_SRCCK_CTRL (0x00000001)
|
||||
#define PSB_2D_DSTCK_CTRL (0x00000002)
|
||||
#define PSB_2D_ALPHA_CTRL (0x00000004)
|
||||
/* Colour Key Colour (SRC/DST)*/
|
||||
#define PSB_2D_CK_COL_MASK (0xFFFFFFFF)
|
||||
#define PSB_2D_CK_COL_CLRMASK (0x00000000)
|
||||
#define PSB_2D_CK_COL_SHIFT (0)
|
||||
#define PSB_2D_CK_COL_MASK (0xFFFFFFFF)
|
||||
#define PSB_2D_CK_COL_CLRMASK (0x00000000)
|
||||
#define PSB_2D_CK_COL_SHIFT (0)
|
||||
/* Colour Key Mask (SRC/DST)*/
|
||||
#define PSB_2D_CK_MASK_MASK (0xFFFFFFFF)
|
||||
#define PSB_2D_CK_MASK_CLRMASK (0x00000000)
|
||||
#define PSB_2D_CK_MASK_SHIFT (0)
|
||||
#define PSB_2D_CK_MASK_MASK (0xFFFFFFFF)
|
||||
#define PSB_2D_CK_MASK_CLRMASK (0x00000000)
|
||||
#define PSB_2D_CK_MASK_SHIFT (0)
|
||||
/* Alpha Control (Alpha/RGB)*/
|
||||
#define PSB_2D_GBLALPHA_MASK (0x000FF000)
|
||||
#define PSB_2D_GBLALPHA_CLRMASK (0xFFF00FFF)
|
||||
#define PSB_2D_GBLALPHA_SHIFT (12)
|
||||
#define PSB_2D_SRCALPHA_OP_MASK (0x00700000)
|
||||
#define PSB_2D_SRCALPHA_OP_CLRMASK (0xFF8FFFFF)
|
||||
#define PSB_2D_SRCALPHA_OP_SHIFT (20)
|
||||
#define PSB_2D_SRCALPHA_OP_ONE (0x00000000)
|
||||
#define PSB_2D_SRCALPHA_OP_SRC (0x00100000)
|
||||
#define PSB_2D_SRCALPHA_OP_DST (0x00200000)
|
||||
#define PSB_2D_SRCALPHA_OP_SG (0x00300000)
|
||||
#define PSB_2D_SRCALPHA_OP_DG (0x00400000)
|
||||
#define PSB_2D_SRCALPHA_OP_GBL (0x00500000)
|
||||
#define PSB_2D_SRCALPHA_OP_ZERO (0x00600000)
|
||||
#define PSB_2D_SRCALPHA_INVERT (0x00800000)
|
||||
#define PSB_2D_SRCALPHA_INVERT_CLR (0xFF7FFFFF)
|
||||
#define PSB_2D_DSTALPHA_OP_MASK (0x07000000)
|
||||
#define PSB_2D_DSTALPHA_OP_CLRMASK (0xF8FFFFFF)
|
||||
#define PSB_2D_DSTALPHA_OP_SHIFT (24)
|
||||
#define PSB_2D_DSTALPHA_OP_ONE (0x00000000)
|
||||
#define PSB_2D_DSTALPHA_OP_SRC (0x01000000)
|
||||
#define PSB_2D_DSTALPHA_OP_DST (0x02000000)
|
||||
#define PSB_2D_DSTALPHA_OP_SG (0x03000000)
|
||||
#define PSB_2D_DSTALPHA_OP_DG (0x04000000)
|
||||
#define PSB_2D_DSTALPHA_OP_GBL (0x05000000)
|
||||
#define PSB_2D_DSTALPHA_OP_ZERO (0x06000000)
|
||||
#define PSB_2D_DSTALPHA_INVERT (0x08000000)
|
||||
#define PSB_2D_DSTALPHA_INVERT_CLR (0xF7FFFFFF)
|
||||
#define PSB_2D_GBLALPHA_MASK (0x000FF000)
|
||||
#define PSB_2D_GBLALPHA_CLRMASK (0xFFF00FFF)
|
||||
#define PSB_2D_GBLALPHA_SHIFT (12)
|
||||
#define PSB_2D_SRCALPHA_OP_MASK (0x00700000)
|
||||
#define PSB_2D_SRCALPHA_OP_CLRMASK (0xFF8FFFFF)
|
||||
#define PSB_2D_SRCALPHA_OP_SHIFT (20)
|
||||
#define PSB_2D_SRCALPHA_OP_ONE (0x00000000)
|
||||
#define PSB_2D_SRCALPHA_OP_SRC (0x00100000)
|
||||
#define PSB_2D_SRCALPHA_OP_DST (0x00200000)
|
||||
#define PSB_2D_SRCALPHA_OP_SG (0x00300000)
|
||||
#define PSB_2D_SRCALPHA_OP_DG (0x00400000)
|
||||
#define PSB_2D_SRCALPHA_OP_GBL (0x00500000)
|
||||
#define PSB_2D_SRCALPHA_OP_ZERO (0x00600000)
|
||||
#define PSB_2D_SRCALPHA_INVERT (0x00800000)
|
||||
#define PSB_2D_SRCALPHA_INVERT_CLR (0xFF7FFFFF)
|
||||
#define PSB_2D_DSTALPHA_OP_MASK (0x07000000)
|
||||
#define PSB_2D_DSTALPHA_OP_CLRMASK (0xF8FFFFFF)
|
||||
#define PSB_2D_DSTALPHA_OP_SHIFT (24)
|
||||
#define PSB_2D_DSTALPHA_OP_ONE (0x00000000)
|
||||
#define PSB_2D_DSTALPHA_OP_SRC (0x01000000)
|
||||
#define PSB_2D_DSTALPHA_OP_DST (0x02000000)
|
||||
#define PSB_2D_DSTALPHA_OP_SG (0x03000000)
|
||||
#define PSB_2D_DSTALPHA_OP_DG (0x04000000)
|
||||
#define PSB_2D_DSTALPHA_OP_GBL (0x05000000)
|
||||
#define PSB_2D_DSTALPHA_OP_ZERO (0x06000000)
|
||||
#define PSB_2D_DSTALPHA_INVERT (0x08000000)
|
||||
#define PSB_2D_DSTALPHA_INVERT_CLR (0xF7FFFFFF)
|
||||
|
||||
#define PSB_2D_PRE_MULTIPLICATION_ENABLE (0x10000000)
|
||||
#define PSB_2D_PRE_MULTIPLICATION_CLRMASK (0xEFFFFFFF)
|
||||
#define PSB_2D_ZERO_SOURCE_ALPHA_ENABLE (0x20000000)
|
||||
#define PSB_2D_ZERO_SOURCE_ALPHA_CLRMASK (0xDFFFFFFF)
|
||||
#define PSB_2D_PRE_MULTIPLICATION_ENABLE (0x10000000)
|
||||
#define PSB_2D_PRE_MULTIPLICATION_CLRMASK (0xEFFFFFFF)
|
||||
#define PSB_2D_ZERO_SOURCE_ALPHA_ENABLE (0x20000000)
|
||||
#define PSB_2D_ZERO_SOURCE_ALPHA_CLRMASK (0xDFFFFFFF)
|
||||
|
||||
/*
|
||||
*Source Offset (PSB_2D_SRC_OFF_BH)
|
||||
*/
|
||||
#define PSB_2D_SRCOFF_XSTART_MASK ((0x00000FFF) << 12)
|
||||
#define PSB_2D_SRCOFF_XSTART_SHIFT (12)
|
||||
#define PSB_2D_SRCOFF_YSTART_MASK (0x00000FFF)
|
||||
#define PSB_2D_SRCOFF_YSTART_SHIFT (0)
|
||||
#define PSB_2D_SRCOFF_XSTART_MASK ((0x00000FFF) << 12)
|
||||
#define PSB_2D_SRCOFF_XSTART_SHIFT (12)
|
||||
#define PSB_2D_SRCOFF_YSTART_MASK (0x00000FFF)
|
||||
#define PSB_2D_SRCOFF_YSTART_SHIFT (0)
|
||||
|
||||
/*
|
||||
* Mask Offset (PSB_2D_MASK_OFF_BH)
|
||||
*/
|
||||
#define PSB_2D_MASKOFF_XSTART_MASK ((0x00000FFF) << 12)
|
||||
#define PSB_2D_MASKOFF_XSTART_SHIFT (12)
|
||||
#define PSB_2D_MASKOFF_YSTART_MASK (0x00000FFF)
|
||||
#define PSB_2D_MASKOFF_YSTART_SHIFT (0)
|
||||
#define PSB_2D_MASKOFF_XSTART_MASK ((0x00000FFF) << 12)
|
||||
#define PSB_2D_MASKOFF_XSTART_SHIFT (12)
|
||||
#define PSB_2D_MASKOFF_YSTART_MASK (0x00000FFF)
|
||||
#define PSB_2D_MASKOFF_YSTART_SHIFT (0)
|
||||
|
||||
/*
|
||||
* 2D Fence (see PSB_2D_FENCE_BH): bits 0:27 are ignored
|
||||
|
|
@ -310,118 +306,118 @@
|
|||
*Blit Rectangle (PSB_2D_BLIT_BH)
|
||||
*/
|
||||
|
||||
#define PSB_2D_ROT_MASK (3<<25)
|
||||
#define PSB_2D_ROT_CLRMASK (~PSB_2D_ROT_MASK)
|
||||
#define PSB_2D_ROT_NONE (0<<25)
|
||||
#define PSB_2D_ROT_90DEGS (1<<25)
|
||||
#define PSB_2D_ROT_180DEGS (2<<25)
|
||||
#define PSB_2D_ROT_270DEGS (3<<25)
|
||||
#define PSB_2D_ROT_MASK (3 << 25)
|
||||
#define PSB_2D_ROT_CLRMASK (~PSB_2D_ROT_MASK)
|
||||
#define PSB_2D_ROT_NONE (0 << 25)
|
||||
#define PSB_2D_ROT_90DEGS (1 << 25)
|
||||
#define PSB_2D_ROT_180DEGS (2 << 25)
|
||||
#define PSB_2D_ROT_270DEGS (3 << 25)
|
||||
|
||||
#define PSB_2D_COPYORDER_MASK (3<<23)
|
||||
#define PSB_2D_COPYORDER_CLRMASK (~PSB_2D_COPYORDER_MASK)
|
||||
#define PSB_2D_COPYORDER_TL2BR (0<<23)
|
||||
#define PSB_2D_COPYORDER_BR2TL (1<<23)
|
||||
#define PSB_2D_COPYORDER_TR2BL (2<<23)
|
||||
#define PSB_2D_COPYORDER_BL2TR (3<<23)
|
||||
#define PSB_2D_COPYORDER_MASK (3 << 23)
|
||||
#define PSB_2D_COPYORDER_CLRMASK (~PSB_2D_COPYORDER_MASK)
|
||||
#define PSB_2D_COPYORDER_TL2BR (0 << 23)
|
||||
#define PSB_2D_COPYORDER_BR2TL (1 << 23)
|
||||
#define PSB_2D_COPYORDER_TR2BL (2 << 23)
|
||||
#define PSB_2D_COPYORDER_BL2TR (3 << 23)
|
||||
|
||||
#define PSB_2D_DSTCK_CLRMASK (0xFF9FFFFF)
|
||||
#define PSB_2D_DSTCK_DISABLE (0x00000000)
|
||||
#define PSB_2D_DSTCK_PASS (0x00200000)
|
||||
#define PSB_2D_DSTCK_REJECT (0x00400000)
|
||||
#define PSB_2D_DSTCK_CLRMASK (0xFF9FFFFF)
|
||||
#define PSB_2D_DSTCK_DISABLE (0x00000000)
|
||||
#define PSB_2D_DSTCK_PASS (0x00200000)
|
||||
#define PSB_2D_DSTCK_REJECT (0x00400000)
|
||||
|
||||
#define PSB_2D_SRCCK_CLRMASK (0xFFE7FFFF)
|
||||
#define PSB_2D_SRCCK_DISABLE (0x00000000)
|
||||
#define PSB_2D_SRCCK_PASS (0x00080000)
|
||||
#define PSB_2D_SRCCK_REJECT (0x00100000)
|
||||
#define PSB_2D_SRCCK_CLRMASK (0xFFE7FFFF)
|
||||
#define PSB_2D_SRCCK_DISABLE (0x00000000)
|
||||
#define PSB_2D_SRCCK_PASS (0x00080000)
|
||||
#define PSB_2D_SRCCK_REJECT (0x00100000)
|
||||
|
||||
#define PSB_2D_CLIP_ENABLE (0x00040000)
|
||||
#define PSB_2D_CLIP_ENABLE (0x00040000)
|
||||
|
||||
#define PSB_2D_ALPHA_ENABLE (0x00020000)
|
||||
#define PSB_2D_ALPHA_ENABLE (0x00020000)
|
||||
|
||||
#define PSB_2D_PAT_CLRMASK (0xFFFEFFFF)
|
||||
#define PSB_2D_PAT_MASK (0x00010000)
|
||||
#define PSB_2D_USE_PAT (0x00010000)
|
||||
#define PSB_2D_USE_FILL (0x00000000)
|
||||
#define PSB_2D_PAT_CLRMASK (0xFFFEFFFF)
|
||||
#define PSB_2D_PAT_MASK (0x00010000)
|
||||
#define PSB_2D_USE_PAT (0x00010000)
|
||||
#define PSB_2D_USE_FILL (0x00000000)
|
||||
/*
|
||||
* Tungsten Graphics note on rop codes: If rop A and rop B are
|
||||
* identical, the mask surface will not be read and need not be
|
||||
* set up.
|
||||
*/
|
||||
|
||||
#define PSB_2D_ROP3B_MASK (0x0000FF00)
|
||||
#define PSB_2D_ROP3B_CLRMASK (0xFFFF00FF)
|
||||
#define PSB_2D_ROP3B_SHIFT (8)
|
||||
#define PSB_2D_ROP3B_MASK (0x0000FF00)
|
||||
#define PSB_2D_ROP3B_CLRMASK (0xFFFF00FF)
|
||||
#define PSB_2D_ROP3B_SHIFT (8)
|
||||
/* rop code A */
|
||||
#define PSB_2D_ROP3A_MASK (0x000000FF)
|
||||
#define PSB_2D_ROP3A_CLRMASK (0xFFFFFF00)
|
||||
#define PSB_2D_ROP3A_SHIFT (0)
|
||||
#define PSB_2D_ROP3A_MASK (0x000000FF)
|
||||
#define PSB_2D_ROP3A_CLRMASK (0xFFFFFF00)
|
||||
#define PSB_2D_ROP3A_SHIFT (0)
|
||||
|
||||
#define PSB_2D_ROP4_MASK (0x0000FFFF)
|
||||
#define PSB_2D_ROP4_MASK (0x0000FFFF)
|
||||
/*
|
||||
* DWORD0: (Only pass if Pattern control == Use Fill Colour)
|
||||
* Fill Colour RGBA8888
|
||||
*/
|
||||
#define PSB_2D_FILLCOLOUR_MASK (0xFFFFFFFF)
|
||||
#define PSB_2D_FILLCOLOUR_SHIFT (0)
|
||||
#define PSB_2D_FILLCOLOUR_MASK (0xFFFFFFFF)
|
||||
#define PSB_2D_FILLCOLOUR_SHIFT (0)
|
||||
/*
|
||||
* DWORD1: (Always Present)
|
||||
* X Start (Dest)
|
||||
* Y Start (Dest)
|
||||
*/
|
||||
#define PSB_2D_DST_XSTART_MASK (0x00FFF000)
|
||||
#define PSB_2D_DST_XSTART_CLRMASK (0xFF000FFF)
|
||||
#define PSB_2D_DST_XSTART_SHIFT (12)
|
||||
#define PSB_2D_DST_YSTART_MASK (0x00000FFF)
|
||||
#define PSB_2D_DST_YSTART_CLRMASK (0xFFFFF000)
|
||||
#define PSB_2D_DST_YSTART_SHIFT (0)
|
||||
#define PSB_2D_DST_XSTART_MASK (0x00FFF000)
|
||||
#define PSB_2D_DST_XSTART_CLRMASK (0xFF000FFF)
|
||||
#define PSB_2D_DST_XSTART_SHIFT (12)
|
||||
#define PSB_2D_DST_YSTART_MASK (0x00000FFF)
|
||||
#define PSB_2D_DST_YSTART_CLRMASK (0xFFFFF000)
|
||||
#define PSB_2D_DST_YSTART_SHIFT (0)
|
||||
/*
|
||||
* DWORD2: (Always Present)
|
||||
* X Size (Dest)
|
||||
* Y Size (Dest)
|
||||
*/
|
||||
#define PSB_2D_DST_XSIZE_MASK (0x00FFF000)
|
||||
#define PSB_2D_DST_XSIZE_CLRMASK (0xFF000FFF)
|
||||
#define PSB_2D_DST_XSIZE_SHIFT (12)
|
||||
#define PSB_2D_DST_YSIZE_MASK (0x00000FFF)
|
||||
#define PSB_2D_DST_YSIZE_CLRMASK (0xFFFFF000)
|
||||
#define PSB_2D_DST_YSIZE_SHIFT (0)
|
||||
#define PSB_2D_DST_XSIZE_MASK (0x00FFF000)
|
||||
#define PSB_2D_DST_XSIZE_CLRMASK (0xFF000FFF)
|
||||
#define PSB_2D_DST_XSIZE_SHIFT (12)
|
||||
#define PSB_2D_DST_YSIZE_MASK (0x00000FFF)
|
||||
#define PSB_2D_DST_YSIZE_CLRMASK (0xFFFFF000)
|
||||
#define PSB_2D_DST_YSIZE_SHIFT (0)
|
||||
|
||||
/*
|
||||
* Source Surface (PSB_2D_SRC_SURF_BH)
|
||||
*/
|
||||
/*
|
||||
* WORD 0
|
||||
* WORD 0
|
||||
*/
|
||||
|
||||
#define PSB_2D_SRC_FORMAT_MASK (0x00078000)
|
||||
#define PSB_2D_SRC_1_PAL (0x00000000)
|
||||
#define PSB_2D_SRC_2_PAL (0x00008000)
|
||||
#define PSB_2D_SRC_4_PAL (0x00010000)
|
||||
#define PSB_2D_SRC_8_PAL (0x00018000)
|
||||
#define PSB_2D_SRC_8_ALPHA (0x00020000)
|
||||
#define PSB_2D_SRC_4_ALPHA (0x00028000)
|
||||
#define PSB_2D_SRC_332RGB (0x00030000)
|
||||
#define PSB_2D_SRC_4444ARGB (0x00038000)
|
||||
#define PSB_2D_SRC_555RGB (0x00040000)
|
||||
#define PSB_2D_SRC_1555ARGB (0x00048000)
|
||||
#define PSB_2D_SRC_565RGB (0x00050000)
|
||||
#define PSB_2D_SRC_0888ARGB (0x00058000)
|
||||
#define PSB_2D_SRC_8888ARGB (0x00060000)
|
||||
#define PSB_2D_SRC_8888UYVY (0x00068000)
|
||||
#define PSB_2D_SRC_RESERVED (0x00070000)
|
||||
#define PSB_2D_SRC_1555ARGB_LOOKUP (0x00078000)
|
||||
#define PSB_2D_SRC_FORMAT_MASK (0x00078000)
|
||||
#define PSB_2D_SRC_1_PAL (0x00000000)
|
||||
#define PSB_2D_SRC_2_PAL (0x00008000)
|
||||
#define PSB_2D_SRC_4_PAL (0x00010000)
|
||||
#define PSB_2D_SRC_8_PAL (0x00018000)
|
||||
#define PSB_2D_SRC_8_ALPHA (0x00020000)
|
||||
#define PSB_2D_SRC_4_ALPHA (0x00028000)
|
||||
#define PSB_2D_SRC_332RGB (0x00030000)
|
||||
#define PSB_2D_SRC_4444ARGB (0x00038000)
|
||||
#define PSB_2D_SRC_555RGB (0x00040000)
|
||||
#define PSB_2D_SRC_1555ARGB (0x00048000)
|
||||
#define PSB_2D_SRC_565RGB (0x00050000)
|
||||
#define PSB_2D_SRC_0888ARGB (0x00058000)
|
||||
#define PSB_2D_SRC_8888ARGB (0x00060000)
|
||||
#define PSB_2D_SRC_8888UYVY (0x00068000)
|
||||
#define PSB_2D_SRC_RESERVED (0x00070000)
|
||||
#define PSB_2D_SRC_1555ARGB_LOOKUP (0x00078000)
|
||||
|
||||
|
||||
#define PSB_2D_SRC_STRIDE_MASK (0x00007FFF)
|
||||
#define PSB_2D_SRC_STRIDE_CLRMASK (0xFFFF8000)
|
||||
#define PSB_2D_SRC_STRIDE_SHIFT (0)
|
||||
#define PSB_2D_SRC_STRIDE_MASK (0x00007FFF)
|
||||
#define PSB_2D_SRC_STRIDE_CLRMASK (0xFFFF8000)
|
||||
#define PSB_2D_SRC_STRIDE_SHIFT (0)
|
||||
/*
|
||||
* WORD 1 - Base Address
|
||||
*/
|
||||
#define PSB_2D_SRC_ADDR_MASK (0x0FFFFFFC)
|
||||
#define PSB_2D_SRC_ADDR_CLRMASK (0x00000003)
|
||||
#define PSB_2D_SRC_ADDR_SHIFT (2)
|
||||
#define PSB_2D_SRC_ADDR_ALIGNSHIFT (2)
|
||||
#define PSB_2D_SRC_ADDR_MASK (0x0FFFFFFC)
|
||||
#define PSB_2D_SRC_ADDR_CLRMASK (0x00000003)
|
||||
#define PSB_2D_SRC_ADDR_SHIFT (2)
|
||||
#define PSB_2D_SRC_ADDR_ALIGNSHIFT (2)
|
||||
|
||||
/*
|
||||
* Pattern Surface (PSB_2D_PAT_SURF_BH)
|
||||
|
|
@ -430,31 +426,31 @@
|
|||
* WORD 0
|
||||
*/
|
||||
|
||||
#define PSB_2D_PAT_FORMAT_MASK (0x00078000)
|
||||
#define PSB_2D_PAT_1_PAL (0x00000000)
|
||||
#define PSB_2D_PAT_2_PAL (0x00008000)
|
||||
#define PSB_2D_PAT_4_PAL (0x00010000)
|
||||
#define PSB_2D_PAT_8_PAL (0x00018000)
|
||||
#define PSB_2D_PAT_8_ALPHA (0x00020000)
|
||||
#define PSB_2D_PAT_4_ALPHA (0x00028000)
|
||||
#define PSB_2D_PAT_332RGB (0x00030000)
|
||||
#define PSB_2D_PAT_4444ARGB (0x00038000)
|
||||
#define PSB_2D_PAT_555RGB (0x00040000)
|
||||
#define PSB_2D_PAT_1555ARGB (0x00048000)
|
||||
#define PSB_2D_PAT_565RGB (0x00050000)
|
||||
#define PSB_2D_PAT_0888ARGB (0x00058000)
|
||||
#define PSB_2D_PAT_8888ARGB (0x00060000)
|
||||
#define PSB_2D_PAT_FORMAT_MASK (0x00078000)
|
||||
#define PSB_2D_PAT_1_PAL (0x00000000)
|
||||
#define PSB_2D_PAT_2_PAL (0x00008000)
|
||||
#define PSB_2D_PAT_4_PAL (0x00010000)
|
||||
#define PSB_2D_PAT_8_PAL (0x00018000)
|
||||
#define PSB_2D_PAT_8_ALPHA (0x00020000)
|
||||
#define PSB_2D_PAT_4_ALPHA (0x00028000)
|
||||
#define PSB_2D_PAT_332RGB (0x00030000)
|
||||
#define PSB_2D_PAT_4444ARGB (0x00038000)
|
||||
#define PSB_2D_PAT_555RGB (0x00040000)
|
||||
#define PSB_2D_PAT_1555ARGB (0x00048000)
|
||||
#define PSB_2D_PAT_565RGB (0x00050000)
|
||||
#define PSB_2D_PAT_0888ARGB (0x00058000)
|
||||
#define PSB_2D_PAT_8888ARGB (0x00060000)
|
||||
|
||||
#define PSB_2D_PAT_STRIDE_MASK (0x00007FFF)
|
||||
#define PSB_2D_PAT_STRIDE_CLRMASK (0xFFFF8000)
|
||||
#define PSB_2D_PAT_STRIDE_SHIFT (0)
|
||||
#define PSB_2D_PAT_STRIDE_MASK (0x00007FFF)
|
||||
#define PSB_2D_PAT_STRIDE_CLRMASK (0xFFFF8000)
|
||||
#define PSB_2D_PAT_STRIDE_SHIFT (0)
|
||||
/*
|
||||
* WORD 1 - Base Address
|
||||
*/
|
||||
#define PSB_2D_PAT_ADDR_MASK (0x0FFFFFFC)
|
||||
#define PSB_2D_PAT_ADDR_CLRMASK (0x00000003)
|
||||
#define PSB_2D_PAT_ADDR_SHIFT (2)
|
||||
#define PSB_2D_PAT_ADDR_ALIGNSHIFT (2)
|
||||
#define PSB_2D_PAT_ADDR_MASK (0x0FFFFFFC)
|
||||
#define PSB_2D_PAT_ADDR_CLRMASK (0x00000003)
|
||||
#define PSB_2D_PAT_ADDR_SHIFT (2)
|
||||
#define PSB_2D_PAT_ADDR_ALIGNSHIFT (2)
|
||||
|
||||
/*
|
||||
* Destination Surface (PSB_2D_DST_SURF_BH)
|
||||
|
|
@ -463,26 +459,26 @@
|
|||
* WORD 0
|
||||
*/
|
||||
|
||||
#define PSB_2D_DST_FORMAT_MASK (0x00078000)
|
||||
#define PSB_2D_DST_332RGB (0x00030000)
|
||||
#define PSB_2D_DST_4444ARGB (0x00038000)
|
||||
#define PSB_2D_DST_555RGB (0x00040000)
|
||||
#define PSB_2D_DST_1555ARGB (0x00048000)
|
||||
#define PSB_2D_DST_565RGB (0x00050000)
|
||||
#define PSB_2D_DST_0888ARGB (0x00058000)
|
||||
#define PSB_2D_DST_8888ARGB (0x00060000)
|
||||
#define PSB_2D_DST_8888AYUV (0x00070000)
|
||||
#define PSB_2D_DST_FORMAT_MASK (0x00078000)
|
||||
#define PSB_2D_DST_332RGB (0x00030000)
|
||||
#define PSB_2D_DST_4444ARGB (0x00038000)
|
||||
#define PSB_2D_DST_555RGB (0x00040000)
|
||||
#define PSB_2D_DST_1555ARGB (0x00048000)
|
||||
#define PSB_2D_DST_565RGB (0x00050000)
|
||||
#define PSB_2D_DST_0888ARGB (0x00058000)
|
||||
#define PSB_2D_DST_8888ARGB (0x00060000)
|
||||
#define PSB_2D_DST_8888AYUV (0x00070000)
|
||||
|
||||
#define PSB_2D_DST_STRIDE_MASK (0x00007FFF)
|
||||
#define PSB_2D_DST_STRIDE_CLRMASK (0xFFFF8000)
|
||||
#define PSB_2D_DST_STRIDE_SHIFT (0)
|
||||
#define PSB_2D_DST_STRIDE_MASK (0x00007FFF)
|
||||
#define PSB_2D_DST_STRIDE_CLRMASK (0xFFFF8000)
|
||||
#define PSB_2D_DST_STRIDE_SHIFT (0)
|
||||
/*
|
||||
* WORD 1 - Base Address
|
||||
*/
|
||||
#define PSB_2D_DST_ADDR_MASK (0x0FFFFFFC)
|
||||
#define PSB_2D_DST_ADDR_CLRMASK (0x00000003)
|
||||
#define PSB_2D_DST_ADDR_SHIFT (2)
|
||||
#define PSB_2D_DST_ADDR_ALIGNSHIFT (2)
|
||||
#define PSB_2D_DST_ADDR_MASK (0x0FFFFFFC)
|
||||
#define PSB_2D_DST_ADDR_CLRMASK (0x00000003)
|
||||
#define PSB_2D_DST_ADDR_SHIFT (2)
|
||||
#define PSB_2D_DST_ADDR_ALIGNSHIFT (2)
|
||||
|
||||
/*
|
||||
* Mask Surface (PSB_2D_MASK_SURF_BH)
|
||||
|
|
@ -490,99 +486,97 @@
|
|||
/*
|
||||
* WORD 0
|
||||
*/
|
||||
#define PSB_2D_MASK_STRIDE_MASK (0x00007FFF)
|
||||
#define PSB_2D_MASK_STRIDE_CLRMASK (0xFFFF8000)
|
||||
#define PSB_2D_MASK_STRIDE_SHIFT (0)
|
||||
#define PSB_2D_MASK_STRIDE_MASK (0x00007FFF)
|
||||
#define PSB_2D_MASK_STRIDE_CLRMASK (0xFFFF8000)
|
||||
#define PSB_2D_MASK_STRIDE_SHIFT (0)
|
||||
/*
|
||||
* WORD 1 - Base Address
|
||||
*/
|
||||
#define PSB_2D_MASK_ADDR_MASK (0x0FFFFFFC)
|
||||
#define PSB_2D_MASK_ADDR_CLRMASK (0x00000003)
|
||||
#define PSB_2D_MASK_ADDR_SHIFT (2)
|
||||
#define PSB_2D_MASK_ADDR_ALIGNSHIFT (2)
|
||||
#define PSB_2D_MASK_ADDR_MASK (0x0FFFFFFC)
|
||||
#define PSB_2D_MASK_ADDR_CLRMASK (0x00000003)
|
||||
#define PSB_2D_MASK_ADDR_SHIFT (2)
|
||||
#define PSB_2D_MASK_ADDR_ALIGNSHIFT (2)
|
||||
|
||||
/*
|
||||
* Source Palette (PSB_2D_SRC_PAL_BH)
|
||||
*/
|
||||
|
||||
#define PSB_2D_SRCPAL_ADDR_SHIFT (0)
|
||||
#define PSB_2D_SRCPAL_ADDR_CLRMASK (0xF0000007)
|
||||
#define PSB_2D_SRCPAL_ADDR_MASK (0x0FFFFFF8)
|
||||
#define PSB_2D_SRCPAL_BYTEALIGN (1024)
|
||||
#define PSB_2D_SRCPAL_ADDR_SHIFT (0)
|
||||
#define PSB_2D_SRCPAL_ADDR_CLRMASK (0xF0000007)
|
||||
#define PSB_2D_SRCPAL_ADDR_MASK (0x0FFFFFF8)
|
||||
#define PSB_2D_SRCPAL_BYTEALIGN (1024)
|
||||
|
||||
/*
|
||||
* Pattern Palette (PSB_2D_PAT_PAL_BH)
|
||||
*/
|
||||
|
||||
#define PSB_2D_PATPAL_ADDR_SHIFT (0)
|
||||
#define PSB_2D_PATPAL_ADDR_CLRMASK (0xF0000007)
|
||||
#define PSB_2D_PATPAL_ADDR_MASK (0x0FFFFFF8)
|
||||
#define PSB_2D_PATPAL_BYTEALIGN (1024)
|
||||
#define PSB_2D_PATPAL_ADDR_SHIFT (0)
|
||||
#define PSB_2D_PATPAL_ADDR_CLRMASK (0xF0000007)
|
||||
#define PSB_2D_PATPAL_ADDR_MASK (0x0FFFFFF8)
|
||||
#define PSB_2D_PATPAL_BYTEALIGN (1024)
|
||||
|
||||
/*
|
||||
* Rop3 Codes (2 LS bytes)
|
||||
*/
|
||||
|
||||
#define PSB_2D_ROP3_SRCCOPY (0xCCCC)
|
||||
#define PSB_2D_ROP3_PATCOPY (0xF0F0)
|
||||
#define PSB_2D_ROP3_WHITENESS (0xFFFF)
|
||||
#define PSB_2D_ROP3_BLACKNESS (0x0000)
|
||||
#define PSB_2D_ROP3_SRC (0xCC)
|
||||
#define PSB_2D_ROP3_PAT (0xF0)
|
||||
#define PSB_2D_ROP3_DST (0xAA)
|
||||
|
||||
#define PSB_2D_ROP3_SRCCOPY (0xCCCC)
|
||||
#define PSB_2D_ROP3_PATCOPY (0xF0F0)
|
||||
#define PSB_2D_ROP3_WHITENESS (0xFFFF)
|
||||
#define PSB_2D_ROP3_BLACKNESS (0x0000)
|
||||
#define PSB_2D_ROP3_SRC (0xCC)
|
||||
#define PSB_2D_ROP3_PAT (0xF0)
|
||||
#define PSB_2D_ROP3_DST (0xAA)
|
||||
|
||||
/*
|
||||
* Sizes.
|
||||
*/
|
||||
|
||||
#define PSB_SCENE_HW_COOKIE_SIZE 16
|
||||
#define PSB_TA_MEM_HW_COOKIE_SIZE 16
|
||||
#define PSB_SCENE_HW_COOKIE_SIZE 16
|
||||
#define PSB_TA_MEM_HW_COOKIE_SIZE 16
|
||||
|
||||
/*
|
||||
* Scene stuff.
|
||||
*/
|
||||
|
||||
#define PSB_NUM_HW_SCENES 2
|
||||
#define PSB_NUM_HW_SCENES 2
|
||||
|
||||
/*
|
||||
* Scheduler completion actions.
|
||||
*/
|
||||
|
||||
#define PSB_RASTER_BLOCK 0
|
||||
#define PSB_RASTER 1
|
||||
#define PSB_RETURN 2
|
||||
#define PSB_TA 3
|
||||
#define PSB_RASTER_BLOCK 0
|
||||
#define PSB_RASTER 1
|
||||
#define PSB_RETURN 2
|
||||
#define PSB_TA 3
|
||||
|
||||
/* Power management */
|
||||
#define PSB_PUNIT_PORT 0x04
|
||||
#define PSB_OSPMBA 0x78
|
||||
#define PSB_APMBA 0x7a
|
||||
#define PSB_APM_CMD 0x0
|
||||
#define PSB_APM_STS 0x04
|
||||
#define PSB_PWRGT_VID_ENC_MASK 0x30
|
||||
#define PSB_PWRGT_VID_DEC_MASK 0xc
|
||||
#define PSB_PWRGT_GL3_MASK 0xc0
|
||||
|
||||
/*Power management*/
|
||||
#define PSB_PUNIT_PORT 0x04
|
||||
#define PSB_OSPMBA 0x78
|
||||
#define PSB_APMBA 0x7a
|
||||
#define PSB_APM_CMD 0x0
|
||||
#define PSB_APM_STS 0x04
|
||||
#define PSB_PWRGT_VID_ENC_MASK 0x30
|
||||
#define PSB_PWRGT_VID_DEC_MASK 0xc
|
||||
#define PSB_PWRGT_GL3_MASK 0xc0
|
||||
|
||||
#define PSB_PM_SSC 0x20
|
||||
#define PSB_PM_SSS 0x30
|
||||
#define PSB_PWRGT_DISPLAY_MASK 0xc /*on a different BA than video/gfx*/
|
||||
#define MDFLD_PWRGT_DISPLAY_A_CNTR 0x0000000c
|
||||
#define MDFLD_PWRGT_DISPLAY_B_CNTR 0x0000c000
|
||||
#define MDFLD_PWRGT_DISPLAY_C_CNTR 0x00030000
|
||||
#define MDFLD_PWRGT_DISP_MIPI_CNTR 0x000c0000
|
||||
#define MDFLD_PWRGT_DISPLAY_CNTR (MDFLD_PWRGT_DISPLAY_A_CNTR | MDFLD_PWRGT_DISPLAY_B_CNTR | MDFLD_PWRGT_DISPLAY_C_CNTR | MDFLD_PWRGT_DISP_MIPI_CNTR)// 0x000fc00c
|
||||
#define PSB_PM_SSC 0x20
|
||||
#define PSB_PM_SSS 0x30
|
||||
#define PSB_PWRGT_DISPLAY_MASK 0xc /*on a different BA than video/gfx*/
|
||||
#define MDFLD_PWRGT_DISPLAY_A_CNTR 0x0000000c
|
||||
#define MDFLD_PWRGT_DISPLAY_B_CNTR 0x0000c000
|
||||
#define MDFLD_PWRGT_DISPLAY_C_CNTR 0x00030000
|
||||
#define MDFLD_PWRGT_DISP_MIPI_CNTR 0x000c0000
|
||||
#define MDFLD_PWRGT_DISPLAY_CNTR (MDFLD_PWRGT_DISPLAY_A_CNTR | MDFLD_PWRGT_DISPLAY_B_CNTR | MDFLD_PWRGT_DISPLAY_C_CNTR | MDFLD_PWRGT_DISP_MIPI_CNTR) /* 0x000fc00c */
|
||||
/* Display SSS register bits are different in A0 vs. B0 */
|
||||
#define PSB_PWRGT_GFX_MASK 0x3
|
||||
#define MDFLD_PWRGT_DISPLAY_A_STS 0x000000c0
|
||||
#define MDFLD_PWRGT_DISPLAY_B_STS 0x00000300
|
||||
#define MDFLD_PWRGT_DISPLAY_C_STS 0x00000c00
|
||||
#define PSB_PWRGT_GFX_MASK_B0 0xc3
|
||||
#define PSB_PWRGT_GFX_MASK 0x3
|
||||
#define MDFLD_PWRGT_DISPLAY_A_STS 0x000000c0
|
||||
#define MDFLD_PWRGT_DISPLAY_B_STS 0x00000300
|
||||
#define MDFLD_PWRGT_DISPLAY_C_STS 0x00000c00
|
||||
#define PSB_PWRGT_GFX_MASK_B0 0xc3
|
||||
#define MDFLD_PWRGT_DISPLAY_A_STS_B0 0x0000000c
|
||||
#define MDFLD_PWRGT_DISPLAY_B_STS_B0 0x0000c000
|
||||
#define MDFLD_PWRGT_DISPLAY_C_STS_B0 0x00030000
|
||||
#define MDFLD_PWRGT_DISP_MIPI_STS 0x000c0000
|
||||
#define MDFLD_PWRGT_DISPLAY_STS_A0 (MDFLD_PWRGT_DISPLAY_A_STS | MDFLD_PWRGT_DISPLAY_B_STS | MDFLD_PWRGT_DISPLAY_C_STS | MDFLD_PWRGT_DISP_MIPI_STS)// 0x000fc00c
|
||||
#define MDFLD_PWRGT_DISPLAY_STS_B0 (MDFLD_PWRGT_DISPLAY_A_STS_B0 | MDFLD_PWRGT_DISPLAY_B_STS_B0 | MDFLD_PWRGT_DISPLAY_C_STS_B0 | MDFLD_PWRGT_DISP_MIPI_STS)// 0x000fc00c
|
||||
#define MDFLD_PWRGT_DISPLAY_B_STS_B0 0x0000c000
|
||||
#define MDFLD_PWRGT_DISPLAY_C_STS_B0 0x00030000
|
||||
#define MDFLD_PWRGT_DISP_MIPI_STS 0x000c0000
|
||||
#define MDFLD_PWRGT_DISPLAY_STS_A0 (MDFLD_PWRGT_DISPLAY_A_STS | MDFLD_PWRGT_DISPLAY_B_STS | MDFLD_PWRGT_DISPLAY_C_STS | MDFLD_PWRGT_DISP_MIPI_STS) /* 0x000fc00c */
|
||||
#define MDFLD_PWRGT_DISPLAY_STS_B0 (MDFLD_PWRGT_DISPLAY_A_STS_B0 | MDFLD_PWRGT_DISPLAY_B_STS_B0 | MDFLD_PWRGT_DISPLAY_C_STS_B0 | MDFLD_PWRGT_DISP_MIPI_STS) /* 0x000fc00c */
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user