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[ARM] orion5x: accelerate NAND on the TS-78xx
The NAND supports 32bit reads and writes so lets stop shunting 8bit chunks across the bus. Doing a dumb 'dd' benchmark, this increases performance roughly like so: * read: 1.3MB/s to 3.4MB/s * write: 614kB/s to 882kB/s Signed-off-by: Alexander Clouter <alex@digriz.org.uk> Signed-off-by: Nicolas Pitre <nico@fluxnic.net>
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@ -191,6 +191,60 @@ static int ts78xx_ts_nand_dev_ready(struct mtd_info *mtd)
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return readb(TS_NAND_CTRL) & 0x20;
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return readb(TS_NAND_CTRL) & 0x20;
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}
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}
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static void ts78xx_ts_nand_write_buf(struct mtd_info *mtd,
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const uint8_t *buf, int len)
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{
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struct nand_chip *chip = mtd->priv;
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void __iomem *io_base = chip->IO_ADDR_W;
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unsigned long off = ((unsigned long)buf & 3);
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int sz;
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if (off) {
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sz = min(4 - off, len);
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writesb(io_base, buf, sz);
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buf += sz;
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len -= sz;
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}
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sz = len >> 2;
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if (sz) {
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u32 *buf32 = (u32 *)buf;
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writesl(io_base, buf32, sz);
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buf += sz << 2;
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len -= sz << 2;
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}
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if (len)
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writesb(io_base, buf, len);
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}
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static void ts78xx_ts_nand_read_buf(struct mtd_info *mtd,
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uint8_t *buf, int len)
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{
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struct nand_chip *chip = mtd->priv;
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void __iomem *io_base = chip->IO_ADDR_R;
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unsigned long off = ((unsigned long)buf & 3);
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int sz;
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if (off) {
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sz = min(4 - off, len);
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readsb(io_base, buf, sz);
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buf += sz;
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len -= sz;
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}
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sz = len >> 2;
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if (sz) {
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u32 *buf32 = (u32 *)buf;
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readsl(io_base, buf32, sz);
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buf += sz << 2;
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len -= sz << 2;
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}
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if (len)
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readsb(io_base, buf, len);
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}
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const char *ts_nand_part_probes[] = { "cmdlinepart", NULL };
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const char *ts_nand_part_probes[] = { "cmdlinepart", NULL };
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static struct mtd_partition ts78xx_ts_nand_parts[] = {
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static struct mtd_partition ts78xx_ts_nand_parts[] = {
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@ -233,6 +287,8 @@ static struct platform_nand_data ts78xx_ts_nand_data = {
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*/
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*/
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.cmd_ctrl = ts78xx_ts_nand_cmd_ctrl,
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.cmd_ctrl = ts78xx_ts_nand_cmd_ctrl,
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.dev_ready = ts78xx_ts_nand_dev_ready,
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.dev_ready = ts78xx_ts_nand_dev_ready,
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.write_buf = ts78xx_ts_nand_write_buf,
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.read_buf = ts78xx_ts_nand_read_buf,
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},
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},
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};
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};
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