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drm: sti: add Mixer
Mixer hardware IP is responsible of mixing the different inputs layers. Z-order is managed by the mixer. We could 2 mixers: one for main path and one for auxillary path Mixers are part of Compositor hardware block Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Reviewed-by: Rob Clark <robdclark@gmail.com>
This commit is contained in:
Benjamin Gaignard
parent
cfd8d744fe
commit
e21e21939c
@ -1,4 +1,5 @@
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sticompositor-y := \
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sti_mixer.o \
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sti_gdp.o \
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sti_vid.o
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@ -12,4 +13,4 @@ obj-$(CONFIG_DRM_STI) = \
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stihdmi.o \
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sti_hda.o \
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sti_tvout.o \
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sticompositor.o
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sticompositor.o
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243
drivers/gpu/drm/sti/sti_mixer.c
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243
drivers/gpu/drm/sti/sti_mixer.c
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@ -0,0 +1,243 @@
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/*
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* Copyright (C) STMicroelectronics SA 2014
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* Authors: Benjamin Gaignard <benjamin.gaignard@st.com>
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* Fabien Dessenne <fabien.dessenne@st.com>
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* for STMicroelectronics.
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* License terms: GNU General Public License (GPL), version 2
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*/
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#include "sti_mixer.h"
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#include "sti_vtg.h"
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/* Identity: G=Y , B=Cb , R=Cr */
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static const u32 mixerColorSpaceMatIdentity[] = {
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0x10000000, 0x00000000, 0x10000000, 0x00001000,
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0x00000000, 0x00000000, 0x00000000, 0x00000000
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};
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/* regs offset */
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#define GAM_MIXER_CTL 0x00
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#define GAM_MIXER_BKC 0x04
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#define GAM_MIXER_BCO 0x0C
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#define GAM_MIXER_BCS 0x10
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#define GAM_MIXER_AVO 0x28
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#define GAM_MIXER_AVS 0x2C
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#define GAM_MIXER_CRB 0x34
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#define GAM_MIXER_ACT 0x38
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#define GAM_MIXER_MBP 0x3C
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#define GAM_MIXER_MX0 0x80
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/* id for depth of CRB reg */
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#define GAM_DEPTH_VID0_ID 1
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#define GAM_DEPTH_VID1_ID 2
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#define GAM_DEPTH_GDP0_ID 3
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#define GAM_DEPTH_GDP1_ID 4
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#define GAM_DEPTH_GDP2_ID 5
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#define GAM_DEPTH_GDP3_ID 6
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#define GAM_DEPTH_MASK_ID 7
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/* mask in CTL reg */
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#define GAM_CTL_BACK_MASK BIT(0)
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#define GAM_CTL_VID0_MASK BIT(1)
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#define GAM_CTL_VID1_MASK BIT(2)
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#define GAM_CTL_GDP0_MASK BIT(3)
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#define GAM_CTL_GDP1_MASK BIT(4)
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#define GAM_CTL_GDP2_MASK BIT(5)
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#define GAM_CTL_GDP3_MASK BIT(6)
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const char *sti_mixer_to_str(struct sti_mixer *mixer)
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{
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switch (mixer->id) {
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case STI_MIXER_MAIN:
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return "MAIN_MIXER";
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case STI_MIXER_AUX:
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return "AUX_MIXER";
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default:
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return "<UNKNOWN MIXER>";
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}
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}
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static inline u32 sti_mixer_reg_read(struct sti_mixer *mixer, u32 reg_id)
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{
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return readl(mixer->regs + reg_id);
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}
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static inline void sti_mixer_reg_write(struct sti_mixer *mixer,
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u32 reg_id, u32 val)
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{
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writel(val, mixer->regs + reg_id);
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}
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void sti_mixer_set_background_status(struct sti_mixer *mixer, bool enable)
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{
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u32 val = sti_mixer_reg_read(mixer, GAM_MIXER_CTL);
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val &= ~GAM_CTL_BACK_MASK;
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val |= enable;
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sti_mixer_reg_write(mixer, GAM_MIXER_CTL, val);
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}
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static void sti_mixer_set_background_color(struct sti_mixer *mixer,
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u8 red, u8 green, u8 blue)
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{
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u32 val = (red << 16) | (green << 8) | blue;
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sti_mixer_reg_write(mixer, GAM_MIXER_BKC, val);
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}
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static void sti_mixer_set_background_area(struct sti_mixer *mixer,
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struct drm_display_mode *mode)
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{
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u32 ydo, xdo, yds, xds;
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ydo = sti_vtg_get_line_number(*mode, 0);
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yds = sti_vtg_get_line_number(*mode, mode->vdisplay - 1);
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xdo = sti_vtg_get_pixel_number(*mode, 0);
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xds = sti_vtg_get_pixel_number(*mode, mode->hdisplay - 1);
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sti_mixer_reg_write(mixer, GAM_MIXER_BCO, ydo << 16 | xdo);
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sti_mixer_reg_write(mixer, GAM_MIXER_BCS, yds << 16 | xds);
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}
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int sti_mixer_set_layer_depth(struct sti_mixer *mixer, struct sti_layer *layer)
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{
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int layer_id = 0, depth = layer->zorder;
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u32 mask, val;
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if (depth >= GAM_MIXER_NB_DEPTH_LEVEL)
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return 1;
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switch (layer->desc) {
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case STI_GDP_0:
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layer_id = GAM_DEPTH_GDP0_ID;
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break;
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case STI_GDP_1:
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layer_id = GAM_DEPTH_GDP1_ID;
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break;
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case STI_GDP_2:
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layer_id = GAM_DEPTH_GDP2_ID;
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break;
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case STI_GDP_3:
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layer_id = GAM_DEPTH_GDP3_ID;
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break;
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case STI_VID_0:
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layer_id = GAM_DEPTH_VID0_ID;
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break;
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case STI_VID_1:
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layer_id = GAM_DEPTH_VID1_ID;
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break;
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default:
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DRM_ERROR("Unknown layer %d\n", layer->desc);
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return 1;
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}
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mask = GAM_DEPTH_MASK_ID << (3 * depth);
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layer_id = layer_id << (3 * depth);
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dev_dbg(mixer->dev, "GAM_MIXER_CRB val 0x%x mask 0x%x\n",
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layer_id, mask);
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val = sti_mixer_reg_read(mixer, GAM_MIXER_CRB);
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val &= ~mask;
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val |= layer_id;
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sti_mixer_reg_write(mixer, GAM_MIXER_CRB, val);
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dev_dbg(mixer->dev, "Read GAM_MIXER_CRB 0x%x\n",
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sti_mixer_reg_read(mixer, GAM_MIXER_CRB));
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return 0;
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}
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int sti_mixer_active_video_area(struct sti_mixer *mixer,
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struct drm_display_mode *mode)
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{
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u32 ydo, xdo, yds, xds;
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ydo = sti_vtg_get_line_number(*mode, 0);
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yds = sti_vtg_get_line_number(*mode, mode->vdisplay - 1);
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xdo = sti_vtg_get_pixel_number(*mode, 0);
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xds = sti_vtg_get_pixel_number(*mode, mode->hdisplay - 1);
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DRM_DEBUG_DRIVER("%s active video area xdo:%d ydo:%d xds:%d yds:%d\n",
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sti_mixer_to_str(mixer), xdo, ydo, xds, yds);
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sti_mixer_reg_write(mixer, GAM_MIXER_AVO, ydo << 16 | xdo);
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sti_mixer_reg_write(mixer, GAM_MIXER_AVS, yds << 16 | xds);
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sti_mixer_set_background_color(mixer, 0xFF, 0, 0);
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sti_mixer_set_background_area(mixer, mode);
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sti_mixer_set_background_status(mixer, true);
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return 0;
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}
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static u32 sti_mixer_get_layer_mask(struct sti_layer *layer)
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{
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switch (layer->desc) {
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case STI_BACK:
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return GAM_CTL_BACK_MASK;
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case STI_GDP_0:
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return GAM_CTL_GDP0_MASK;
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case STI_GDP_1:
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return GAM_CTL_GDP1_MASK;
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case STI_GDP_2:
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return GAM_CTL_GDP2_MASK;
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case STI_GDP_3:
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return GAM_CTL_GDP3_MASK;
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case STI_VID_0:
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return GAM_CTL_VID0_MASK;
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case STI_VID_1:
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return GAM_CTL_VID1_MASK;
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default:
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return 0;
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}
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}
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int sti_mixer_set_layer_status(struct sti_mixer *mixer,
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struct sti_layer *layer, bool status)
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{
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u32 mask, val;
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mask = sti_mixer_get_layer_mask(layer);
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if (!mask) {
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DRM_ERROR("Can not find layer mask\n");
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return -EINVAL;
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}
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val = sti_mixer_reg_read(mixer, GAM_MIXER_CTL);
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val &= ~mask;
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val |= status ? mask : 0;
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sti_mixer_reg_write(mixer, GAM_MIXER_CTL, val);
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return 0;
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}
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void sti_mixer_set_matrix(struct sti_mixer *mixer)
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{
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unsigned int i;
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for (i = 0; i < ARRAY_SIZE(mixerColorSpaceMatIdentity); i++)
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sti_mixer_reg_write(mixer, GAM_MIXER_MX0 + (i * 4),
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mixerColorSpaceMatIdentity[i]);
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}
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struct sti_mixer *sti_mixer_create(struct device *dev, int id,
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void __iomem *baseaddr)
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{
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struct sti_mixer *mixer = devm_kzalloc(dev, sizeof(*mixer), GFP_KERNEL);
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struct device_node *np = dev->of_node;
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dev_dbg(dev, "%s\n", __func__);
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if (!mixer) {
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DRM_ERROR("Failed to allocated memory for mixer\n");
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return NULL;
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}
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mixer->regs = baseaddr;
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mixer->dev = dev;
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mixer->id = id;
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if (of_device_is_compatible(np, "st,stih416-compositor"))
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sti_mixer_set_matrix(mixer);
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DRM_DEBUG_DRIVER("%s created. Regs=%p\n",
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sti_mixer_to_str(mixer), mixer->regs);
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return mixer;
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}
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54
drivers/gpu/drm/sti/sti_mixer.h
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54
drivers/gpu/drm/sti/sti_mixer.h
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@ -0,0 +1,54 @@
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/*
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* Copyright (C) STMicroelectronics SA 2014
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* Authors: Benjamin Gaignard <benjamin.gaignard@st.com>
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* Fabien Dessenne <fabien.dessenne@st.com>
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* for STMicroelectronics.
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* License terms: GNU General Public License (GPL), version 2
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*/
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#ifndef _STI_MIXER_H_
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#define _STI_MIXER_H_
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#include <drm/drmP.h>
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#include "sti_layer.h"
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#define to_sti_mixer(x) container_of(x, struct sti_mixer, drm_crtc)
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/**
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* STI Mixer subdevice structure
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*
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* @dev: driver device
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* @regs: mixer registers
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* @id: id of the mixer
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* @drm_crtc: crtc object link to the mixer
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* @pending_event: set if a flip event is pending on crtc
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*/
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struct sti_mixer {
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struct device *dev;
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void __iomem *regs;
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int id;
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struct drm_crtc drm_crtc;
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struct drm_pending_vblank_event *pending_event;
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};
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const char *sti_mixer_to_str(struct sti_mixer *mixer);
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struct sti_mixer *sti_mixer_create(struct device *dev, int id,
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void __iomem *baseaddr);
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int sti_mixer_set_layer_status(struct sti_mixer *mixer,
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struct sti_layer *layer, bool status);
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int sti_mixer_set_layer_depth(struct sti_mixer *mixer, struct sti_layer *layer);
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int sti_mixer_active_video_area(struct sti_mixer *mixer,
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struct drm_display_mode *mode);
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void sti_mixer_set_background_status(struct sti_mixer *mixer, bool enable);
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/* depth in Cross-bar control = z order */
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#define GAM_MIXER_NB_DEPTH_LEVEL 7
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#define STI_MIXER_MAIN 0
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#define STI_MIXER_AUX 1
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#endif
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