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powerpc/85xx: P3041DS - change espi input-clock from 40MHz to 35MHz

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Default CoreNet Coherency Bus (CCB) frequency on P3041 is 750MHz, but espi
cannot work at 40MHz with this CCB frequency, so we need to slow down the
clock rate of espi to 35MHz to make it work stable at the CCB frequency.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Shaohui Xie 2012-07-17 15:18:31 +08:00 committed by Kumar Gala
parent 771e6089e3
commit e1bd5d8bc1
1 changed files with 1 additions and 1 deletions
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2
arch/powerpc/boot/dts/p3041ds.dts
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@ -58,7 +58,7 @@
#size-cells = <1>;
compatible = "spansion,s25sl12801";
reg = <0>;
spi-max-frequency = <40000000>; /* input clock */
spi-max-frequency = <35000000>; /* input clock */
partition@u-boot {
label = "u-boot";
reg = <0x00000000 0x00100000>;