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[PATCH] tpm: replace odd LPC init function
Realized the tpm_lpc_init function isn't really necessary. Replaced it with vendor specific logic to find out the address the BIOS mapped the TPM to. This patch removes the tpm_lpc_init function, enums associated with it and calls to it. The patch also implements the replacement functionality. Signed-off-by: Kylene Hall <kjhall@us.ibm.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
This commit is contained in:
Kylene Hall
Linus Torvalds
parent
a6df7da8f7
commit
e1a23c6671
@ -35,25 +35,6 @@ enum tpm_const {
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TPM_NUM_MASK_ENTRIES = TPM_NUM_DEVICES / (8 * sizeof(int))
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};
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/* PCI configuration addresses */
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enum tpm_pci_config_addr {
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PCI_GEN_PMCON_1 = 0xA0,
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PCI_GEN1_DEC = 0xE4,
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PCI_LPC_EN = 0xE6,
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PCI_GEN2_DEC = 0xEC
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};
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enum tpm_config {
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TPM_LOCK_REG = 0x0D,
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TPM_INTERUPT_REG = 0x0A,
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TPM_BASE_ADDR_LO = 0x08,
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TPM_BASE_ADDR_HI = 0x09,
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TPM_UNLOCK_VALUE = 0x55,
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TPM_LOCK_VALUE = 0xAA,
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TPM_DISABLE_INTERUPT_VALUE = 0x00
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};
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static LIST_HEAD(tpm_chip_list);
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static DEFINE_SPINLOCK(driver_lock);
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static int dev_mask[TPM_NUM_MASK_ENTRIES];
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@ -68,73 +49,6 @@ static void user_reader_timeout(unsigned long ptr)
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up(&chip->buffer_mutex);
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}
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/*
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* Initialize the LPC bus and enable the TPM ports
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*/
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int tpm_lpc_bus_init(struct pci_dev *pci_dev, u16 base)
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{
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u32 lpcenable, tmp;
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int is_lpcm = 0;
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switch (pci_dev->vendor) {
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case PCI_VENDOR_ID_INTEL:
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switch (pci_dev->device) {
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case PCI_DEVICE_ID_INTEL_82801CA_12:
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case PCI_DEVICE_ID_INTEL_82801DB_12:
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is_lpcm = 1;
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break;
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}
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/* init ICH (enable LPC) */
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pci_read_config_dword(pci_dev, PCI_GEN1_DEC, &lpcenable);
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lpcenable |= 0x20000000;
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pci_write_config_dword(pci_dev, PCI_GEN1_DEC, lpcenable);
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if (is_lpcm) {
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pci_read_config_dword(pci_dev, PCI_GEN1_DEC,
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&lpcenable);
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if ((lpcenable & 0x20000000) == 0) {
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dev_err(&pci_dev->dev,
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"cannot enable LPC\n");
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return -ENODEV;
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}
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}
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/* initialize TPM registers */
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pci_read_config_dword(pci_dev, PCI_GEN2_DEC, &tmp);
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if (!is_lpcm)
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tmp = (tmp & 0xFFFF0000) | (base & 0xFFF0);
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else
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tmp =
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(tmp & 0xFFFF0000) | (base & 0xFFF0) |
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0x00000001;
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pci_write_config_dword(pci_dev, PCI_GEN2_DEC, tmp);
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if (is_lpcm) {
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pci_read_config_dword(pci_dev, PCI_GEN_PMCON_1,
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&tmp);
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tmp |= 0x00000004; /* enable CLKRUN */
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pci_write_config_dword(pci_dev, PCI_GEN_PMCON_1,
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tmp);
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}
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break;
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case PCI_VENDOR_ID_AMD:
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/* nothing yet */
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break;
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}
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tpm_write_index(TPM_LOCK_REG, TPM_UNLOCK_VALUE);
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tpm_write_index(TPM_INTERUPT_REG, TPM_DISABLE_INTERUPT_VALUE);
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tpm_write_index(TPM_BASE_ADDR_LO, base);
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tpm_write_index(TPM_BASE_ADDR_HI, (base & 0xFF00) >> 8);
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tpm_write_index(TPM_LOCK_REG, TPM_LOCK_VALUE);
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return 0;
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}
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EXPORT_SYMBOL_GPL(tpm_lpc_bus_init);
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/*
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* Internal kernel interface to transmit TPM commands
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*/
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@ -586,10 +500,6 @@ int tpm_pm_resume(struct pci_dev *pci_dev)
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if (chip == NULL)
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return -ENODEV;
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spin_lock(&driver_lock);
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tpm_lpc_bus_init(pci_dev, chip->vendor->base);
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spin_unlock(&driver_lock);
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return 0;
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}
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@ -91,8 +91,6 @@ static inline void tpm_write_index(int index, int value)
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outb(value & 0xFF, TPM_DATA);
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}
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extern int tpm_lpc_bus_init(struct pci_dev *, u16);
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extern int tpm_register_hardware(struct pci_dev *,
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struct tpm_vendor_specific *);
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extern int tpm_open(struct inode *, struct file *);
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@ -22,8 +22,9 @@
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#include "tpm.h"
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/* Atmel definitions */
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enum tpm_atmel_addr{
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TPM_ATML_BASE = 0x400
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enum tpm_atmel_addr {
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TPM_ATMEL_BASE_ADDR_LO = 0x08,
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TPM_ATMEL_BASE_ADDR_HI = 0x09
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};
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/* write status bits */
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@ -148,7 +149,6 @@ static struct tpm_vendor_specific tpm_atmel = {
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.req_complete_mask = ATML_STATUS_BUSY | ATML_STATUS_DATA_AVAIL,
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.req_complete_val = ATML_STATUS_DATA_AVAIL,
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.req_canceled = ATML_STATUS_READY,
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.base = TPM_ATML_BASE,
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.attr_group = &atmel_attr_grp,
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.miscdev = { .fops = &atmel_ops, },
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};
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@ -158,14 +158,16 @@ static int __devinit tpm_atml_init(struct pci_dev *pci_dev,
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{
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u8 version[4];
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int rc = 0;
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int lo, hi;
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if (pci_enable_device(pci_dev))
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return -EIO;
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if (tpm_lpc_bus_init(pci_dev, TPM_ATML_BASE)) {
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rc = -ENODEV;
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goto out_err;
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}
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lo = tpm_read_index( TPM_ATMEL_BASE_ADDR_LO );
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hi = tpm_read_index( TPM_ATMEL_BASE_ADDR_HI );
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tpm_atmel.base = (hi<<8)|lo;
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dev_dbg( &pci_dev->dev, "Operating with base: 0x%x\n", tpm_atmel.base);
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/* verify that it is an Atmel part */
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if (tpm_read_index(4) != 'A' || tpm_read_index(5) != 'T'
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@ -22,9 +22,13 @@
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#include "tpm.h"
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/* National definitions */
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enum tpm_nsc_addr {
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enum tpm_nsc_addr{
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TPM_NSC_BASE = 0x360,
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TPM_NSC_IRQ = 0x07
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TPM_NSC_IRQ = 0x07,
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TPM_NSC_BASE0_HI = 0x60,
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TPM_NSC_BASE0_LO = 0x61,
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TPM_NSC_BASE1_HI = 0x62,
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TPM_NSC_BASE1_LO = 0x63
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};
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enum tpm_nsc_index {
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@ -44,7 +48,7 @@ enum tpm_nsc_status_loc {
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};
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/* status bits */
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enum tpm_nsc_status{
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enum tpm_nsc_status {
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NSC_STATUS_OBF = 0x01, /* output buffer full */
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NSC_STATUS_IBF = 0x02, /* input buffer full */
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NSC_STATUS_F0 = 0x04, /* F0 */
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@ -246,7 +250,6 @@ static struct tpm_vendor_specific tpm_nsc = {
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.req_complete_mask = NSC_STATUS_OBF,
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.req_complete_val = NSC_STATUS_OBF,
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.req_canceled = NSC_STATUS_RDY,
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.base = TPM_NSC_BASE,
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.attr_group = &nsc_attr_grp,
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.miscdev = { .fops = &nsc_ops, },
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};
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@ -255,15 +258,16 @@ static int __devinit tpm_nsc_init(struct pci_dev *pci_dev,
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const struct pci_device_id *pci_id)
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{
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int rc = 0;
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int lo, hi;
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hi = tpm_read_index(TPM_NSC_BASE0_HI);
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lo = tpm_read_index(TPM_NSC_BASE0_LO);
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tpm_nsc.base = (hi<<8) | lo;
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if (pci_enable_device(pci_dev))
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return -EIO;
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if (tpm_lpc_bus_init(pci_dev, TPM_NSC_BASE)) {
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rc = -ENODEV;
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goto out_err;
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}
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/* verify that it is a National part (SID) */
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if (tpm_read_index(NSC_SID_INDEX) != 0xEF) {
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rc = -ENODEV;
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