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Qualcomm DeviceTree updates for v5.17

Browse Source 
To SDX55 this introduces the description of the IPA, PCIe PHY and PCIe
 endpoint controller, as well as enables these for the FN960 device.
 
 The SDX65 5G platform is introduced, currently with definitions
 necessary to boot to a shell.
 
 The undocumented property "input-name" is dropped throughout the dts
 files, dwc3 nodes throughout gains more specific compatibles and lastly
 building of the Dragonboard 410c DTB on ARM32 is enabled, in addition to
 its normal operation in 64-bit mode.
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Merge tag 'qcom-dts-for-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/dt

Qualcomm DeviceTree updates for v5.17

To SDX55 this introduces the description of the IPA, PCIe PHY and PCIe
endpoint controller, as well as enables these for the FN960 device.

The SDX65 5G platform is introduced, currently with definitions
necessary to boot to a shell.

The undocumented property "input-name" is dropped throughout the dts
files, dwc3 nodes throughout gains more specific compatibles and lastly
building of the Dragonboard 410c DTB on ARM32 is enabled, in addition to
its normal operation in 64-bit mode.

* tag 'qcom-dts-for-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux:
  ARM: dts: qcom: Drop input-name property
  ARM: dts: qcom: sdx65: Add pincontrol node
  ARM: dts: qcom: Add SDX65 platform and MTP board support
  dt-bindings: arm: qcom: Document SDX65 platform and boards
  dt-bindings: clock: Add SDX65 GCC clock bindings
  ARM: dts: qcom: Build apq8016-sbc/DragonBoard 410c DTB on ARM32
  ARM: dts: qcom: sdx55-t55: Enable IPA
  ARM: dts: qcom: sdx55-fn980: Enable IPA
  ARM: dts: qcom: sdx55-fn980: Enable PCIe EP
  ARM: dts: qcom: sdx55: Add support for PCIe EP
  ARM: dts: qcom: sdx55-fn980: Enable PCIE0 PHY
  ARM: dts: qcom: sdx55: Add support for PCIe PHY
  ARM: dts: qcom: update USB nodes with new platform specific compatible

Link: https://lore.kernel.org/r/20211221042154.3621955-1-bjorn.andersson@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2021-12-21 15:37:20 +01:00
commit dfdded9b0b
19 changed files with 609 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
Documentation/devicetree/bindings/arm/qcom.yaml
View File

@ -48,6 +48,7 @@ description: |
sdx65
sm7225
sm8150
sdx65
sm8250
sm8350
@ -224,6 +225,11 @@ properties:
- qcom,sdx65-mtp
- const: qcom,sdx65
- items:
- enum:
- qcom,sdx65-mtp
- const: qcom,sdx65
- items:
- enum:
- qcom,ipq6018-cp01

80
Documentation/devicetree/bindings/clock/qcom,gcc-sdx65.yaml Normal file
View File

@ -0,0 +1,80 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,gcc-sdx65.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Binding for SDX65
maintainers:
- Vamsi krishna Lanka <quic_vamslank@quicinc.com>
description: |
Qualcomm global clock control module which supports the clocks, resets and
power domains on SDX65
See also:
- dt-bindings/clock/qcom,gcc-sdx65.h
properties:
compatible:
const: qcom,gcc-sdx65
reg:
maxItems: 1
clocks:
items:
- description: Board XO source
- description: Board active XO source
- description: Sleep clock source
- description: PCIE Pipe clock source
- description: USB3 phy wrapper pipe clock source
- description: PLL test clock source (Optional clock)
minItems: 5
clock-names:
items:
- const: bi_tcxo
- const: bi_tcxo_ao
- const: sleep_clk
- const: pcie_pipe_clk
- const: usb3_phy_wrapper_gcc_usb30_pipe_clk
- const: core_bi_pll_test_se # Optional clock
minItems: 5
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
required:
- compatible
- reg
- clocks
- clock-names
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
clock-controller@100000 {
compatible = "qcom,gcc-sdx65";
reg = <0x100000 0x1f7400>;
clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,
<&pcie_pipe_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>, <&pll_test_clk>;
clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
"pcie_pipe_clk", "usb3_phy_wrapper_gcc_usb30_pipe_clk", "core_bi_pll_test_se";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...

4
arch/arm/boot/dts/Makefile
View File

@ -966,6 +966,7 @@ dtb-$(CONFIG_ARCH_OXNAS) += \
ox810se-wd-mbwe.dtb \
ox820-cloudengines-pogoplug-series-3.dtb
dtb-$(CONFIG_ARCH_QCOM) += \
qcom-apq8016-sbc.dtb \
qcom-apq8026-lg-lenok.dtb \
qcom-apq8060-dragonboard.dtb \
qcom-apq8064-cm-qs600.dtb \
@ -998,7 +999,8 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-mdm9615-wp8548-mangoh-green.dtb \
qcom-sdx55-mtp.dtb \
qcom-sdx55-t55.dtb \
qcom-sdx55-telit-fn980-tlb.dtb
qcom-sdx55-telit-fn980-tlb.dtb \
qcom-sdx65-mtp.dtb
dtb-$(CONFIG_ARCH_RDA) += \
rda8810pl-orangepi-2g-iot.dtb \
rda8810pl-orangepi-i96.dtb

2
arch/arm/boot/dts/qcom-apq8016-sbc.dts Normal file
View File

@ -0,0 +1,2 @@
// SPDX-License-Identifier: GPL-2.0-only
#include "arm64/qcom/apq8016-sbc.dts"

1
arch/arm/boot/dts/qcom-apq8064-sony-xperia-yuga.dts
View File

@ -19,7 +19,6 @@
gpio-keys {
compatible = "gpio-keys";
input-name = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&gpio_keys_pin_a>;

4
arch/arm/boot/dts/qcom-ipq4019.dtsi
View File

@ -637,7 +637,7 @@
};
usb3: usb3@8af8800 {
compatible = "qcom,dwc3";
compatible = "qcom,ipq4019-dwc3", "qcom,dwc3";
reg = <0x8af8800 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@ -669,7 +669,7 @@
};
usb2: usb2@60f8800 {
compatible = "qcom,dwc3";
compatible = "qcom,ipq4019-dwc3", "qcom,dwc3";
reg = <0x60f8800 0x100>;
#address-cells = <1>;
#size-cells = <1>;

4
arch/arm/boot/dts/qcom-ipq8064.dtsi
View File

@ -1080,7 +1080,7 @@
};
usb3_0: usb3@100f8800 {
compatible = "qcom,dwc3", "syscon";
compatible = "qcom,ipq8064-dwc3", "qcom,dwc3";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x100f8800 0x8000>;
@ -1122,7 +1122,7 @@
};
usb3_1: usb3@110f8800 {
compatible = "qcom,dwc3", "syscon";
compatible = "qcom,ipq8064-dwc3", "qcom,dwc3";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x110f8800 0x8000>;

1
arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts
View File

@ -20,7 +20,6 @@
gpio-keys {
compatible = "gpio-keys";
input-name = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&gpio_keys_pin_a>;

1
arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts
View File

@ -450,7 +450,6 @@
gpio-keys {
compatible = "gpio-keys";
input-name = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&gpio_keys_pin_a>;

1
arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts
View File

@ -349,7 +349,6 @@
gpio-keys {
compatible = "gpio-keys";
input-name = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&gpio_keys_pin_a>;

1
arch/arm/boot/dts/qcom-msm8974-sony-xperia-amami.dts
View File

@ -20,7 +20,6 @@
gpio-keys {
compatible = "gpio-keys";
input-name = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&gpio_keys_pin_a>;

1
arch/arm/boot/dts/qcom-msm8974-sony-xperia-castor.dts
View File

@ -20,7 +20,6 @@
gpio-keys {
compatible = "gpio-keys";
input-name = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&gpio_keys_pin_a>;

1
arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts
View File

@ -20,7 +20,6 @@
gpio-keys {
compatible = "gpio-keys";
input-name = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&gpio_keys_pin_a>;

6
arch/arm/boot/dts/qcom-sdx55-t55.dts
View File

@ -236,6 +236,12 @@
status = "ok";
};
&ipa {
status = "okay";
memory-region = <&ipa_fw_mem>;
};
&qpic_bam {
status = "ok";
};

59
arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts
View File

@ -236,6 +236,27 @@
status = "ok";
};
&ipa {
status = "okay";
memory-region = <&ipa_fw_mem>;
};
&pcie0_phy {
status = "okay";
vdda-phy-supply = <&vreg_l1e_bb_1p2>;
vdda-pll-supply = <&vreg_l4e_bb_0p875>;
};
&pcie_ep {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pcie_ep_clkreq_default &pcie_ep_perst_default
&pcie_ep_wake_default>;
};
&qpic_bam {
status = "ok";
};
@ -260,6 +281,44 @@
memory-region = <&mpss_adsp_mem>;
};
&tlmm {
pcie_ep_clkreq_default: pcie_ep_clkreq_default {
mux {
pins = "gpio56";
function = "pcie_clkreq";
};
config {
pins = "gpio56";
drive-strength = <2>;
bias-disable;
};
};
pcie_ep_perst_default: pcie_ep_perst_default {
mux {
pins = "gpio57";
function = "gpio";
};
config {
pins = "gpio57";
drive-strength = <2>;
bias-pull-down;
};
};
pcie_ep_wake_default: pcie_ep_wake_default {
mux {
pins = "gpio53";
function = "gpio";
};
config {
pins = "gpio53";
drive-strength = <2>;
bias-disable;
};
};
};
&usb_hsphy {
status = "okay";
vdda-pll-supply = <&vreg_l4e_bb_0p875>;

80
arch/arm/boot/dts/qcom-sdx55.dtsi
View File

@ -8,6 +8,7 @@
#include <dt-bindings/clock/qcom,gcc-sdx55.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interconnect/qcom,sdx55.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/qcom-rpmpd.h>
@ -309,6 +310,41 @@
status = "disabled";
};
pcie0_phy: phy@1c07000 {
compatible = "qcom,sdx55-qmp-pcie-phy";
reg = <0x01c07000 0x1c4>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
clocks = <&gcc GCC_PCIE_AUX_PHY_CLK_SRC>,
<&gcc GCC_PCIE_CFG_AHB_CLK>,
<&gcc GCC_PCIE_0_CLKREF_CLK>,
<&gcc GCC_PCIE_RCHNG_PHY_CLK>;
clock-names = "aux", "cfg_ahb", "ref", "refgen";
resets = <&gcc GCC_PCIE_PHY_BCR>;
reset-names = "phy";
assigned-clocks = <&gcc GCC_PCIE_RCHNG_PHY_CLK>;
assigned-clock-rates = <100000000>;
status = "disabled";
pcie0_lane: lanes@1c06000 {
reg = <0x01c06000 0x104>, /* tx0 */
<0x01c06200 0x328>, /* rx0 */
<0x01c07200 0x1e8>, /* pcs */
<0x01c06800 0x104>, /* tx1 */
<0x01c06a00 0x328>, /* rx1 */
<0x01c07600 0x800>; /* pcs_misc */
clocks = <&gcc GCC_PCIE_PIPE_CLK>;
clock-names = "pipe0";
#phy-cells = <0>;
clock-output-names = "pcie_pipe_clk";
};
};
ipa: ipa@1e40000 {
compatible = "qcom,sdx55-ipa";
@ -356,6 +392,11 @@
#hwlock-cells = <1>;
};
tcsr: syscon@1fcb000 {
compatible = "syscon";
reg = <0x01fc0000 0x1000>;
};
sdhc_1: sdhci@8804000 {
compatible = "qcom,sdx55-sdhci", "qcom,sdhci-msm-v5";
reg = <0x08804000 0x1000>;
@ -368,6 +409,45 @@
status = "disabled";
};
pcie_ep: pcie-ep@40000000 {
compatible = "qcom,sdx55-pcie-ep";
reg = <0x01c00000 0x3000>,
<0x40000000 0xf1d>,
<0x40000f20 0xc8>,
<0x40001000 0x1000>,
<0x40002000 0x10000>,
<0x01c03000 0x3000>;
reg-names = "parf", "dbi", "elbi", "atu", "addr_space",
"mmio";
qcom,perst-regs = <&tcsr 0xb258 0xb270>;
clocks = <&gcc GCC_PCIE_AUX_CLK>,
<&gcc GCC_PCIE_CFG_AHB_CLK>,
<&gcc GCC_PCIE_MSTR_AXI_CLK>,
<&gcc GCC_PCIE_SLV_AXI_CLK>,
<&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
<&gcc GCC_PCIE_SLEEP_CLK>,
<&gcc GCC_PCIE_0_CLKREF_CLK>;
clock-names = "aux", "cfg", "bus_master", "bus_slave",
"slave_q2a", "sleep", "ref";
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "global", "doorbell";
reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>;
resets = <&gcc GCC_PCIE_BCR>;
reset-names = "core";
power-domains = <&gcc PCIE_GDSC>;
phys = <&pcie0_lane>;
phy-names = "pciephy";
max-link-speed = <3>;
num-lanes = <2>;
status = "disabled";
};
remoteproc_mpss: remoteproc@4080000 {
compatible = "qcom,sdx55-mpss-pas";
reg = <0x04080000 0x4040>;

25
arch/arm/boot/dts/qcom-sdx65-mtp.dts Normal file
View File

@ -0,0 +1,25 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
#include "qcom-sdx65.dtsi"
/ {
model = "Qualcomm Technologies, Inc. SDX65 MTP";
compatible = "qcom,sdx65-mtp", "qcom,sdx65";
qcom,board-id = <0x2010008 0x302>;
aliases {
serial0 = &blsp1_uart3;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&blsp1_uart3 {
status = "ok";
};

222
arch/arm/boot/dts/qcom-sdx65.dtsi Normal file
View File

@ -0,0 +1,222 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* SDX65 SoC device tree source
*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
*/
#include <dt-bindings/clock/qcom,gcc-sdx65.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
qcom,msm-id = <458 0x10000>, <483 0x10000>, <509 0x10000>;
interrupt-parent = <&intc>;
memory {
device_type = "memory";
reg = <0 0>;
};
clocks {
xo_board: xo-board {
compatible = "fixed-clock";
clock-frequency = <76800000>;
clock-output-names = "xo_board";
#clock-cells = <0>;
};
sleep_clk: sleep-clk {
compatible = "fixed-clock";
clock-frequency = <32764>;
clock-output-names = "sleep_clk";
#clock-cells = <0>;
};
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x0>;
enable-method = "psci";
};
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
reserved_memory: reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
cmd_db: reserved-memory@8fee0000 {
compatible = "qcom,cmd-db";
reg = <0x8fee0000 0x20000>;
no-map;
};
};
soc: soc {
#address-cells = <1>;
#size-cells = <1>;
ranges;
compatible = "simple-bus";
gcc: clock-controller@100000 {
compatible = "qcom,gcc-sdx65";
reg = <0x00100000 0x001f7400>;
clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>;
clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
#clock-cells = <1>;
#reset-cells = <1>;
};
blsp1_uart3: serial@831000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x00831000 0x200>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
status = "disabled";
};
tlmm: pinctrl@f100000 {
compatible = "qcom,sdx65-tlmm";
reg = <0xf100000 0x300000>;
interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&tlmm 0 0 109>;
interrupt-controller;
interrupt-parent = <&intc>;
#interrupt-cells = <2>;
};
pdc: interrupt-controller@b210000 {
compatible = "qcom,sdx65-pdc", "qcom,pdc";
reg = <0xb210000 0x10000>;
qcom,pdc-ranges = <0 147 52>, <52 266 32>;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupt-controller;
};
intc: interrupt-controller@17800000 {
compatible = "qcom,msm-qgic2";
interrupt-controller;
interrupt-parent = <&intc>;
#interrupt-cells = <3>;
reg = <0x17800000 0x1000>,
<0x17802000 0x1000>;
};
timer@17820000 {
#address-cells = <1>;
#size-cells = <1>;
ranges;
compatible = "arm,armv7-timer-mem";
reg = <0x17820000 0x1000>;
clock-frequency = <19200000>;
frame@17821000 {
frame-number = <0>;
interrupts = <GIC_SPI 7 0x4>,
<GIC_SPI 6 0x4>;
reg = <0x17821000 0x1000>,
<0x17822000 0x1000>;
};
frame@17823000 {
frame-number = <1>;
interrupts = <GIC_SPI 8 0x4>;
reg = <0x17823000 0x1000>;
status = "disabled";
};
frame@17824000 {
frame-number = <2>;
interrupts = <GIC_SPI 9 0x4>;
reg = <0x17824000 0x1000>;
status = "disabled";
};
frame@17825000 {
frame-number = <3>;
interrupts = <GIC_SPI 10 0x4>;
reg = <0x17825000 0x1000>;
status = "disabled";
};
frame@17826000 {
frame-number = <4>;
interrupts = <GIC_SPI 11 0x4>;
reg = <0x17826000 0x1000>;
status = "disabled";
};
frame@17827000 {
frame-number = <5>;
interrupts = <GIC_SPI 12 0x4>;
reg = <0x17827000 0x1000>;
status = "disabled";
};
frame@17828000 {
frame-number = <6>;
interrupts = <GIC_SPI 13 0x4>;
reg = <0x17828000 0x1000>;
status = "disabled";
};
frame@17829000 {
frame-number = <7>;
interrupts = <GIC_SPI 14 0x4>;
reg = <0x17829000 0x1000>;
status = "disabled";
};
};
apps_rsc: rsc@17830000 {
label = "apps_rsc";
compatible = "qcom,rpmh-rsc";
reg = <0x17830000 0x10000>,
<0x17840000 0x10000>;
reg-names = "drv-0", "drv-1";
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
qcom,tcs-offset = <0xd00>;
qcom,drv-id = <1>;
qcom,tcs-config = <ACTIVE_TCS 2>,
<SLEEP_TCS 2>,
<WAKE_TCS 2>,
<CONTROL_TCS 1>;
rpmhcc: clock-controller@1 {
compatible = "qcom,sdx65-rpmh-clk";
#clock-cells = <1>;
clock-names = "xo";
clocks = <&xo_board>;
};
};
};
timer {
compatible = "arm,armv7-timer";
interrupts = <1 13 0xf08>,
<1 12 0xf08>,
<1 10 0xf08>,
<1 11 0xf08>;
clock-frequency = <19200000>;
};
};

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include/dt-bindings/clock/qcom,gcc-sdx65.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SDX65_H
#define _DT_BINDINGS_CLK_QCOM_GCC_SDX65_H
/* GCC clocks */
#define GPLL0 0
#define GPLL0_OUT_EVEN 1
#define GCC_AHB_PCIE_LINK_CLK 2
#define GCC_BLSP1_AHB_CLK 3
#define GCC_BLSP1_QUP1_I2C_APPS_CLK 4
#define GCC_BLSP1_QUP1_I2C_APPS_CLK_SRC 5
#define GCC_BLSP1_QUP1_SPI_APPS_CLK 6
#define GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC 7
#define GCC_BLSP1_QUP2_I2C_APPS_CLK 8
#define GCC_BLSP1_QUP2_I2C_APPS_CLK_SRC 9
#define GCC_BLSP1_QUP2_SPI_APPS_CLK 10
#define GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC 11
#define GCC_BLSP1_QUP3_I2C_APPS_CLK 12
#define GCC_BLSP1_QUP3_I2C_APPS_CLK_SRC 13
#define GCC_BLSP1_QUP3_SPI_APPS_CLK 14
#define GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC 15
#define GCC_BLSP1_QUP4_I2C_APPS_CLK 16
#define GCC_BLSP1_QUP4_I2C_APPS_CLK_SRC 17
#define GCC_BLSP1_QUP4_SPI_APPS_CLK 18
#define GCC_BLSP1_QUP4_SPI_APPS_CLK_SRC 19
#define GCC_BLSP1_SLEEP_CLK 20
#define GCC_BLSP1_UART1_APPS_CLK 21
#define GCC_BLSP1_UART1_APPS_CLK_SRC 22
#define GCC_BLSP1_UART2_APPS_CLK 23
#define GCC_BLSP1_UART2_APPS_CLK_SRC 24
#define GCC_BLSP1_UART3_APPS_CLK 25
#define GCC_BLSP1_UART3_APPS_CLK_SRC 26
#define GCC_BLSP1_UART4_APPS_CLK 27
#define GCC_BLSP1_UART4_APPS_CLK_SRC 28
#define GCC_BOOT_ROM_AHB_CLK 29
#define GCC_CPUSS_AHB_CLK 30
#define GCC_CPUSS_AHB_CLK_SRC 31
#define GCC_CPUSS_AHB_POSTDIV_CLK_SRC 32
#define GCC_CPUSS_GNOC_CLK 33
#define GCC_GP1_CLK 34
#define GCC_GP1_CLK_SRC 35
#define GCC_GP2_CLK 36
#define GCC_GP2_CLK_SRC 37
#define GCC_GP3_CLK 38
#define GCC_GP3_CLK_SRC 39
#define GCC_PCIE_0_CLKREF_EN 40
#define GCC_PCIE_AUX_CLK 41
#define GCC_PCIE_AUX_CLK_SRC 42
#define GCC_PCIE_AUX_PHY_CLK_SRC 43
#define GCC_PCIE_CFG_AHB_CLK 44
#define GCC_PCIE_MSTR_AXI_CLK 45
#define GCC_PCIE_PIPE_CLK 46
#define GCC_PCIE_PIPE_CLK_SRC 47
#define GCC_PCIE_RCHNG_PHY_CLK 48
#define GCC_PCIE_RCHNG_PHY_CLK_SRC 49
#define GCC_PCIE_SLEEP_CLK 50
#define GCC_PCIE_SLV_AXI_CLK 51
#define GCC_PCIE_SLV_Q2A_AXI_CLK 52
#define GCC_PDM2_CLK 53
#define GCC_PDM2_CLK_SRC 54
#define GCC_PDM_AHB_CLK 55
#define GCC_PDM_XO4_CLK 56
#define GCC_RX1_USB2_CLKREF_EN 57
#define GCC_SDCC1_AHB_CLK 58
#define GCC_SDCC1_APPS_CLK 59
#define GCC_SDCC1_APPS_CLK_SRC 60
#define GCC_SPMI_FETCHER_AHB_CLK 61
#define GCC_SPMI_FETCHER_CLK 62
#define GCC_SPMI_FETCHER_CLK_SRC 63
#define GCC_SYS_NOC_CPUSS_AHB_CLK 64
#define GCC_USB30_MASTER_CLK 65
#define GCC_USB30_MASTER_CLK_SRC 66
#define GCC_USB30_MOCK_UTMI_CLK 67
#define GCC_USB30_MOCK_UTMI_CLK_SRC 68
#define GCC_USB30_MOCK_UTMI_POSTDIV_CLK_SRC 69
#define GCC_USB30_MSTR_AXI_CLK 70
#define GCC_USB30_SLEEP_CLK 71
#define GCC_USB30_SLV_AHB_CLK 72
#define GCC_USB3_PHY_AUX_CLK 73
#define GCC_USB3_PHY_AUX_CLK_SRC 74
#define GCC_USB3_PHY_PIPE_CLK 75
#define GCC_USB3_PHY_PIPE_CLK_SRC 76
#define GCC_USB3_PRIM_CLKREF_EN 77
#define GCC_USB_PHY_CFG_AHB2PHY_CLK 78
#define GCC_XO_DIV4_CLK 79
#define GCC_XO_PCIE_LINK_CLK 80
/* GCC resets */
#define GCC_BLSP1_QUP1_BCR 0
#define GCC_BLSP1_QUP2_BCR 1
#define GCC_BLSP1_QUP3_BCR 2
#define GCC_BLSP1_QUP4_BCR 3
#define GCC_BLSP1_UART1_BCR 4
#define GCC_BLSP1_UART2_BCR 5
#define GCC_BLSP1_UART3_BCR 6
#define GCC_BLSP1_UART4_BCR 7
#define GCC_PCIE_BCR 8
#define GCC_PCIE_LINK_DOWN_BCR 9
#define GCC_PCIE_NOCSR_COM_PHY_BCR 10
#define GCC_PCIE_PHY_BCR 11
#define GCC_PCIE_PHY_CFG_AHB_BCR 12
#define GCC_PCIE_PHY_COM_BCR 13
#define GCC_PCIE_PHY_NOCSR_COM_PHY_BCR 14
#define GCC_PDM_BCR 15
#define GCC_QUSB2PHY_BCR 16
#define GCC_SDCC1_BCR 17
#define GCC_SPMI_FETCHER_BCR 18
#define GCC_TCSR_PCIE_BCR 19
#define GCC_USB30_BCR 20
#define GCC_USB3_PHY_BCR 21
#define GCC_USB3PHY_PHY_BCR 22
#define GCC_USB_PHY_CFG_AHB2PHY_BCR 23
/* GCC power domains */
#define USB30_GDSC 0
#define PCIE_GDSC 1
#endif