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pwm: atmel-hlcdc: Prevent division by zero

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The slow and system clock should never return a rate of zero, but this
might happen if the clocks property defined in the DT is referencing the
wrong clocks.

Prevent any division by zero from happening by testing the clk_freq
value before calling do_div().

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
This commit is contained in:
Boris BREZILLON 2014-12-18 21:05:30 +01:00 committed by Thierry Reding
parent d2048c4915
commit df6922adec
1 changed files with 6 additions and 0 deletions
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6
drivers/pwm/pwm-atmel-hlcdc.c
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@ -64,6 +64,9 @@ static int atmel_hlcdc_pwm_config(struct pwm_chip *c,
if (!chip->errata || !chip->errata->slow_clk_erratum) {
clk_freq = clk_get_rate(new_clk);
if (!clk_freq)
return -EINVAL;
clk_period_ns = (u64)NSEC_PER_SEC * 256;
do_div(clk_period_ns, clk_freq);
}
@ -73,6 +76,9 @@ static int atmel_hlcdc_pwm_config(struct pwm_chip *c,
clk_period_ns > period_ns) {
new_clk = hlcdc->sys_clk;
clk_freq = clk_get_rate(new_clk);
if (!clk_freq)
return -EINVAL;
clk_period_ns = (u64)NSEC_PER_SEC * 256;
do_div(clk_period_ns, clk_freq);
}