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x86/amd_nb: Enhance SMN access error checking
AMD Zen-based systems use a System Management Network (SMN) that provides access to implementation-specific registers. SMN accesses are done indirectly through an index/data pair in PCI config space. The accesses can fail for a variety of reasons. Include code comments to describe some possible scenarios. Require error checking for callers of amd_smn_read() and amd_smn_write(). This is needed because many error conditions cannot be checked by these functions. [ bp: Touchup comment. ] Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Mario Limonciello <mario.limonciello@amd.com> Link: https://lore.kernel.org/r/20240606-fix-smn-bad-read-v4-4-ffde21931c3f@amd.com
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@ -21,8 +21,8 @@ extern int amd_numa_init(void);
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extern int amd_get_subcaches(int);
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extern int amd_get_subcaches(int);
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extern int amd_set_subcaches(int, unsigned long);
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extern int amd_set_subcaches(int, unsigned long);
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extern int amd_smn_read(u16 node, u32 address, u32 *value);
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int __must_check amd_smn_read(u16 node, u32 address, u32 *value);
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extern int amd_smn_write(u16 node, u32 address, u32 value);
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int __must_check amd_smn_write(u16 node, u32 address, u32 value);
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struct amd_l3_cache {
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struct amd_l3_cache {
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unsigned indices;
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unsigned indices;
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@ -180,6 +180,43 @@ static struct pci_dev *next_northbridge(struct pci_dev *dev,
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return dev;
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return dev;
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}
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}
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/*
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* SMN accesses may fail in ways that are difficult to detect here in the called
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* functions amd_smn_read() and amd_smn_write(). Therefore, callers must do
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* their own checking based on what behavior they expect.
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*
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* For SMN reads, the returned value may be zero if the register is Read-as-Zero.
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* Or it may be a "PCI Error Response", e.g. all 0xFFs. The "PCI Error Response"
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* can be checked here, and a proper error code can be returned.
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*
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* But the Read-as-Zero response cannot be verified here. A value of 0 may be
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* correct in some cases, so callers must check that this correct is for the
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* register/fields they need.
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*
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* For SMN writes, success can be determined through a "write and read back"
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* However, this is not robust when done here.
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*
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* Possible issues:
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*
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* 1) Bits that are "Write-1-to-Clear". In this case, the read value should
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* *not* match the write value.
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*
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* 2) Bits that are "Read-as-Zero"/"Writes-Ignored". This information cannot be
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* known here.
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*
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* 3) Bits that are "Reserved / Set to 1". Ditto above.
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*
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* Callers of amd_smn_write() should do the "write and read back" check
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* themselves, if needed.
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*
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* For #1, they can see if their target bits got cleared.
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*
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* For #2 and #3, they can check if their target bits got set as intended.
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*
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* This matches what is done for RDMSR/WRMSR. As long as there's no #GP, then
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* the operation is considered a success, and the caller does their own
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* checking.
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*/
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static int __amd_smn_rw(u16 node, u32 address, u32 *value, bool write)
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static int __amd_smn_rw(u16 node, u32 address, u32 *value, bool write)
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{
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{
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struct pci_dev *root;
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struct pci_dev *root;
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@ -202,9 +239,6 @@ static int __amd_smn_rw(u16 node, u32 address, u32 *value, bool write)
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err = (write ? pci_write_config_dword(root, 0x64, *value)
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err = (write ? pci_write_config_dword(root, 0x64, *value)
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: pci_read_config_dword(root, 0x64, value));
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: pci_read_config_dword(root, 0x64, value));
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if (err)
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pr_warn("Error %s SMN address 0x%x.\n",
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(write ? "writing to" : "reading from"), address);
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out_unlock:
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out_unlock:
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mutex_unlock(&smn_mutex);
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mutex_unlock(&smn_mutex);
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@ -213,7 +247,7 @@ out:
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return err;
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return err;
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}
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}
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int amd_smn_read(u16 node, u32 address, u32 *value)
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int __must_check amd_smn_read(u16 node, u32 address, u32 *value)
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{
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{
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int err = __amd_smn_rw(node, address, value, false);
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int err = __amd_smn_rw(node, address, value, false);
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@ -226,7 +260,7 @@ int amd_smn_read(u16 node, u32 address, u32 *value)
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}
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}
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EXPORT_SYMBOL_GPL(amd_smn_read);
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EXPORT_SYMBOL_GPL(amd_smn_read);
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int amd_smn_write(u16 node, u32 address, u32 value)
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int __must_check amd_smn_write(u16 node, u32 address, u32 value)
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{
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{
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return __amd_smn_rw(node, address, &value, true);
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return __amd_smn_rw(node, address, &value, true);
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}
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}
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