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Merge branch 'mvneta'
Thomas Petazzoni says: ==================== net: mvneta: fix usage as a module The following set of two patches fix the usage of the mvneta driver when built as a module, and used in RGMII configurations. It is somewhat similar to a previous fix that was made by Arnaud Patard, but which was limited to SGMII configurations. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
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commit
dc0fe58f35
@ -22,6 +22,7 @@
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#include <linux/interrupt.h>
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#include <net/ip.h>
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#include <net/ipv6.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include <linux/of_mdio.h>
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@ -88,8 +89,9 @@
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#define MVNETA_TX_IN_PRGRS BIT(1)
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#define MVNETA_TX_FIFO_EMPTY BIT(8)
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#define MVNETA_RX_MIN_FRAME_SIZE 0x247c
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#define MVNETA_SGMII_SERDES_CFG 0x24A0
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#define MVNETA_SERDES_CFG 0x24A0
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#define MVNETA_SGMII_SERDES_PROTO 0x0cc7
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#define MVNETA_RGMII_SERDES_PROTO 0x0667
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#define MVNETA_TYPE_PRIO 0x24bc
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#define MVNETA_FORCE_UNI BIT(21)
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#define MVNETA_TXQ_CMD_1 0x24e4
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@ -161,7 +163,7 @@
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#define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc
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#define MVNETA_GMAC0_PORT_ENABLE BIT(0)
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#define MVNETA_GMAC_CTRL_2 0x2c08
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#define MVNETA_GMAC2_PSC_ENABLE BIT(3)
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#define MVNETA_GMAC2_PCS_ENABLE BIT(3)
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#define MVNETA_GMAC2_PORT_RGMII BIT(4)
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#define MVNETA_GMAC2_PORT_RESET BIT(6)
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#define MVNETA_GMAC_STATUS 0x2c10
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@ -710,35 +712,6 @@ static void mvneta_rxq_bm_disable(struct mvneta_port *pp,
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mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
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}
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/* Sets the RGMII Enable bit (RGMIIEn) in port MAC control register */
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static void mvneta_gmac_rgmii_set(struct mvneta_port *pp, int enable)
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{
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u32 val;
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val = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
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if (enable)
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val |= MVNETA_GMAC2_PORT_RGMII;
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else
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val &= ~MVNETA_GMAC2_PORT_RGMII;
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mvreg_write(pp, MVNETA_GMAC_CTRL_2, val);
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}
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/* Config SGMII port */
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static void mvneta_port_sgmii_config(struct mvneta_port *pp)
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{
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u32 val;
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val = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
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val |= MVNETA_GMAC2_PSC_ENABLE;
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mvreg_write(pp, MVNETA_GMAC_CTRL_2, val);
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mvreg_write(pp, MVNETA_SGMII_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO);
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}
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/* Start the Ethernet port RX and TX activity */
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static void mvneta_port_up(struct mvneta_port *pp)
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{
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@ -2756,12 +2729,15 @@ static void mvneta_port_power_up(struct mvneta_port *pp, int phy_mode)
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mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0);
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if (phy_mode == PHY_INTERFACE_MODE_SGMII)
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mvneta_port_sgmii_config(pp);
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mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO);
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else
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mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_RGMII_SERDES_PROTO);
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mvneta_gmac_rgmii_set(pp, 1);
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val = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
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val |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII;
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/* Cancel Port Reset */
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val = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
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val &= ~MVNETA_GMAC2_PORT_RESET;
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mvreg_write(pp, MVNETA_GMAC_CTRL_2, val);
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@ -2774,6 +2750,7 @@ static void mvneta_port_power_up(struct mvneta_port *pp, int phy_mode)
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static int mvneta_probe(struct platform_device *pdev)
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{
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const struct mbus_dram_target_info *dram_target_info;
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struct resource *res;
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struct device_node *dn = pdev->dev.of_node;
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struct device_node *phy_node;
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u32 phy_addr;
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@ -2838,9 +2815,15 @@ static int mvneta_probe(struct platform_device *pdev)
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clk_prepare_enable(pp->clk);
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pp->base = of_iomap(dn, 0);
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res) {
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err = -ENODEV;
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goto err_clk;
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}
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pp->base = devm_ioremap_resource(&pdev->dev, res);
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if (pp->base == NULL) {
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err = -ENOMEM;
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err = PTR_ERR(pp->base);
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goto err_clk;
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}
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@ -2848,7 +2831,7 @@ static int mvneta_probe(struct platform_device *pdev)
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pp->stats = alloc_percpu(struct mvneta_pcpu_stats);
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if (!pp->stats) {
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err = -ENOMEM;
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goto err_unmap;
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goto err_clk;
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}
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for_each_possible_cpu(cpu) {
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@ -2913,8 +2896,6 @@ err_deinit:
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mvneta_deinit(pp);
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err_free_stats:
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free_percpu(pp->stats);
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err_unmap:
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iounmap(pp->base);
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err_clk:
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clk_disable_unprepare(pp->clk);
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err_free_irq:
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@ -2934,7 +2915,6 @@ static int mvneta_remove(struct platform_device *pdev)
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mvneta_deinit(pp);
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clk_disable_unprepare(pp->clk);
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free_percpu(pp->stats);
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iounmap(pp->base);
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irq_dispose_mapping(dev->irq);
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free_netdev(dev);
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