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PCI: mvebu: Add PCI Express root complex capability block
Add a PCI Express root complex capability block so the PCI layer identifies the bridge as a PCI Express device. We expose this as a version 1 PCIe capability block, with slot support. We disable the clock power management capability as this depends on boards wiring the CLKREQ# signal. Tested-by: Willy Tarreau <w@1wt.eu> (Iomega iConnect Kirkwood, MiraBox Armada 370) Tested-by: Andrew Lunn <andrew@lunn.ch> (D-Link DIR664 Kirkwood) Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> (Armada XP GP) Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
This commit is contained in:
Russell King
Bjorn Helgaas
parent
d609a8d8e8
commit
dc0352ab0b
@ -30,6 +30,7 @@
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#define PCIE_DEV_REV_OFF 0x0008
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#define PCIE_BAR_LO_OFF(n) (0x0010 + ((n) << 3))
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#define PCIE_BAR_HI_OFF(n) (0x0014 + ((n) << 3))
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#define PCIE_CAP_PCIEXP 0x0060
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#define PCIE_HEADER_LOG_4_OFF 0x0128
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#define PCIE_BAR_CTRL_OFF(n) (0x1804 + (((n) - 1) * 4))
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#define PCIE_WIN04_CTRL_OFF(n) (0x1820 + ((n) << 4))
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@ -57,14 +58,35 @@
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#define PCIE_STAT_BUS 0xff00
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#define PCIE_STAT_DEV 0x1f0000
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#define PCIE_STAT_LINK_DOWN BIT(0)
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#define PCIE_RC_RTSTA 0x1a14
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#define PCIE_DEBUG_CTRL 0x1a60
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#define PCIE_DEBUG_SOFT_RESET BIT(20)
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enum {
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PCISWCAP = PCI_BRIDGE_CONTROL + 2,
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PCISWCAP_EXP_LIST_ID = PCISWCAP + PCI_CAP_LIST_ID,
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PCISWCAP_EXP_DEVCAP = PCISWCAP + PCI_EXP_DEVCAP,
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PCISWCAP_EXP_DEVCTL = PCISWCAP + PCI_EXP_DEVCTL,
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PCISWCAP_EXP_LNKCAP = PCISWCAP + PCI_EXP_LNKCAP,
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PCISWCAP_EXP_LNKCTL = PCISWCAP + PCI_EXP_LNKCTL,
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PCISWCAP_EXP_SLTCAP = PCISWCAP + PCI_EXP_SLTCAP,
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PCISWCAP_EXP_SLTCTL = PCISWCAP + PCI_EXP_SLTCTL,
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PCISWCAP_EXP_RTCTL = PCISWCAP + PCI_EXP_RTCTL,
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PCISWCAP_EXP_RTSTA = PCISWCAP + PCI_EXP_RTSTA,
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PCISWCAP_EXP_DEVCAP2 = PCISWCAP + PCI_EXP_DEVCAP2,
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PCISWCAP_EXP_DEVCTL2 = PCISWCAP + PCI_EXP_DEVCTL2,
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PCISWCAP_EXP_LNKCAP2 = PCISWCAP + PCI_EXP_LNKCAP2,
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PCISWCAP_EXP_LNKCTL2 = PCISWCAP + PCI_EXP_LNKCTL2,
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PCISWCAP_EXP_SLTCAP2 = PCISWCAP + PCI_EXP_SLTCAP2,
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PCISWCAP_EXP_SLTCTL2 = PCISWCAP + PCI_EXP_SLTCTL2,
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};
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/* PCI configuration space of a PCI-to-PCI bridge */
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struct mvebu_sw_pci_bridge {
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u16 vendor;
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u16 device;
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u16 command;
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u16 status;
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u16 class;
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u8 interface;
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u8 revision;
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@ -84,13 +106,15 @@ struct mvebu_sw_pci_bridge {
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u16 memlimit;
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u16 iobaseupper;
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u16 iolimitupper;
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u8 cappointer;
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u8 reserved1;
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u16 reserved2;
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u32 romaddr;
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u8 intline;
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u8 intpin;
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u16 bridgectrl;
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/* PCI express capability */
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u32 pcie_sltcap;
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u16 pcie_devctl;
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u16 pcie_rtctl;
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};
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struct mvebu_pcie_port;
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@ -451,6 +475,9 @@ static void mvebu_sw_pci_bridge_init(struct mvebu_pcie_port *port)
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/* We support 32 bits I/O addressing */
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bridge->iobase = PCI_IO_RANGE_TYPE_32;
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bridge->iolimit = PCI_IO_RANGE_TYPE_32;
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/* Add capabilities */
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bridge->status = PCI_STATUS_CAP_LIST;
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}
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/*
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@ -468,7 +495,7 @@ static int mvebu_sw_pci_bridge_read(struct mvebu_pcie_port *port,
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break;
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case PCI_COMMAND:
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*value = bridge->command;
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*value = bridge->command | bridge->status << 16;
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break;
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case PCI_CLASS_REVISION:
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@ -513,6 +540,10 @@ static int mvebu_sw_pci_bridge_read(struct mvebu_pcie_port *port,
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*value = (bridge->iolimitupper << 16 | bridge->iobaseupper);
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break;
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case PCI_CAPABILITY_LIST:
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*value = PCISWCAP;
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break;
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case PCI_ROM_ADDRESS1:
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*value = 0;
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break;
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@ -522,6 +553,59 @@ static int mvebu_sw_pci_bridge_read(struct mvebu_pcie_port *port,
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*value = 0;
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break;
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case PCISWCAP_EXP_LIST_ID:
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/* Set PCIe v2, root port, slot support */
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*value = (PCI_EXP_TYPE_ROOT_PORT << 4 | 2 |
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PCI_EXP_FLAGS_SLOT) << 16 | PCI_CAP_ID_EXP;
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break;
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case PCISWCAP_EXP_DEVCAP:
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*value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_DEVCAP);
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break;
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case PCISWCAP_EXP_DEVCTL:
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*value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_DEVCTL) &
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~(PCI_EXP_DEVCTL_URRE | PCI_EXP_DEVCTL_FERE |
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PCI_EXP_DEVCTL_NFERE | PCI_EXP_DEVCTL_CERE);
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*value |= bridge->pcie_devctl;
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break;
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case PCISWCAP_EXP_LNKCAP:
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/*
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* PCIe requires the clock power management capability to be
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* hard-wired to zero for downstream ports
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*/
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*value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_LNKCAP) &
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~PCI_EXP_LNKCAP_CLKPM;
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break;
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case PCISWCAP_EXP_LNKCTL:
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*value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL);
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break;
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case PCISWCAP_EXP_SLTCAP:
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*value = bridge->pcie_sltcap;
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break;
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case PCISWCAP_EXP_SLTCTL:
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*value = PCI_EXP_SLTSTA_PDS << 16;
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break;
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case PCISWCAP_EXP_RTCTL:
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*value = bridge->pcie_rtctl;
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break;
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case PCISWCAP_EXP_RTSTA:
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*value = mvebu_readl(port, PCIE_RC_RTSTA);
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break;
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/* PCIe requires the v2 fields to be hard-wired to zero */
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case PCISWCAP_EXP_DEVCAP2:
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case PCISWCAP_EXP_DEVCTL2:
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case PCISWCAP_EXP_LNKCAP2:
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case PCISWCAP_EXP_LNKCTL2:
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case PCISWCAP_EXP_SLTCAP2:
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case PCISWCAP_EXP_SLTCTL2:
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default:
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/*
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* PCI defines configuration read accesses to reserved or
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@ -614,6 +698,51 @@ static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port,
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mvebu_pcie_set_local_bus_nr(port, bridge->secondary_bus);
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break;
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case PCISWCAP_EXP_DEVCTL:
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/*
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* Armada370 data says these bits must always
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* be zero when in root complex mode.
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*/
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value &= ~(PCI_EXP_DEVCTL_URRE | PCI_EXP_DEVCTL_FERE |
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PCI_EXP_DEVCTL_NFERE | PCI_EXP_DEVCTL_CERE);
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/*
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* If the mask is 0xffff0000, then we only want to write
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* the device control register, rather than clearing the
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* RW1C bits in the device status register. Mask out the
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* status register bits.
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*/
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if (mask == 0xffff0000)
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value &= 0xffff;
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mvebu_writel(port, value, PCIE_CAP_PCIEXP + PCI_EXP_DEVCTL);
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break;
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case PCISWCAP_EXP_LNKCTL:
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/*
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* If we don't support CLKREQ, we must ensure that the
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* CLKREQ enable bit always reads zero. Since we haven't
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* had this capability, and it's dependent on board wiring,
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* disable it for the time being.
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*/
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value &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
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/*
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* If the mask is 0xffff0000, then we only want to write
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* the link control register, rather than clearing the
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* RW1C bits in the link status register. Mask out the
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* status register bits.
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*/
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if (mask == 0xffff0000)
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value &= 0xffff;
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mvebu_writel(port, value, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL);
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break;
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case PCISWCAP_EXP_RTSTA:
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mvebu_writel(port, value, PCIE_RC_RTSTA);
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break;
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default:
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break;
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}
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