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Merge tag 'br-v6.2b' of git://linuxtv.org/hverkuil/media_tree into media_stage

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* tag 'br-v6.2b' of git://linuxtv.org/hverkuil/media_tree: (24 commits)
  media: imx-jpeg: Lock on ioctl encoder/decoder stop cmd
  media: imx-jpeg: Support contiguous and non contiguous format
  media: imx-jpeg: Implement g_selection and s_selection
  mtk-jpegdec: add stop cmd interface for jpgdec
  media: mtk-jpegdec: refactor jpegdec func interface
  media: mtk-jpegdec: add output pic reorder interface
  media: mtk-jpegdec: add jpeg decode worker interface
  media: mtk-jpegdec: add jpegdec timeout func interface
  media: mtk-jpegdec: support jpegdec multi-hardware
  media: mtk-jpegdec: export jpeg decoder functions
  dt-bindings: mediatek: Add mediatek,mt8195-jpgdec compatible
  mtk-jpegenc: add stop cmd interface for jpgenc
  mtk-jpegenc: add output pic reorder interface
  mtk-jpegenc: add jpeg encode worker interface
  mtk-jpegenc: add jpegenc timeout func interface
  mtk-jpegenc: support jpegenc multi-hardware
  mtk-jpegenc: export jpeg encoder functions
  dt-bindings: mediatek: Add mediatek, mt8195-jpgenc compatible
  media: imx-jpeg: Disable useless interrupt to avoid kernel panic
  media: imx-jpeg: Don't clear stop state in handling dynamic resolution change
  ...
This commit is contained in:
Mauro Carvalho Chehab 2022-11-08 08:45:14 +00:00
commit dbc1fdcbe2
14 changed files with 1933 additions and 256 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

168
Documentation/devicetree/bindings/media/mediatek,mt8195-jpegdec.yaml Normal file
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@ -0,0 +1,168 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/mediatek,mt8195-jpegdec.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek JPEG Decoder
maintainers:
- kyrie wu <kyrie.wu@mediatek.corp-partner.google.com>
description:
MediaTek JPEG Decoder is the JPEG decode hardware present in MediaTek SoCs
properties:
compatible:
const: mediatek,mt8195-jpgdec
power-domains:
maxItems: 1
iommus:
maxItems: 6
description:
Points to the respective IOMMU block with master port as argument, see
Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
Ports are according to the HW.
dma-ranges:
maxItems: 1
description: |
Describes the physical address space of IOMMU maps to memory.
"#address-cells":
const: 2
"#size-cells":
const: 2
ranges: true
# Required child node:
patternProperties:
"^jpgdec@[0-9a-f]+$":
type: object
description:
The jpeg decoder hardware device node which should be added as subnodes to
the main jpeg node.
properties:
compatible:
const: mediatek,mt8195-jpgdec-hw
reg:
maxItems: 1
iommus:
minItems: 1
maxItems: 32
description:
List of the hardware port in respective IOMMU block for current Socs.
Refer to bindings/iommu/mediatek,iommu.yaml.
interrupts:
maxItems: 1
clocks:
maxItems: 1
clock-names:
items:
- const: jpgdec
power-domains:
maxItems: 1
required:
- compatible
- reg
- iommus
- interrupts
- clocks
- clock-names
- power-domains
additionalProperties: false
required:
- compatible
- power-domains
- iommus
- dma-ranges
- ranges
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/memory/mt8195-memory-port.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clock/mt8195-clk.h>
#include <dt-bindings/power/mt8195-power.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
jpgdec-master {
compatible = "mediatek,mt8195-jpgdec";
power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
iommus = <&iommu_vpp M4U_PORT_L19_JPGDEC_WDMA0>,
<&iommu_vpp M4U_PORT_L19_JPGDEC_BSDMA0>,
<&iommu_vpp M4U_PORT_L19_JPGDEC_WDMA1>,
<&iommu_vpp M4U_PORT_L19_JPGDEC_BSDMA1>,
<&iommu_vpp M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,
<&iommu_vpp M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
jpgdec@1a040000 {
compatible = "mediatek,mt8195-jpgdec-hw";
reg = <0 0x1a040000 0 0x10000>;/* JPGDEC_C0 */
iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>,
<&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>,
<&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>,
<&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>,
<&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,
<&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vencsys CLK_VENC_JPGDEC>;
clock-names = "jpgdec";
power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
};
jpgdec@1a050000 {
compatible = "mediatek,mt8195-jpgdec-hw";
reg = <0 0x1a050000 0 0x10000>;/* JPGDEC_C1 */
iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>,
<&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>,
<&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>,
<&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>,
<&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,
<&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vencsys CLK_VENC_JPGDEC_C1>;
clock-names = "jpgdec";
power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
};
jpgdec@1b040000 {
compatible = "mediatek,mt8195-jpgdec-hw";
reg = <0 0x1b040000 0 0x10000>;/* JPGDEC_C2 */
iommus = <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA0>,
<&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA0>,
<&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA1>,
<&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA1>,
<&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET1>,
<&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET0>;
interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGDEC>;
clock-names = "jpgdec";
power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>;
};
};
};

147
Documentation/devicetree/bindings/media/mediatek,mt8195-jpegenc.yaml Normal file
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@ -0,0 +1,147 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/mediatek,mt8195-jpegenc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek JPEG Encoder
maintainers:
- kyrie wu <kyrie.wu@mediatek.corp-partner.google.com>
description:
MediaTek JPEG Encoder is the JPEG encode hardware present in MediaTek SoCs
properties:
compatible:
const: mediatek,mt8195-jpgenc
power-domains:
maxItems: 1
iommus:
maxItems: 4
description:
Points to the respective IOMMU block with master port as argument, see
Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
Ports are according to the HW.
dma-ranges:
maxItems: 1
description: |
Describes the physical address space of IOMMU maps to memory.
"#address-cells":
const: 2
"#size-cells":
const: 2
ranges: true
# Required child node:
patternProperties:
"^jpgenc@[0-9a-f]+$":
type: object
description:
The jpeg encoder hardware device node which should be added as subnodes to
the main jpeg node.
properties:
compatible:
const: mediatek,mt8195-jpgenc-hw
reg:
maxItems: 1
iommus:
minItems: 1
maxItems: 32
description:
List of the hardware port in respective IOMMU block for current Socs.
Refer to bindings/iommu/mediatek,iommu.yaml.
interrupts:
maxItems: 1
clocks:
maxItems: 1
clock-names:
items:
- const: jpgenc
power-domains:
maxItems: 1
required:
- compatible
- reg
- iommus
- interrupts
- clocks
- clock-names
- power-domains
additionalProperties: false
required:
- compatible
- power-domains
- iommus
- dma-ranges
- ranges
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/memory/mt8195-memory-port.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clock/mt8195-clk.h>
#include <dt-bindings/power/mt8195-power.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
jpgenc-master {
compatible = "mediatek,mt8195-jpgenc";
power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>,
<&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>,
<&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>,
<&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>;
dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
jpgenc@1a030000 {
compatible = "mediatek,mt8195-jpgenc-hw";
reg = <0 0x1a030000 0 0x10000>;
iommus = <&iommu_vdo M4U_PORT_L19_JPGENC_Y_RDMA>,
<&iommu_vdo M4U_PORT_L19_JPGENC_C_RDMA>,
<&iommu_vdo M4U_PORT_L19_JPGENC_Q_TABLE>,
<&iommu_vdo M4U_PORT_L19_JPGENC_BSDMA>;
interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vencsys CLK_VENC_JPGENC>;
clock-names = "jpgenc";
power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
};
jpgenc@1b030000 {
compatible = "mediatek,mt8195-jpgenc-hw";
reg = <0 0x1b030000 0 0x10000>;
iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>,
<&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>,
<&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>,
<&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>;
interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGENC>;
clock-names = "jpgenc";
power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
};
};
};

1
Documentation/devicetree/bindings/media/mediatek-jpeg-decoder.yaml
View File

@ -22,6 +22,7 @@ properties:
- items:
- enum:
- mediatek,mt7623-jpgdec
- mediatek,mt8188-jpgdec
- const: mediatek,mt2701-jpgdec
reg:

1
Documentation/devicetree/bindings/media/mediatek-jpeg-encoder.yaml
View File

@ -19,6 +19,7 @@ properties:
- mediatek,mt2701-jpgenc
- mediatek,mt8183-jpgenc
- mediatek,mt8186-jpgenc
- mediatek,mt8188-jpgenc
- const: mediatek,mtk-jpgenc
reg:
maxItems: 1

14
drivers/media/platform/mediatek/jpeg/Makefile
View File

@ -1,6 +1,10 @@
# SPDX-License-Identifier: GPL-2.0-only
mtk_jpeg-objs := mtk_jpeg_core.o \
mtk_jpeg_dec_hw.o \
mtk_jpeg_dec_parse.o \
mtk_jpeg_enc_hw.o
obj-$(CONFIG_VIDEO_MEDIATEK_JPEG) += mtk_jpeg.o
obj-$(CONFIG_VIDEO_MEDIATEK_JPEG) += mtk_jpeg.o \
mtk-jpeg-enc-hw.o \
mtk-jpeg-dec-hw.o
mtk_jpeg-y := mtk_jpeg_core.o \
mtk_jpeg_dec_parse.o
mtk-jpeg-enc-hw-y := mtk_jpeg_enc_hw.o
mtk-jpeg-dec-hw-y := mtk_jpeg_dec_hw.o

490
drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
View File

@ -104,11 +104,11 @@ static struct mtk_jpeg_fmt mtk_jpeg_dec_formats[] = {
#define MTK_JPEG_ENC_NUM_FORMATS ARRAY_SIZE(mtk_jpeg_enc_formats)
#define MTK_JPEG_DEC_NUM_FORMATS ARRAY_SIZE(mtk_jpeg_dec_formats)
#define MTK_JPEG_MAX_RETRY_TIME 5000
struct mtk_jpeg_src_buf {
struct vb2_v4l2_buffer b;
struct list_head list;
struct mtk_jpeg_dec_param dec_param;
enum {
MTK_JPEG_BUF_FLAGS_INIT = 0,
MTK_JPEG_BUF_FLAGS_LAST_FRAME = 1,
};
static int debug;
@ -586,6 +586,31 @@ static int mtk_jpeg_enc_s_selection(struct file *file, void *priv,
return 0;
}
static int mtk_jpeg_qbuf(struct file *file, void *priv, struct v4l2_buffer *buf)
{
struct v4l2_fh *fh = file->private_data;
struct mtk_jpeg_ctx *ctx = mtk_jpeg_fh_to_ctx(priv);
struct vb2_queue *vq;
struct vb2_buffer *vb;
struct mtk_jpeg_src_buf *jpeg_src_buf;
if (buf->type != V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)
goto end;
vq = v4l2_m2m_get_vq(fh->m2m_ctx, buf->type);
if (buf->index >= vq->num_buffers) {
dev_err(ctx->jpeg->dev, "buffer index out of range\n");
return -EINVAL;
}
vb = vq->bufs[buf->index];
jpeg_src_buf = mtk_jpeg_vb2_to_srcbuf(vb);
jpeg_src_buf->bs_size = buf->m.planes[0].bytesused;
end:
return v4l2_m2m_qbuf(file, fh->m2m_ctx, buf);
}
static const struct v4l2_ioctl_ops mtk_jpeg_enc_ioctl_ops = {
.vidioc_querycap = mtk_jpeg_querycap,
.vidioc_enum_fmt_vid_cap = mtk_jpeg_enum_fmt_vid_cap,
@ -611,6 +636,9 @@ static const struct v4l2_ioctl_ops mtk_jpeg_enc_ioctl_ops = {
.vidioc_streamoff = v4l2_m2m_ioctl_streamoff,
.vidioc_unsubscribe_event = v4l2_event_unsubscribe,
.vidioc_encoder_cmd = v4l2_m2m_ioctl_encoder_cmd,
.vidioc_try_encoder_cmd = v4l2_m2m_ioctl_try_encoder_cmd,
};
static const struct v4l2_ioctl_ops mtk_jpeg_dec_ioctl_ops = {
@ -623,7 +651,7 @@ static const struct v4l2_ioctl_ops mtk_jpeg_dec_ioctl_ops = {
.vidioc_g_fmt_vid_out_mplane = mtk_jpeg_g_fmt_vid_mplane,
.vidioc_s_fmt_vid_cap_mplane = mtk_jpeg_s_fmt_vid_cap_mplane,
.vidioc_s_fmt_vid_out_mplane = mtk_jpeg_s_fmt_vid_out_mplane,
.vidioc_qbuf = v4l2_m2m_ioctl_qbuf,
.vidioc_qbuf = mtk_jpeg_qbuf,
.vidioc_subscribe_event = mtk_jpeg_subscribe_event,
.vidioc_g_selection = mtk_jpeg_dec_g_selection,
@ -637,6 +665,9 @@ static const struct v4l2_ioctl_ops mtk_jpeg_dec_ioctl_ops = {
.vidioc_streamoff = v4l2_m2m_ioctl_streamoff,
.vidioc_unsubscribe_event = v4l2_event_unsubscribe,
.vidioc_decoder_cmd = v4l2_m2m_ioctl_decoder_cmd,
.vidioc_try_decoder_cmd = v4l2_m2m_ioctl_try_decoder_cmd,
};
static int mtk_jpeg_queue_setup(struct vb2_queue *q,
@ -678,7 +709,7 @@ static int mtk_jpeg_buf_prepare(struct vb2_buffer *vb)
{
struct mtk_jpeg_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
struct mtk_jpeg_q_data *q_data = NULL;
struct v4l2_plane_pix_format plane_fmt;
struct v4l2_plane_pix_format plane_fmt = {};
int i;
q_data = mtk_jpeg_get_q_data(ctx, vb->vb2_queue->type);
@ -905,6 +936,148 @@ static int mtk_jpeg_set_dec_dst(struct mtk_jpeg_ctx *ctx,
return 0;
}
static int mtk_jpegenc_get_hw(struct mtk_jpeg_ctx *ctx)
{
struct mtk_jpegenc_comp_dev *comp_jpeg;
struct mtk_jpeg_dev *jpeg = ctx->jpeg;
unsigned long flags;
int hw_id = -1;
int i;
spin_lock_irqsave(&jpeg->hw_lock, flags);
for (i = 0; i < MTK_JPEGENC_HW_MAX; i++) {
comp_jpeg = jpeg->enc_hw_dev[i];
if (comp_jpeg->hw_state == MTK_JPEG_HW_IDLE) {
hw_id = i;
comp_jpeg->hw_state = MTK_JPEG_HW_BUSY;
break;
}
}
spin_unlock_irqrestore(&jpeg->hw_lock, flags);
return hw_id;
}
static int mtk_jpegenc_set_hw_param(struct mtk_jpeg_ctx *ctx,
int hw_id,
struct vb2_v4l2_buffer *src_buf,
struct vb2_v4l2_buffer *dst_buf)
{
struct mtk_jpegenc_comp_dev *jpeg = ctx->jpeg->enc_hw_dev[hw_id];
jpeg->hw_param.curr_ctx = ctx;
jpeg->hw_param.src_buffer = src_buf;
jpeg->hw_param.dst_buffer = dst_buf;
return 0;
}
static int mtk_jpegenc_put_hw(struct mtk_jpeg_dev *jpeg, int hw_id)
{
unsigned long flags;
spin_lock_irqsave(&jpeg->hw_lock, flags);
jpeg->enc_hw_dev[hw_id]->hw_state = MTK_JPEG_HW_IDLE;
spin_unlock_irqrestore(&jpeg->hw_lock, flags);
return 0;
}
static void mtk_jpegenc_worker(struct work_struct *work)
{
struct mtk_jpegenc_comp_dev *comp_jpeg[MTK_JPEGENC_HW_MAX];
enum vb2_buffer_state buf_state = VB2_BUF_STATE_ERROR;
struct mtk_jpeg_src_buf *jpeg_dst_buf;
struct vb2_v4l2_buffer *src_buf, *dst_buf;
int ret, i, hw_id = 0;
unsigned long flags;
struct mtk_jpeg_ctx *ctx = container_of(work,
struct mtk_jpeg_ctx,
jpeg_work);
struct mtk_jpeg_dev *jpeg = ctx->jpeg;
for (i = 0; i < MTK_JPEGENC_HW_MAX; i++)
comp_jpeg[i] = jpeg->enc_hw_dev[i];
i = 0;
retry_select:
hw_id = mtk_jpegenc_get_hw(ctx);
if (hw_id < 0) {
ret = wait_event_interruptible(jpeg->enc_hw_wq,
atomic_read(&jpeg->enchw_rdy) > 0);
if (ret != 0 || (i++ > MTK_JPEG_MAX_RETRY_TIME)) {
dev_err(jpeg->dev, "%s : %d, all HW are busy\n",
__func__, __LINE__);
v4l2_m2m_job_finish(jpeg->m2m_dev, ctx->fh.m2m_ctx);
return;
}
goto retry_select;
}
atomic_dec(&jpeg->enchw_rdy);
src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
if (!src_buf)
goto getbuf_fail;
dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
if (!dst_buf)
goto getbuf_fail;
v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
v4l2_m2m_buf_copy_metadata(src_buf, dst_buf, true);
mtk_jpegenc_set_hw_param(ctx, hw_id, src_buf, dst_buf);
ret = pm_runtime_get_sync(comp_jpeg[hw_id]->dev);
if (ret < 0) {
dev_err(jpeg->dev, "%s : %d, pm_runtime_get_sync fail !!!\n",
__func__, __LINE__);
goto enc_end;
}
ret = clk_prepare_enable(comp_jpeg[hw_id]->venc_clk.clks->clk);
if (ret) {
dev_err(jpeg->dev, "%s : %d, jpegenc clk_prepare_enable fail\n",
__func__, __LINE__);
goto enc_end;
}
schedule_delayed_work(&comp_jpeg[hw_id]->job_timeout_work,
msecs_to_jiffies(MTK_JPEG_HW_TIMEOUT_MSEC));
spin_lock_irqsave(&comp_jpeg[hw_id]->hw_lock, flags);
jpeg_dst_buf = mtk_jpeg_vb2_to_srcbuf(&dst_buf->vb2_buf);
jpeg_dst_buf->curr_ctx = ctx;
jpeg_dst_buf->frame_num = ctx->total_frame_num;
ctx->total_frame_num++;
mtk_jpeg_enc_reset(comp_jpeg[hw_id]->reg_base);
mtk_jpeg_set_enc_dst(ctx,
comp_jpeg[hw_id]->reg_base,
&dst_buf->vb2_buf);
mtk_jpeg_set_enc_src(ctx,
comp_jpeg[hw_id]->reg_base,
&src_buf->vb2_buf);
mtk_jpeg_set_enc_params(ctx, comp_jpeg[hw_id]->reg_base);
mtk_jpeg_enc_start(comp_jpeg[hw_id]->reg_base);
v4l2_m2m_job_finish(jpeg->m2m_dev, ctx->fh.m2m_ctx);
spin_unlock_irqrestore(&comp_jpeg[hw_id]->hw_lock, flags);
return;
enc_end:
v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
v4l2_m2m_buf_done(src_buf, buf_state);
v4l2_m2m_buf_done(dst_buf, buf_state);
getbuf_fail:
atomic_inc(&jpeg->enchw_rdy);
mtk_jpegenc_put_hw(jpeg, hw_id);
v4l2_m2m_job_finish(jpeg->m2m_dev, ctx->fh.m2m_ctx);
}
static void mtk_jpeg_enc_device_run(void *priv)
{
struct mtk_jpeg_ctx *ctx = priv;
@ -922,7 +1095,7 @@ static void mtk_jpeg_enc_device_run(void *priv)
goto enc_end;
schedule_delayed_work(&jpeg->job_timeout_work,
msecs_to_jiffies(MTK_JPEG_HW_TIMEOUT_MSEC));
msecs_to_jiffies(MTK_JPEG_HW_TIMEOUT_MSEC));
spin_lock_irqsave(&jpeg->hw_lock, flags);
@ -947,6 +1120,189 @@ enc_end:
v4l2_m2m_job_finish(jpeg->m2m_dev, ctx->fh.m2m_ctx);
}
static void mtk_jpeg_multicore_enc_device_run(void *priv)
{
struct mtk_jpeg_ctx *ctx = priv;
struct mtk_jpeg_dev *jpeg = ctx->jpeg;
queue_work(jpeg->workqueue, &ctx->jpeg_work);
}
static int mtk_jpegdec_get_hw(struct mtk_jpeg_ctx *ctx)
{
struct mtk_jpegdec_comp_dev *comp_jpeg;
struct mtk_jpeg_dev *jpeg = ctx->jpeg;
unsigned long flags;
int hw_id = -1;
int i;
spin_lock_irqsave(&jpeg->hw_lock, flags);
for (i = 0; i < MTK_JPEGDEC_HW_MAX; i++) {
comp_jpeg = jpeg->dec_hw_dev[i];
if (comp_jpeg->hw_state == MTK_JPEG_HW_IDLE) {
hw_id = i;
comp_jpeg->hw_state = MTK_JPEG_HW_BUSY;
break;
}
}
spin_unlock_irqrestore(&jpeg->hw_lock, flags);
return hw_id;
}
static int mtk_jpegdec_put_hw(struct mtk_jpeg_dev *jpeg, int hw_id)
{
unsigned long flags;
spin_lock_irqsave(&jpeg->hw_lock, flags);
jpeg->dec_hw_dev[hw_id]->hw_state =
MTK_JPEG_HW_IDLE;
spin_unlock_irqrestore(&jpeg->hw_lock, flags);
return 0;
}
static int mtk_jpegdec_set_hw_param(struct mtk_jpeg_ctx *ctx,
int hw_id,
struct vb2_v4l2_buffer *src_buf,
struct vb2_v4l2_buffer *dst_buf)
{
struct mtk_jpegdec_comp_dev *jpeg =
ctx->jpeg->dec_hw_dev[hw_id];
jpeg->hw_param.curr_ctx = ctx;
jpeg->hw_param.src_buffer = src_buf;
jpeg->hw_param.dst_buffer = dst_buf;
return 0;
}
static void mtk_jpegdec_worker(struct work_struct *work)
{
struct mtk_jpeg_ctx *ctx = container_of(work, struct mtk_jpeg_ctx,
jpeg_work);
struct mtk_jpegdec_comp_dev *comp_jpeg[MTK_JPEGDEC_HW_MAX];
enum vb2_buffer_state buf_state = VB2_BUF_STATE_ERROR;
struct mtk_jpeg_src_buf *jpeg_src_buf, *jpeg_dst_buf;
struct vb2_v4l2_buffer *src_buf, *dst_buf;
struct mtk_jpeg_dev *jpeg = ctx->jpeg;
int ret, i, hw_id = 0;
struct mtk_jpeg_bs bs;
struct mtk_jpeg_fb fb;
unsigned long flags;
for (i = 0; i < MTK_JPEGDEC_HW_MAX; i++)
comp_jpeg[i] = jpeg->dec_hw_dev[i];
i = 0;
retry_select:
hw_id = mtk_jpegdec_get_hw(ctx);
if (hw_id < 0) {
ret = wait_event_interruptible_timeout(jpeg->dec_hw_wq,
atomic_read(&jpeg->dechw_rdy) > 0,
MTK_JPEG_HW_TIMEOUT_MSEC);
if (ret != 0 || (i++ > MTK_JPEG_MAX_RETRY_TIME)) {
dev_err(jpeg->dev, "%s : %d, all HW are busy\n",
__func__, __LINE__);
v4l2_m2m_job_finish(jpeg->m2m_dev, ctx->fh.m2m_ctx);
return;
}
goto retry_select;
}
atomic_dec(&jpeg->dechw_rdy);
src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
if (!src_buf)
goto getbuf_fail;
dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
if (!dst_buf)
goto getbuf_fail;
v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
v4l2_m2m_buf_copy_metadata(src_buf, dst_buf, true);
jpeg_src_buf = mtk_jpeg_vb2_to_srcbuf(&src_buf->vb2_buf);
jpeg_dst_buf = mtk_jpeg_vb2_to_srcbuf(&dst_buf->vb2_buf);
if (mtk_jpeg_check_resolution_change(ctx,
&jpeg_src_buf->dec_param)) {
mtk_jpeg_queue_src_chg_event(ctx);
ctx->state = MTK_JPEG_SOURCE_CHANGE;
goto dec_end;
}
jpeg_src_buf->curr_ctx = ctx;
jpeg_src_buf->frame_num = ctx->total_frame_num;
jpeg_dst_buf->curr_ctx = ctx;
jpeg_dst_buf->frame_num = ctx->total_frame_num;
mtk_jpegdec_set_hw_param(ctx, hw_id, src_buf, dst_buf);
ret = pm_runtime_get_sync(comp_jpeg[hw_id]->dev);
if (ret < 0) {
dev_err(jpeg->dev, "%s : %d, pm_runtime_get_sync fail !!!\n",
__func__, __LINE__);
goto dec_end;
}
ret = clk_prepare_enable(comp_jpeg[hw_id]->jdec_clk.clks->clk);
if (ret) {
dev_err(jpeg->dev, "%s : %d, jpegdec clk_prepare_enable fail\n",
__func__, __LINE__);
goto clk_end;
}
schedule_delayed_work(&comp_jpeg[hw_id]->job_timeout_work,
msecs_to_jiffies(MTK_JPEG_HW_TIMEOUT_MSEC));
mtk_jpeg_set_dec_src(ctx, &src_buf->vb2_buf, &bs);
if (mtk_jpeg_set_dec_dst(ctx,
&jpeg_src_buf->dec_param,
&dst_buf->vb2_buf, &fb)) {
dev_err(jpeg->dev, "%s : %d, mtk_jpeg_set_dec_dst fail\n",
__func__, __LINE__);
goto setdst_end;
}
spin_lock_irqsave(&comp_jpeg[hw_id]->hw_lock, flags);
ctx->total_frame_num++;
mtk_jpeg_dec_reset(comp_jpeg[hw_id]->reg_base);
mtk_jpeg_dec_set_config(comp_jpeg[hw_id]->reg_base,
&jpeg_src_buf->dec_param,
jpeg_src_buf->bs_size,
&bs,
&fb);
mtk_jpeg_dec_start(comp_jpeg[hw_id]->reg_base);
v4l2_m2m_job_finish(jpeg->m2m_dev, ctx->fh.m2m_ctx);
spin_unlock_irqrestore(&comp_jpeg[hw_id]->hw_lock, flags);
return;
setdst_end:
clk_disable_unprepare(comp_jpeg[hw_id]->jdec_clk.clks->clk);
clk_end:
pm_runtime_put(comp_jpeg[hw_id]->dev);
dec_end:
v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
v4l2_m2m_buf_done(src_buf, buf_state);
v4l2_m2m_buf_done(dst_buf, buf_state);
getbuf_fail:
atomic_inc(&jpeg->dechw_rdy);
mtk_jpegdec_put_hw(jpeg, hw_id);
v4l2_m2m_job_finish(jpeg->m2m_dev, ctx->fh.m2m_ctx);
}
static void mtk_jpeg_multicore_dec_device_run(void *priv)
{
struct mtk_jpeg_ctx *ctx = priv;
struct mtk_jpeg_dev *jpeg = ctx->jpeg;
queue_work(jpeg->workqueue, &ctx->jpeg_work);
}
static void mtk_jpeg_dec_device_run(void *priv)
{
struct mtk_jpeg_ctx *ctx = priv;
@ -984,8 +1340,10 @@ static void mtk_jpeg_dec_device_run(void *priv)
spin_lock_irqsave(&jpeg->hw_lock, flags);
mtk_jpeg_dec_reset(jpeg->reg_base);
mtk_jpeg_dec_set_config(jpeg->reg_base,
&jpeg_src_buf->dec_param, &bs, &fb);
&jpeg_src_buf->dec_param,
jpeg_src_buf->bs_size,
&bs,
&fb);
mtk_jpeg_dec_start(jpeg->reg_base);
spin_unlock_irqrestore(&jpeg->hw_lock, flags);
return;
@ -1009,6 +1367,14 @@ static const struct v4l2_m2m_ops mtk_jpeg_enc_m2m_ops = {
.device_run = mtk_jpeg_enc_device_run,
};
static const struct v4l2_m2m_ops mtk_jpeg_multicore_enc_m2m_ops = {
.device_run = mtk_jpeg_multicore_enc_device_run,
};
static const struct v4l2_m2m_ops mtk_jpeg_multicore_dec_m2m_ops = {
.device_run = mtk_jpeg_multicore_dec_device_run,
};
static const struct v4l2_m2m_ops mtk_jpeg_dec_m2m_ops = {
.device_run = mtk_jpeg_dec_device_run,
.job_ready = mtk_jpeg_dec_job_ready,
@ -1209,6 +1575,14 @@ static int mtk_jpeg_open(struct file *file)
goto free;
}
if (jpeg->is_jpgenc_multihw)
INIT_WORK(&ctx->jpeg_work, mtk_jpegenc_worker);
if (jpeg->is_jpgdec_multihw)
INIT_WORK(&ctx->jpeg_work, mtk_jpegdec_worker);
INIT_LIST_HEAD(&ctx->dst_done_queue);
spin_lock_init(&ctx->done_queue_lock);
v4l2_fh_init(&ctx->fh, vfd);
file->private_data = &ctx->fh;
v4l2_fh_add(&ctx->fh);
@ -1230,6 +1604,7 @@ static int mtk_jpeg_open(struct file *file)
} else {
v4l2_ctrl_handler_init(&ctx->ctrl_hdl, 0);
}
mtk_jpeg_set_default_params(ctx);
mutex_unlock(&jpeg->lock);
return 0;
@ -1310,38 +1685,51 @@ static int mtk_jpeg_probe(struct platform_device *pdev)
spin_lock_init(&jpeg->hw_lock);
jpeg->dev = &pdev->dev;
jpeg->variant = of_device_get_match_data(jpeg->dev);
INIT_DELAYED_WORK(&jpeg->job_timeout_work, mtk_jpeg_job_timeout_work);
jpeg->reg_base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(jpeg->reg_base)) {
ret = PTR_ERR(jpeg->reg_base);
return ret;
ret = devm_of_platform_populate(&pdev->dev);
if (ret) {
v4l2_err(&jpeg->v4l2_dev, "Master of platform populate failed.");
return -EINVAL;
}
jpeg_irq = platform_get_irq(pdev, 0);
if (jpeg_irq < 0)
return jpeg_irq;
if (list_empty(&pdev->dev.devres_head)) {
INIT_DELAYED_WORK(&jpeg->job_timeout_work,
mtk_jpeg_job_timeout_work);
ret = devm_request_irq(&pdev->dev, jpeg_irq,
jpeg->variant->irq_handler, 0, pdev->name, jpeg);
if (ret) {
dev_err(&pdev->dev, "Failed to request jpeg_irq %d (%d)\n",
jpeg_irq, ret);
goto err_req_irq;
}
jpeg->reg_base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(jpeg->reg_base)) {
ret = PTR_ERR(jpeg->reg_base);
return ret;
}
ret = devm_clk_bulk_get(jpeg->dev, jpeg->variant->num_clks,
jpeg->variant->clks);
if (ret) {
dev_err(&pdev->dev, "Failed to init clk, err %d\n", ret);
goto err_clk_init;
jpeg_irq = platform_get_irq(pdev, 0);
if (jpeg_irq < 0)
return jpeg_irq;
ret = devm_request_irq(&pdev->dev,
jpeg_irq,
jpeg->variant->irq_handler,
0,
pdev->name, jpeg);
if (ret) {
dev_err(&pdev->dev, "Failed to request jpeg_irq %d (%d)\n",
jpeg_irq, ret);
return ret;
}
ret = devm_clk_bulk_get(jpeg->dev,
jpeg->variant->num_clks,
jpeg->variant->clks);
if (ret) {
dev_err(&pdev->dev, "Failed to init clk\n");
return ret;
}
}
ret = v4l2_device_register(&pdev->dev, &jpeg->v4l2_dev);
if (ret) {
dev_err(&pdev->dev, "Failed to register v4l2 device\n");
ret = -EINVAL;
goto err_dev_register;
return -EINVAL;
}
jpeg->m2m_dev = v4l2_m2m_init(jpeg->variant->m2m_ops);
@ -1399,12 +1787,6 @@ err_vfd_jpeg_alloc:
err_m2m_init:
v4l2_device_unregister(&jpeg->v4l2_dev);
err_dev_register:
err_clk_init:
err_req_irq:
return ret;
}
@ -1494,6 +1876,29 @@ static const struct mtk_jpeg_variant mtk_jpeg_drvdata = {
.cap_q_default_fourcc = V4L2_PIX_FMT_JPEG,
};
static struct mtk_jpeg_variant mtk8195_jpegenc_drvdata = {
.formats = mtk_jpeg_enc_formats,
.num_formats = MTK_JPEG_ENC_NUM_FORMATS,
.qops = &mtk_jpeg_enc_qops,
.m2m_ops = &mtk_jpeg_multicore_enc_m2m_ops,
.dev_name = "mtk-jpeg-enc",
.ioctl_ops = &mtk_jpeg_enc_ioctl_ops,
.out_q_default_fourcc = V4L2_PIX_FMT_YUYV,
.cap_q_default_fourcc = V4L2_PIX_FMT_JPEG,
};
static const struct mtk_jpeg_variant mtk8195_jpegdec_drvdata = {
.formats = mtk_jpeg_dec_formats,
.num_formats = MTK_JPEG_DEC_NUM_FORMATS,
.qops = &mtk_jpeg_dec_qops,
.m2m_ops = &mtk_jpeg_multicore_dec_m2m_ops,
.dev_name = "mtk-jpeg-dec",
.ioctl_ops = &mtk_jpeg_dec_ioctl_ops,
.out_q_default_fourcc = V4L2_PIX_FMT_JPEG,
.cap_q_default_fourcc = V4L2_PIX_FMT_YUV420M,
};
#if defined(CONFIG_OF)
static const struct of_device_id mtk_jpeg_match[] = {
{
.compatible = "mediatek,mt8173-jpgdec",
@ -1507,17 +1912,26 @@ static const struct of_device_id mtk_jpeg_match[] = {
.compatible = "mediatek,mtk-jpgenc",
.data = &mtk_jpeg_drvdata,
},
{
.compatible = "mediatek,mt8195-jpgenc",
.data = &mtk8195_jpegenc_drvdata,
},
{
.compatible = "mediatek,mt8195-jpgdec",
.data = &mtk8195_jpegdec_drvdata,
},
{},
};
MODULE_DEVICE_TABLE(of, mtk_jpeg_match);
#endif
static struct platform_driver mtk_jpeg_driver = {
.probe = mtk_jpeg_probe,
.remove = mtk_jpeg_remove,
.driver = {
.name = MTK_JPEG_NAME,
.of_match_table = mtk_jpeg_match,
.of_match_table = of_match_ptr(mtk_jpeg_match),
.pm = &mtk_jpeg_pm_ops,
},
};

169
drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h
View File

@ -9,15 +9,17 @@
#ifndef _MTK_JPEG_CORE_H
#define _MTK_JPEG_CORE_H
#include <linux/clk.h>
#include <linux/interrupt.h>
#include <media/v4l2-ctrls.h>
#include <media/v4l2-device.h>
#include <media/v4l2-fh.h>
#include <media/videobuf2-v4l2.h>
#include "mtk_jpeg_dec_hw.h"
#define MTK_JPEG_NAME "mtk-jpeg"
#define MTK_JPEG_COMP_MAX 3
#define MTK_JPEG_FMT_FLAG_OUTPUT BIT(0)
#define MTK_JPEG_FMT_FLAG_CAPTURE BIT(1)
@ -74,6 +76,115 @@ struct mtk_jpeg_variant {
u32 cap_q_default_fourcc;
};
struct mtk_jpeg_src_buf {
u32 frame_num;
struct vb2_v4l2_buffer b;
struct list_head list;
u32 bs_size;
struct mtk_jpeg_dec_param dec_param;
struct mtk_jpeg_ctx *curr_ctx;
};
enum mtk_jpeg_hw_state {
MTK_JPEG_HW_IDLE = 0,
MTK_JPEG_HW_BUSY = 1,
};
struct mtk_jpeg_hw_param {
struct vb2_v4l2_buffer *src_buffer;
struct vb2_v4l2_buffer *dst_buffer;
struct mtk_jpeg_ctx *curr_ctx;
};
enum mtk_jpegenc_hw_id {
MTK_JPEGENC_HW0,
MTK_JPEGENC_HW1,
MTK_JPEGENC_HW_MAX,
};
enum mtk_jpegdec_hw_id {
MTK_JPEGDEC_HW0,
MTK_JPEGDEC_HW1,
MTK_JPEGDEC_HW2,
MTK_JPEGDEC_HW_MAX,
};
/**
* struct mtk_jpegenc_clk - Structure used to store vcodec clock information
* @clks: JPEG encode clock
* @clk_num: JPEG encode clock numbers
*/
struct mtk_jpegenc_clk {
struct clk_bulk_data *clks;
int clk_num;
};
/**
* struct mtk_jpegdec_clk - Structure used to store vcodec clock information
* @clks: JPEG decode clock
* @clk_num: JPEG decode clock numbers
*/
struct mtk_jpegdec_clk {
struct clk_bulk_data *clks;
int clk_num;
};
/**
* struct mtk_jpegenc_comp_dev - JPEG COREX abstraction
* @dev: JPEG device
* @plat_dev: platform device data
* @reg_base: JPEG registers mapping
* @master_dev: mtk_jpeg_dev device
* @venc_clk: jpeg encode clock
* @jpegenc_irq: jpeg encode irq num
* @job_timeout_work: encode timeout workqueue
* @hw_param: jpeg encode hw parameters
* @hw_rdy: record hw ready
* @hw_state: record hw state
* @hw_lock: spinlock protecting the hw device resource
*/
struct mtk_jpegenc_comp_dev {
struct device *dev;
struct platform_device *plat_dev;
void __iomem *reg_base;
struct mtk_jpeg_dev *master_dev;
struct mtk_jpegenc_clk venc_clk;
int jpegenc_irq;
struct delayed_work job_timeout_work;
struct mtk_jpeg_hw_param hw_param;
enum mtk_jpeg_hw_state hw_state;
/* spinlock protecting the hw device resource */
spinlock_t hw_lock;
};
/**
* struct mtk_jpegdec_comp_dev - JPEG COREX abstraction
* @dev: JPEG device
* @plat_dev: platform device data
* @reg_base: JPEG registers mapping
* @master_dev: mtk_jpeg_dev device
* @jdec_clk: mtk_jpegdec_clk
* @jpegdec_irq: jpeg decode irq num
* @job_timeout_work: decode timeout workqueue
* @hw_param: jpeg decode hw parameters
* @hw_state: record hw state
* @hw_lock: spinlock protecting hw
*/
struct mtk_jpegdec_comp_dev {
struct device *dev;
struct platform_device *plat_dev;
void __iomem *reg_base;
struct mtk_jpeg_dev *master_dev;
struct mtk_jpegdec_clk jdec_clk;
int jpegdec_irq;
struct delayed_work job_timeout_work;
struct mtk_jpeg_hw_param hw_param;
enum mtk_jpeg_hw_state hw_state;
/* spinlock protecting the hw device resource */
spinlock_t hw_lock;
};
/**
* struct mtk_jpeg_dev - JPEG IP abstraction
* @lock: the mutex protecting this structure
@ -87,6 +198,17 @@ struct mtk_jpeg_variant {
* @reg_base: JPEG registers mapping
* @job_timeout_work: IRQ timeout structure
* @variant: driver variant to be used
* @reg_encbase: jpg encode register base addr
* @enc_hw_dev: jpg encode hardware device
* @is_jpgenc_multihw: the flag of multi-hw core
* @enc_hw_wq: jpg encode wait queue
* @enchw_rdy: jpg encode hw ready flag
* @reg_decbase: jpg decode register base addr
* @dec_hw_dev: jpg decode hardware device
* @is_jpgdec_multihw: the flag of dec multi-hw core
* @dec_hw_wq: jpg decode wait queue
* @dec_workqueue: jpg decode work queue
* @dechw_rdy: jpg decode hw ready flag
*/
struct mtk_jpeg_dev {
struct mutex lock;
@ -100,6 +222,19 @@ struct mtk_jpeg_dev {
void __iomem *reg_base;
struct delayed_work job_timeout_work;
const struct mtk_jpeg_variant *variant;
void __iomem *reg_encbase[MTK_JPEGENC_HW_MAX];
struct mtk_jpegenc_comp_dev *enc_hw_dev[MTK_JPEGENC_HW_MAX];
bool is_jpgenc_multihw;
wait_queue_head_t enc_hw_wq;
atomic_t enchw_rdy;
void __iomem *reg_decbase[MTK_JPEGDEC_HW_MAX];
struct mtk_jpegdec_comp_dev *dec_hw_dev[MTK_JPEGDEC_HW_MAX];
bool is_jpgdec_multihw;
wait_queue_head_t dec_hw_wq;
struct workqueue_struct *dec_workqueue;
atomic_t dechw_rdy;
};
/**
@ -138,15 +273,20 @@ struct mtk_jpeg_q_data {
/**
* struct mtk_jpeg_ctx - the device context data
* @jpeg: JPEG IP device for this context
* @out_q: source (output) queue information
* @cap_q: destination (capture) queue queue information
* @fh: V4L2 file handle
* @state: state of the context
* @enable_exif: enable exif mode of jpeg encoder
* @enc_quality: jpeg encoder quality
* @restart_interval: jpeg encoder restart interval
* @ctrl_hdl: controls handler
* @jpeg: JPEG IP device for this context
* @out_q: source (output) queue information
* @cap_q: destination queue information
* @fh: V4L2 file handle
* @state: state of the context
* @enable_exif: enable exif mode of jpeg encoder
* @enc_quality: jpeg encoder quality
* @restart_interval: jpeg encoder restart interval
* @ctrl_hdl: controls handler
* @jpeg_work: jpeg encoder workqueue
* @total_frame_num: encoded frame number
* @dst_done_queue: encoded frame buffer queue
* @done_queue_lock: encoded frame operation spinlock
* @last_done_frame_num: the last encoded frame number
*/
struct mtk_jpeg_ctx {
struct mtk_jpeg_dev *jpeg;
@ -158,6 +298,13 @@ struct mtk_jpeg_ctx {
u8 enc_quality;
u8 restart_interval;
struct v4l2_ctrl_handler ctrl_hdl;
struct work_struct jpeg_work;
u32 total_frame_num;
struct list_head dst_done_queue;
/* spinlock protecting the encode done buffer */
spinlock_t done_queue_lock;
u32 last_done_frame_num;
};
#endif /* _MTK_JPEG_CORE_H */

313
drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
View File

@ -5,10 +5,26 @@
* Rick Chang <rick.chang@mediatek.com>
*/
#include <linux/clk.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pm_runtime.h>
#include <linux/slab.h>
#include <media/media-device.h>
#include <media/videobuf2-core.h>
#include <media/videobuf2-v4l2.h>
#include <media/v4l2-mem2mem.h>
#include <media/v4l2-dev.h>
#include <media/v4l2-device.h>
#include <media/v4l2-fh.h>
#include <media/v4l2-event.h>
#include "mtk_jpeg_core.h"
#include "mtk_jpeg_dec_hw.h"
#define MTK_JPEG_DUNUM_MASK(val) (((val) - 1) & 0x3)
@ -23,6 +39,16 @@ enum mtk_jpeg_color {
MTK_JPEG_COLOR_400 = 0x00110000
};
#if defined(CONFIG_OF)
static const struct of_device_id mtk_jpegdec_hw_ids[] = {
{
.compatible = "mediatek,mt8195-jpgdec-hw",
},
{},
};
MODULE_DEVICE_TABLE(of, mtk_jpegdec_hw_ids);
#endif
static inline int mtk_jpeg_verify_align(u32 val, int align, u32 reg)
{
if (val & (align - 1)) {
@ -188,6 +214,7 @@ int mtk_jpeg_dec_fill_param(struct mtk_jpeg_dec_param *param)
return 0;
}
EXPORT_SYMBOL_GPL(mtk_jpeg_dec_fill_param);
u32 mtk_jpeg_dec_get_int_status(void __iomem *base)
{
@ -199,6 +226,7 @@ u32 mtk_jpeg_dec_get_int_status(void __iomem *base)
return ret;
}
EXPORT_SYMBOL_GPL(mtk_jpeg_dec_get_int_status);
u32 mtk_jpeg_dec_enum_result(u32 irq_result)
{
@ -215,11 +243,13 @@ u32 mtk_jpeg_dec_enum_result(u32 irq_result)
return MTK_JPEG_DEC_RESULT_ERROR_UNKNOWN;
}
EXPORT_SYMBOL_GPL(mtk_jpeg_dec_enum_result);
void mtk_jpeg_dec_start(void __iomem *base)
{
writel(0, base + JPGDEC_REG_TRIG);
}
EXPORT_SYMBOL_GPL(mtk_jpeg_dec_start);
static void mtk_jpeg_dec_soft_reset(void __iomem *base)
{
@ -239,6 +269,7 @@ void mtk_jpeg_dec_reset(void __iomem *base)
mtk_jpeg_dec_soft_reset(base);
mtk_jpeg_dec_hard_reset(base);
}
EXPORT_SYMBOL_GPL(mtk_jpeg_dec_reset);
static void mtk_jpeg_dec_set_brz_factor(void __iomem *base, u8 yscale_w,
u8 yscale_h, u8 uvscale_w, u8 uvscale_h)
@ -299,12 +330,14 @@ static void mtk_jpeg_dec_set_bs_write_ptr(void __iomem *base, u32 ptr)
writel(ptr, base + JPGDEC_REG_FILE_BRP);
}
static void mtk_jpeg_dec_set_bs_info(void __iomem *base, u32 addr, u32 size)
static void mtk_jpeg_dec_set_bs_info(void __iomem *base, u32 addr, u32 size,
u32 bitstream_size)
{
mtk_jpeg_verify_align(addr, 16, JPGDEC_REG_FILE_ADDR);
mtk_jpeg_verify_align(size, 128, JPGDEC_REG_FILE_TOTAL_SIZE);
writel(addr, base + JPGDEC_REG_FILE_ADDR);
writel(size, base + JPGDEC_REG_FILE_TOTAL_SIZE);
writel(bitstream_size, base + JPGDEC_REG_BIT_STREAM_SIZE);
}
static void mtk_jpeg_dec_set_comp_id(void __iomem *base, u32 id_y, u32 id_u,
@ -373,37 +406,265 @@ static void mtk_jpeg_dec_set_sampling_factor(void __iomem *base, u32 comp_num,
}
void mtk_jpeg_dec_set_config(void __iomem *base,
struct mtk_jpeg_dec_param *config,
struct mtk_jpeg_dec_param *cfg,
u32 bitstream_size,
struct mtk_jpeg_bs *bs,
struct mtk_jpeg_fb *fb)
{
mtk_jpeg_dec_set_brz_factor(base, 0, 0, config->uv_brz_w, 0);
mtk_jpeg_dec_set_brz_factor(base, 0, 0, cfg->uv_brz_w, 0);
mtk_jpeg_dec_set_dec_mode(base, 0);
mtk_jpeg_dec_set_comp0_du(base, config->unit_num);
mtk_jpeg_dec_set_total_mcu(base, config->total_mcu);
mtk_jpeg_dec_set_bs_info(base, bs->str_addr, bs->size);
mtk_jpeg_dec_set_comp0_du(base, cfg->unit_num);
mtk_jpeg_dec_set_total_mcu(base, cfg->total_mcu);
mtk_jpeg_dec_set_bs_info(base, bs->str_addr, bs->size, bitstream_size);
mtk_jpeg_dec_set_bs_write_ptr(base, bs->end_addr);
mtk_jpeg_dec_set_du_membership(base, config->membership, 1,
(config->comp_num == 1) ? 1 : 0);
mtk_jpeg_dec_set_comp_id(base, config->comp_id[0], config->comp_id[1],
config->comp_id[2]);
mtk_jpeg_dec_set_q_table(base, config->qtbl_num[0],
config->qtbl_num[1], config->qtbl_num[2]);
mtk_jpeg_dec_set_sampling_factor(base, config->comp_num,
config->sampling_w[0],
config->sampling_h[0],
config->sampling_w[1],
config->sampling_h[1],
config->sampling_w[2],
config->sampling_h[2]);
mtk_jpeg_dec_set_mem_stride(base, config->mem_stride[0],
config->mem_stride[1]);
mtk_jpeg_dec_set_img_stride(base, config->img_stride[0],
config->img_stride[1]);
mtk_jpeg_dec_set_du_membership(base, cfg->membership, 1,
(cfg->comp_num == 1) ? 1 : 0);
mtk_jpeg_dec_set_comp_id(base, cfg->comp_id[0], cfg->comp_id[1],
cfg->comp_id[2]);
mtk_jpeg_dec_set_q_table(base, cfg->qtbl_num[0],
cfg->qtbl_num[1], cfg->qtbl_num[2]);
mtk_jpeg_dec_set_sampling_factor(base, cfg->comp_num,
cfg->sampling_w[0],
cfg->sampling_h[0],
cfg->sampling_w[1],
cfg->sampling_h[1],
cfg->sampling_w[2],
cfg->sampling_h[2]);
mtk_jpeg_dec_set_mem_stride(base, cfg->mem_stride[0],
cfg->mem_stride[1]);
mtk_jpeg_dec_set_img_stride(base, cfg->img_stride[0],
cfg->img_stride[1]);
mtk_jpeg_dec_set_dst_bank0(base, fb->plane_addr[0],
fb->plane_addr[1], fb->plane_addr[2]);
mtk_jpeg_dec_set_dst_bank1(base, 0, 0, 0);
mtk_jpeg_dec_set_dma_group(base, config->dma_mcu, config->dma_group,
config->dma_last_mcu);
mtk_jpeg_dec_set_pause_mcu_idx(base, config->total_mcu);
mtk_jpeg_dec_set_dma_group(base, cfg->dma_mcu, cfg->dma_group,
cfg->dma_last_mcu);
mtk_jpeg_dec_set_pause_mcu_idx(base, cfg->total_mcu);
}
EXPORT_SYMBOL_GPL(mtk_jpeg_dec_set_config);
static void mtk_jpegdec_put_buf(struct mtk_jpegdec_comp_dev *jpeg)
{
struct mtk_jpeg_src_buf *dst_done_buf, *tmp_dst_done_buf;
struct vb2_v4l2_buffer *dst_buffer;
struct list_head *temp_entry;
struct list_head *pos = NULL;
struct mtk_jpeg_ctx *ctx;
unsigned long flags;
ctx = jpeg->hw_param.curr_ctx;
if (unlikely(!ctx)) {
dev_err(jpeg->dev, "comp_jpeg ctx fail !!!\n");
return;
}
dst_buffer = jpeg->hw_param.dst_buffer;
if (!dst_buffer) {
dev_err(jpeg->dev, "comp_jpeg dst_buffer fail !!!\n");
return;
}
dst_done_buf = container_of(dst_buffer, struct mtk_jpeg_src_buf, b);
spin_lock_irqsave(&ctx->done_queue_lock, flags);
list_add_tail(&dst_done_buf->list, &ctx->dst_done_queue);
while (!list_empty(&ctx->dst_done_queue) &&
(pos != &ctx->dst_done_queue)) {
list_for_each_prev_safe(pos, temp_entry, &ctx->dst_done_queue) {
tmp_dst_done_buf = list_entry(pos,
struct mtk_jpeg_src_buf,
list);
if (tmp_dst_done_buf->frame_num ==
ctx->last_done_frame_num) {
list_del(&tmp_dst_done_buf->list);
v4l2_m2m_buf_done(&tmp_dst_done_buf->b,
VB2_BUF_STATE_DONE);
ctx->last_done_frame_num++;
}
}
}
spin_unlock_irqrestore(&ctx->done_queue_lock, flags);
}
static void mtk_jpegdec_timeout_work(struct work_struct *work)
{
enum vb2_buffer_state buf_state = VB2_BUF_STATE_ERROR;
struct mtk_jpegdec_comp_dev *cjpeg =
container_of(work, struct mtk_jpegdec_comp_dev,
job_timeout_work.work);
struct mtk_jpeg_dev *master_jpeg = cjpeg->master_dev;
struct vb2_v4l2_buffer *src_buf, *dst_buf;
src_buf = cjpeg->hw_param.src_buffer;
dst_buf = cjpeg->hw_param.dst_buffer;
v4l2_m2m_buf_copy_metadata(src_buf, dst_buf, true);
mtk_jpeg_dec_reset(cjpeg->reg_base);
clk_disable_unprepare(cjpeg->jdec_clk.clks->clk);
pm_runtime_put(cjpeg->dev);
cjpeg->hw_state = MTK_JPEG_HW_IDLE;
atomic_inc(&master_jpeg->dechw_rdy);
wake_up(&master_jpeg->dec_hw_wq);
v4l2_m2m_buf_done(src_buf, buf_state);
mtk_jpegdec_put_buf(cjpeg);
}
static irqreturn_t mtk_jpegdec_hw_irq_handler(int irq, void *priv)
{
struct vb2_v4l2_buffer *src_buf, *dst_buf;
struct mtk_jpeg_src_buf *jpeg_src_buf;
enum vb2_buffer_state buf_state;
struct mtk_jpeg_ctx *ctx;
u32 dec_irq_ret;
u32 irq_status;
int i;
struct mtk_jpegdec_comp_dev *jpeg = priv;
struct mtk_jpeg_dev *master_jpeg = jpeg->master_dev;
cancel_delayed_work(&jpeg->job_timeout_work);
ctx = jpeg->hw_param.curr_ctx;
src_buf = jpeg->hw_param.src_buffer;
dst_buf = jpeg->hw_param.dst_buffer;
v4l2_m2m_buf_copy_metadata(src_buf, dst_buf, true);
irq_status = mtk_jpeg_dec_get_int_status(jpeg->reg_base);
dec_irq_ret = mtk_jpeg_dec_enum_result(irq_status);
if (dec_irq_ret >= MTK_JPEG_DEC_RESULT_UNDERFLOW)
mtk_jpeg_dec_reset(jpeg->reg_base);
if (dec_irq_ret != MTK_JPEG_DEC_RESULT_EOF_DONE)
dev_warn(jpeg->dev, "Jpg Dec occurs unknown Err.");
jpeg_src_buf =
container_of(src_buf, struct mtk_jpeg_src_buf, b);
for (i = 0; i < dst_buf->vb2_buf.num_planes; i++)
vb2_set_plane_payload(&dst_buf->vb2_buf, i,
jpeg_src_buf->dec_param.comp_size[i]);
buf_state = VB2_BUF_STATE_DONE;
v4l2_m2m_buf_done(src_buf, buf_state);
mtk_jpegdec_put_buf(jpeg);
pm_runtime_put(ctx->jpeg->dev);
clk_disable_unprepare(jpeg->jdec_clk.clks->clk);
jpeg->hw_state = MTK_JPEG_HW_IDLE;
wake_up(&master_jpeg->dec_hw_wq);
atomic_inc(&master_jpeg->dechw_rdy);
return IRQ_HANDLED;
}
static int mtk_jpegdec_hw_init_irq(struct mtk_jpegdec_comp_dev *dev)
{
struct platform_device *pdev = dev->plat_dev;
int ret;
dev->jpegdec_irq = platform_get_irq(pdev, 0);
if (dev->jpegdec_irq < 0)
return dev->jpegdec_irq;
ret = devm_request_irq(&pdev->dev,
dev->jpegdec_irq,
mtk_jpegdec_hw_irq_handler,
0,
pdev->name, dev);
if (ret) {
dev_err(&pdev->dev, "Failed to devm_request_irq %d (%d)",
dev->jpegdec_irq, ret);
return ret;
}
return 0;
}
static int mtk_jpegdec_hw_probe(struct platform_device *pdev)
{
struct mtk_jpegdec_clk *jpegdec_clk;
struct mtk_jpeg_dev *master_dev;
struct mtk_jpegdec_comp_dev *dev;
int ret, i;
struct device *decs = &pdev->dev;
if (!decs->parent)
return -EPROBE_DEFER;
master_dev = dev_get_drvdata(decs->parent);
if (!master_dev)
return -EPROBE_DEFER;
dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
if (!dev)
return -ENOMEM;
dev->plat_dev = pdev;
dev->dev = &pdev->dev;
if (!master_dev->is_jpgdec_multihw) {
master_dev->is_jpgdec_multihw = true;
for (i = 0; i < MTK_JPEGDEC_HW_MAX; i++)
master_dev->dec_hw_dev[i] = NULL;
init_waitqueue_head(&master_dev->dec_hw_wq);
master_dev->workqueue = alloc_ordered_workqueue(MTK_JPEG_NAME,
WQ_MEM_RECLAIM
| WQ_FREEZABLE);
if (!master_dev->workqueue)
return -EINVAL;
}
atomic_set(&master_dev->dechw_rdy, MTK_JPEGDEC_HW_MAX);
spin_lock_init(&dev->hw_lock);
dev->hw_state = MTK_JPEG_HW_IDLE;
INIT_DELAYED_WORK(&dev->job_timeout_work,
mtk_jpegdec_timeout_work);
jpegdec_clk = &dev->jdec_clk;
jpegdec_clk->clk_num = devm_clk_bulk_get_all(&pdev->dev,
&jpegdec_clk->clks);
if (jpegdec_clk->clk_num < 0)
return dev_err_probe(&pdev->dev,
jpegdec_clk->clk_num,
"Failed to get jpegdec clock count.\n");
dev->reg_base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(dev->reg_base))
return PTR_ERR(dev->reg_base);
ret = mtk_jpegdec_hw_init_irq(dev);
if (ret)
return dev_err_probe(&pdev->dev, ret,
"Failed to register JPEGDEC irq handler.\n");
for (i = 0; i < MTK_JPEGDEC_HW_MAX; i++) {
if (master_dev->dec_hw_dev[i])
continue;
master_dev->dec_hw_dev[i] = dev;
master_dev->reg_decbase[i] = dev->reg_base;
dev->master_dev = master_dev;
}
platform_set_drvdata(pdev, dev);
pm_runtime_enable(&pdev->dev);
return 0;
}
static struct platform_driver mtk_jpegdec_hw_driver = {
.probe = mtk_jpegdec_hw_probe,
.driver = {
.name = "mtk-jpegdec-hw",
.of_match_table = of_match_ptr(mtk_jpegdec_hw_ids),
},
};
module_platform_driver(mtk_jpegdec_hw_driver);
MODULE_DESCRIPTION("MediaTek JPEG decode HW driver");
MODULE_LICENSE("GPL");

6
drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.h
View File

@ -11,9 +11,10 @@
#include <media/videobuf2-core.h>
#include "mtk_jpeg_core.h"
#include "mtk_jpeg_dec_reg.h"
#define MTK_JPEG_COMP_MAX 3
enum {
MTK_JPEG_DEC_RESULT_EOF_DONE = 0,
MTK_JPEG_DEC_RESULT_PAUSE = 1,
@ -70,7 +71,8 @@ int mtk_jpeg_dec_fill_param(struct mtk_jpeg_dec_param *param);
u32 mtk_jpeg_dec_get_int_status(void __iomem *dec_reg_base);
u32 mtk_jpeg_dec_enum_result(u32 irq_result);
void mtk_jpeg_dec_set_config(void __iomem *base,
struct mtk_jpeg_dec_param *config,
struct mtk_jpeg_dec_param *cfg,
u32 bitstream_size,
struct mtk_jpeg_bs *bs,
struct mtk_jpeg_fb *fb);
void mtk_jpeg_dec_reset(void __iomem *dec_reg_base);

1
drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_reg.h
View File

@ -45,5 +45,6 @@
#define JPGDEC_REG_QT_ID 0x0270
#define JPGDEC_REG_INTERRUPT_STATUS 0x0274
#define JPGDEC_REG_STATUS 0x0278
#define JPGDEC_REG_BIT_STREAM_SIZE 0x0344
#endif /* _MTK_JPEG_REG_H */

255
drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c
View File

@ -5,11 +5,27 @@
*
*/
#include <linux/clk.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pm_runtime.h>
#include <linux/slab.h>
#include <media/media-device.h>
#include <media/videobuf2-core.h>
#include <media/videobuf2-dma-contig.h>
#include <media/videobuf2-v4l2.h>
#include <media/v4l2-mem2mem.h>
#include <media/v4l2-dev.h>
#include <media/v4l2-device.h>
#include <media/v4l2-fh.h>
#include <media/v4l2-event.h>
#include "mtk_jpeg_core.h"
#include "mtk_jpeg_enc_hw.h"
static const struct mtk_jpeg_enc_qlt mtk_jpeg_enc_quality[] = {
@ -30,18 +46,30 @@ static const struct mtk_jpeg_enc_qlt mtk_jpeg_enc_quality[] = {
{.quality_param = 97, .hardware_value = JPEG_ENC_QUALITY_Q97},
};
#if defined(CONFIG_OF)
static const struct of_device_id mtk_jpegenc_drv_ids[] = {
{
.compatible = "mediatek,mt8195-jpgenc-hw",
},
{},
};
MODULE_DEVICE_TABLE(of, mtk_jpegenc_drv_ids);
#endif
void mtk_jpeg_enc_reset(void __iomem *base)
{
writel(0, base + JPEG_ENC_RSTB);
writel(JPEG_ENC_RESET_BIT, base + JPEG_ENC_RSTB);
writel(0, base + JPEG_ENC_CODEC_SEL);
}
EXPORT_SYMBOL_GPL(mtk_jpeg_enc_reset);
u32 mtk_jpeg_enc_get_file_size(void __iomem *base)
{
return readl(base + JPEG_ENC_DMA_ADDR0) -
readl(base + JPEG_ENC_DST_ADDR0);
}
EXPORT_SYMBOL_GPL(mtk_jpeg_enc_get_file_size);
void mtk_jpeg_enc_start(void __iomem *base)
{
@ -51,6 +79,7 @@ void mtk_jpeg_enc_start(void __iomem *base)
value |= JPEG_ENC_CTRL_INT_EN_BIT | JPEG_ENC_CTRL_ENABLE_BIT;
writel(value, base + JPEG_ENC_CTRL);
}
EXPORT_SYMBOL_GPL(mtk_jpeg_enc_start);
void mtk_jpeg_set_enc_src(struct mtk_jpeg_ctx *ctx, void __iomem *base,
struct vb2_buffer *src_buf)
@ -67,6 +96,7 @@ void mtk_jpeg_set_enc_src(struct mtk_jpeg_ctx *ctx, void __iomem *base,
writel(dma_addr, base + JPEG_ENC_SRC_CHROMA_ADDR);
}
}
EXPORT_SYMBOL_GPL(mtk_jpeg_set_enc_src);
void mtk_jpeg_set_enc_dst(struct mtk_jpeg_ctx *ctx, void __iomem *base,
struct vb2_buffer *dst_buf)
@ -86,6 +116,7 @@ void mtk_jpeg_set_enc_dst(struct mtk_jpeg_ctx *ctx, void __iomem *base,
writel(dma_addr & ~0xf, base + JPEG_ENC_DST_ADDR0);
writel((dma_addr + size) & ~0xf, base + JPEG_ENC_STALL_ADDR0);
}
EXPORT_SYMBOL_GPL(mtk_jpeg_set_enc_dst);
void mtk_jpeg_set_enc_params(struct mtk_jpeg_ctx *ctx, void __iomem *base)
{
@ -152,3 +183,227 @@ void mtk_jpeg_set_enc_params(struct mtk_jpeg_ctx *ctx, void __iomem *base)
writel(ctx->restart_interval, base + JPEG_ENC_RST_MCU_NUM);
}
EXPORT_SYMBOL_GPL(mtk_jpeg_set_enc_params);
static void mtk_jpegenc_put_buf(struct mtk_jpegenc_comp_dev *jpeg)
{
struct mtk_jpeg_ctx *ctx;
struct vb2_v4l2_buffer *dst_buffer;
struct list_head *temp_entry;
struct list_head *pos = NULL;
struct mtk_jpeg_src_buf *dst_done_buf, *tmp_dst_done_buf;
unsigned long flags;
ctx = jpeg->hw_param.curr_ctx;
if (!ctx) {
dev_err(jpeg->dev, "comp_jpeg ctx fail !!!\n");
return;
}
dst_buffer = jpeg->hw_param.dst_buffer;
if (!dst_buffer) {
dev_err(jpeg->dev, "comp_jpeg dst_buffer fail !!!\n");
return;
}
dst_done_buf = container_of(dst_buffer,
struct mtk_jpeg_src_buf, b);
spin_lock_irqsave(&ctx->done_queue_lock, flags);
list_add_tail(&dst_done_buf->list, &ctx->dst_done_queue);
while (!list_empty(&ctx->dst_done_queue) &&
(pos != &ctx->dst_done_queue)) {
list_for_each_prev_safe(pos, temp_entry, &ctx->dst_done_queue) {
tmp_dst_done_buf = list_entry(pos,
struct mtk_jpeg_src_buf,
list);
if (tmp_dst_done_buf->frame_num ==
ctx->last_done_frame_num) {
list_del(&tmp_dst_done_buf->list);
v4l2_m2m_buf_done(&tmp_dst_done_buf->b,
VB2_BUF_STATE_DONE);
ctx->last_done_frame_num++;
}
}
}
spin_unlock_irqrestore(&ctx->done_queue_lock, flags);
}
static void mtk_jpegenc_timeout_work(struct work_struct *work)
{
struct delayed_work *dly_work = to_delayed_work(work);
struct mtk_jpegenc_comp_dev *cjpeg =
container_of(dly_work,
struct mtk_jpegenc_comp_dev,
job_timeout_work);
struct mtk_jpeg_dev *master_jpeg = cjpeg->master_dev;
enum vb2_buffer_state buf_state = VB2_BUF_STATE_ERROR;
struct vb2_v4l2_buffer *src_buf, *dst_buf;
src_buf = cjpeg->hw_param.src_buffer;
dst_buf = cjpeg->hw_param.dst_buffer;
v4l2_m2m_buf_copy_metadata(src_buf, dst_buf, true);
mtk_jpeg_enc_reset(cjpeg->reg_base);
clk_disable_unprepare(cjpeg->venc_clk.clks->clk);
pm_runtime_put(cjpeg->dev);
cjpeg->hw_state = MTK_JPEG_HW_IDLE;
atomic_inc(&master_jpeg->enchw_rdy);
wake_up(&master_jpeg->enc_hw_wq);
v4l2_m2m_buf_done(src_buf, buf_state);
mtk_jpegenc_put_buf(cjpeg);
}
static irqreturn_t mtk_jpegenc_hw_irq_handler(int irq, void *priv)
{
struct vb2_v4l2_buffer *src_buf, *dst_buf;
enum vb2_buffer_state buf_state;
struct mtk_jpeg_ctx *ctx;
u32 result_size;
u32 irq_status;
struct mtk_jpegenc_comp_dev *jpeg = priv;
struct mtk_jpeg_dev *master_jpeg = jpeg->master_dev;
cancel_delayed_work(&jpeg->job_timeout_work);
ctx = jpeg->hw_param.curr_ctx;
src_buf = jpeg->hw_param.src_buffer;
dst_buf = jpeg->hw_param.dst_buffer;
v4l2_m2m_buf_copy_metadata(src_buf, dst_buf, true);
irq_status = readl(jpeg->reg_base + JPEG_ENC_INT_STS) &
JPEG_ENC_INT_STATUS_MASK_ALLIRQ;
if (irq_status)
writel(0, jpeg->reg_base + JPEG_ENC_INT_STS);
if (!(irq_status & JPEG_ENC_INT_STATUS_DONE))
dev_warn(jpeg->dev, "Jpg Enc occurs unknown Err.");
result_size = mtk_jpeg_enc_get_file_size(jpeg->reg_base);
vb2_set_plane_payload(&dst_buf->vb2_buf, 0, result_size);
buf_state = VB2_BUF_STATE_DONE;
v4l2_m2m_buf_done(src_buf, buf_state);
mtk_jpegenc_put_buf(jpeg);
pm_runtime_put(ctx->jpeg->dev);
clk_disable_unprepare(jpeg->venc_clk.clks->clk);
if (!list_empty(&ctx->fh.m2m_ctx->out_q_ctx.rdy_queue) ||
!list_empty(&ctx->fh.m2m_ctx->cap_q_ctx.rdy_queue)) {
queue_work(master_jpeg->workqueue, &ctx->jpeg_work);
}
jpeg->hw_state = MTK_JPEG_HW_IDLE;
wake_up(&master_jpeg->enc_hw_wq);
atomic_inc(&master_jpeg->enchw_rdy);
return IRQ_HANDLED;
}
static int mtk_jpegenc_hw_init_irq(struct mtk_jpegenc_comp_dev *dev)
{
struct platform_device *pdev = dev->plat_dev;
int ret;
dev->jpegenc_irq = platform_get_irq(pdev, 0);
if (dev->jpegenc_irq < 0)
return dev->jpegenc_irq;
ret = devm_request_irq(&pdev->dev,
dev->jpegenc_irq,
mtk_jpegenc_hw_irq_handler,
0,
pdev->name, dev);
if (ret) {
dev_err(&pdev->dev, "Failed to devm_request_irq %d (%d)",
dev->jpegenc_irq, ret);
return ret;
}
return 0;
}
static int mtk_jpegenc_hw_probe(struct platform_device *pdev)
{
struct mtk_jpegenc_clk *jpegenc_clk;
struct mtk_jpeg_dev *master_dev;
struct mtk_jpegenc_comp_dev *dev;
int ret, i;
struct device *decs = &pdev->dev;
if (!decs->parent)
return -EPROBE_DEFER;
master_dev = dev_get_drvdata(decs->parent);
if (!master_dev)
return -EPROBE_DEFER;
dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
if (!dev)
return -ENOMEM;
dev->plat_dev = pdev;
dev->dev = &pdev->dev;
if (!master_dev->is_jpgenc_multihw) {
master_dev->is_jpgenc_multihw = true;
for (i = 0; i < MTK_JPEGENC_HW_MAX; i++)
master_dev->enc_hw_dev[i] = NULL;
init_waitqueue_head(&master_dev->enc_hw_wq);
master_dev->workqueue = alloc_ordered_workqueue(MTK_JPEG_NAME,
WQ_MEM_RECLAIM
| WQ_FREEZABLE);
if (!master_dev->workqueue)
return -EINVAL;
}
atomic_set(&master_dev->enchw_rdy, MTK_JPEGENC_HW_MAX);
spin_lock_init(&dev->hw_lock);
dev->hw_state = MTK_JPEG_HW_IDLE;
INIT_DELAYED_WORK(&dev->job_timeout_work,
mtk_jpegenc_timeout_work);
jpegenc_clk = &dev->venc_clk;
jpegenc_clk->clk_num = devm_clk_bulk_get_all(&pdev->dev,
&jpegenc_clk->clks);
if (jpegenc_clk->clk_num < 0)
return dev_err_probe(&pdev->dev, jpegenc_clk->clk_num,
"Failed to get jpegenc clock count\n");
dev->reg_base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(dev->reg_base))
return PTR_ERR(dev->reg_base);
ret = mtk_jpegenc_hw_init_irq(dev);
if (ret)
return ret;
for (i = 0; i < MTK_JPEGENC_HW_MAX; i++) {
if (master_dev->enc_hw_dev[i])
continue;
master_dev->enc_hw_dev[i] = dev;
master_dev->reg_encbase[i] = dev->reg_base;
dev->master_dev = master_dev;
}
platform_set_drvdata(pdev, dev);
pm_runtime_enable(&pdev->dev);
return 0;
}
static struct platform_driver mtk_jpegenc_hw_driver = {
.probe = mtk_jpegenc_hw_probe,
.driver = {
.name = "mtk-jpegenc-hw",
.of_match_table = of_match_ptr(mtk_jpegenc_drv_ids),
},
};
module_platform_driver(mtk_jpegenc_hw_driver);
MODULE_DESCRIPTION("MediaTek JPEG encode HW driver");
MODULE_LICENSE("GPL");

4
drivers/media/platform/nxp/imx-jpeg/mxc-jpeg-hw.c
View File

@ -76,12 +76,14 @@ void print_wrapper_info(struct device *dev, void __iomem *reg)
void mxc_jpeg_enable_irq(void __iomem *reg, int slot)
{
writel(0xFFFFFFFF, reg + MXC_SLOT_OFFSET(slot, SLOT_IRQ_EN));
writel(0xFFFFFFFF, reg + MXC_SLOT_OFFSET(slot, SLOT_STATUS));
writel(0xF0C, reg + MXC_SLOT_OFFSET(slot, SLOT_IRQ_EN));
}
void mxc_jpeg_disable_irq(void __iomem *reg, int slot)
{
writel(0x0, reg + MXC_SLOT_OFFSET(slot, SLOT_IRQ_EN));
writel(0xFFFFFFFF, reg + MXC_SLOT_OFFSET(slot, SLOT_STATUS));
}
void mxc_jpeg_sw_reset(void __iomem *reg)

610
drivers/media/platform/nxp/imx-jpeg/mxc-jpeg.c
View File

File diff suppressed because it is too large Load Diff

10
drivers/media/platform/nxp/imx-jpeg/mxc-jpeg.h
View File

@ -45,11 +45,13 @@ enum mxc_jpeg_mode {
* @subsampling: subsampling of jpeg components
* @nc: number of color components
* @depth: number of bits per pixel
* @colplanes: number of color planes (1 for packed formats)
* @mem_planes: number of memory planes (1 for packed formats)
* @comp_planes:number of component planes, which includes the alpha plane (1 to 4).
* @h_align: horizontal alignment order (align to 2^h_align)
* @v_align: vertical alignment order (align to 2^v_align)
* @flags: flags describing format applicability
* @precision: jpeg sample precision
* @is_rgb: is an RGB pixel format
*/
struct mxc_jpeg_fmt {
const char *name;
@ -57,11 +59,13 @@ struct mxc_jpeg_fmt {
enum v4l2_jpeg_chroma_subsampling subsampling;
int nc;
int depth;
int colplanes;
int mem_planes;
int comp_planes;
int h_align;
int v_align;
u32 flags;
u8 precision;
u8 is_rgb;
};
struct mxc_jpeg_desc {
@ -84,6 +88,7 @@ struct mxc_jpeg_q_data {
int h;
int h_adjusted;
unsigned int sequence;
struct v4l2_rect crop;
};
struct mxc_jpeg_ctx {
@ -97,6 +102,7 @@ struct mxc_jpeg_ctx {
bool header_parsed;
struct v4l2_ctrl_handler ctrl_handler;
u8 jpeg_quality;
struct delayed_work task_timer;
};
struct mxc_jpeg_slot_data {