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EDAC, amd64_edac: Extend scrub rate support to F15hM60h

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The scrub rate control register has moved to function 2 in PCI config
space and is at a different offset on family 0x15, models 0x60 and
later. The minimum recommended scrub rate has also changed. (Refer to
D18F2x1c9_dct[1:0][DramScrub] in Fam15hM60h BKDG).

Adjust set_scrub_rate() and get_scrub_rate() functions to accommodate
this.

Tested on F15hM60h, Fam15h, models 00h-0fh and Fam10h systems.

Signed-off-by: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
Cc: linux-edac <linux-edac@vger.kernel.org>
Link: http://lkml.kernel.org/r/1443440593-2316-2-git-send-email-Aravind.Gopalakrishnan@amd.com
[ Cleanup conditionals. ]
Signed-off-by: Borislav Petkov <bp@suse.de>
This commit is contained in:
Aravind Gopalakrishnan 2015-09-28 06:43:12 -05:00 committed by Borislav Petkov
parent d0c9c93019
commit da92110dfd
2 changed files with 27 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

35
drivers/edac/amd64_edac.c
View File

@ -173,7 +173,7 @@ static inline int amd64_read_dct_pci_cfg(struct amd64_pvt *pvt, u8 dct,
* scan the scrub rate mapping table for a close or matching bandwidth value to * scan the scrub rate mapping table for a close or matching bandwidth value to
* issue. If requested is too big, then use last maximum value found. * issue. If requested is too big, then use last maximum value found.
*/ */
static int __set_scrub_rate(struct pci_dev *ctl, u32 new_bw, u32 min_rate) static int __set_scrub_rate(struct amd64_pvt *pvt, u32 new_bw, u32 min_rate)
{ {
u32 scrubval; u32 scrubval;
int i; int i;
@ -201,7 +201,14 @@ static int __set_scrub_rate(struct pci_dev *ctl, u32 new_bw, u32 min_rate)
scrubval = scrubrates[i].scrubval; scrubval = scrubrates[i].scrubval;
pci_write_bits32(ctl, SCRCTRL, scrubval, 0x001F); if (pvt->fam == 0x15 && pvt->model == 0x60) {
f15h_select_dct(pvt, 0);
pci_write_bits32(pvt->F2, F15H_M60H_SCRCTRL, scrubval, 0x001F);
f15h_select_dct(pvt, 1);
pci_write_bits32(pvt->F2, F15H_M60H_SCRCTRL, scrubval, 0x001F);
} else {
pci_write_bits32(pvt->F3, SCRCTRL, scrubval, 0x001F);
}
if (scrubval) if (scrubval)
return scrubrates[i].bandwidth; return scrubrates[i].bandwidth;
@ -217,11 +224,15 @@ static int set_scrub_rate(struct mem_ctl_info *mci, u32 bw)
if (pvt->fam == 0xf) if (pvt->fam == 0xf)
min_scrubrate = 0x0; min_scrubrate = 0x0;
/* Erratum #505 */ if (pvt->fam == 0x15) {
if (pvt->fam == 0x15 && pvt->model < 0x10) /* Erratum #505 */
f15h_select_dct(pvt, 0); if (pvt->model < 0x10)
f15h_select_dct(pvt, 0);
return __set_scrub_rate(pvt->F3, bw, min_scrubrate); if (pvt->model == 0x60)
min_scrubrate = 0x6;
}
return __set_scrub_rate(pvt, bw, min_scrubrate);
} }
static int get_scrub_rate(struct mem_ctl_info *mci) static int get_scrub_rate(struct mem_ctl_info *mci)
@ -230,11 +241,15 @@ static int get_scrub_rate(struct mem_ctl_info *mci)
u32 scrubval = 0; u32 scrubval = 0;
int i, retval = -EINVAL; int i, retval = -EINVAL;
/* Erratum #505 */ if (pvt->fam == 0x15) {
if (pvt->fam == 0x15 && pvt->model < 0x10) /* Erratum #505 */
f15h_select_dct(pvt, 0); if (pvt->model < 0x10)
f15h_select_dct(pvt, 0);
amd64_read_pci_cfg(pvt->F3, SCRCTRL, &scrubval); if (pvt->model == 0x60)
amd64_read_pci_cfg(pvt->F2, F15H_M60H_SCRCTRL, &scrubval);
} else
amd64_read_pci_cfg(pvt->F3, SCRCTRL, &scrubval);
scrubval = scrubval & 0x001F; scrubval = scrubval & 0x001F;

2
drivers/edac/amd64_edac.h
View File

@ -255,6 +255,8 @@
#define DCT_SEL_HI 0x114 #define DCT_SEL_HI 0x114
#define F15H_M60H_SCRCTRL 0x1C8
/* /*
* Function 3 - Misc Control * Function 3 - Misc Control
*/ */