mirror of
https://github.com/torvalds/linux.git
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Merge branch 'sh/dynamic-irq-cleanup' into sh-latest
Conflicts: drivers/sh/intc/dynamic.c Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Paul Mundt
commit
d978006a54
@ -44,6 +44,8 @@ config SH_7721_SOLUTION_ENGINE
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config SH_7722_SOLUTION_ENGINE
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bool "SolutionEngine7722"
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select SOLUTION_ENGINE
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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depends on CPU_SUBTYPE_SH7722
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help
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Select 7722 SolutionEngine if configuring for a Hitachi SH772
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@ -80,6 +82,8 @@ config SH_7780_SOLUTION_ENGINE
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config SH_7343_SOLUTION_ENGINE
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bool "SolutionEngine7343"
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select SOLUTION_ENGINE
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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depends on CPU_SUBTYPE_SH7343
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help
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Select 7343 SolutionEngine if configuring for a Hitachi
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@ -295,6 +299,7 @@ config SH_X3PROTO
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bool "SH-X3 Prototype board"
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depends on CPU_SUBTYPE_SHX3
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select NO_IOPORT if !PCI
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select IRQ_DOMAIN
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config SH_MAGIC_PANEL_R2
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bool "Magic Panel R2"
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@ -8,10 +8,11 @@
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* This file is part of the LinuxDC project (www.linuxdc.org)
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* Released under the terms of the GNU GPL v2.0
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*/
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <asm/irq.h>
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#include <linux/irq.h>
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#include <linux/export.h>
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#include <linux/err.h>
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#include <mach/sysasic.h>
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/*
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@ -141,26 +142,15 @@ int systemasic_irq_demux(int irq)
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void systemasic_irq_init(void)
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{
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int i, nid = cpu_to_node(boot_cpu_data);
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int irq_base, i;
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/* Assign all virtual IRQs to the System ASIC int. handler */
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for (i = HW_EVENT_IRQ_BASE; i < HW_EVENT_IRQ_MAX; i++) {
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unsigned int irq;
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irq = create_irq_nr(i, nid);
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if (unlikely(irq == 0)) {
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pr_err("%s: failed hooking irq %d for systemasic\n",
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__func__, i);
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return;
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}
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if (unlikely(irq != i)) {
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pr_err("%s: got irq %d but wanted %d, bailing.\n",
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__func__, irq, i);
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destroy_irq(irq);
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return;
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}
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irq_set_chip_and_handler(i, &systemasic_int, handle_level_irq);
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irq_base = irq_alloc_descs(HW_EVENT_IRQ_BASE, HW_EVENT_IRQ_BASE,
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HW_EVENT_IRQ_MAX - HW_EVENT_IRQ_BASE, -1);
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if (IS_ERR_VALUE(irq_base)) {
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pr_err("%s: failed hooking irqs\n", __func__);
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return;
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}
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for (i = HW_EVENT_IRQ_BASE; i < HW_EVENT_IRQ_MAX; i++)
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irq_set_chip_and_handler(i, &systemasic_int, handle_level_irq);
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}
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@ -1,54 +1,109 @@
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/*
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* linux/arch/sh/boards/se/7343/irq.c
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* Hitachi UL SolutionEngine 7343 FPGA IRQ Support.
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*
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* Copyright (C) 2008 Yoshihiro Shimoda
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* Copyright (C) 2012 Paul Mundt
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*
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* Based on linux/arch/sh/boards/se/7722/irq.c
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* Based on linux/arch/sh/boards/se/7343/irq.c
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* Copyright (C) 2007 Nobuhiro Iwamatsu
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#define DRV_NAME "SE7343-FPGA"
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#define pr_fmt(fmt) DRV_NAME ": " fmt
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#define irq_reg_readl ioread16
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#define irq_reg_writel iowrite16
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/irqdomain.h>
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#include <linux/io.h>
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#include <asm/sizes.h>
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#include <mach-se/mach/se7343.h>
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unsigned int se7343_fpga_irq[SE7343_FPGA_IRQ_NR] = { 0, };
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#define PA_CPLD_BASE_ADDR 0x11400000
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#define PA_CPLD_ST_REG 0x08 /* CPLD Interrupt status register */
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#define PA_CPLD_IMSK_REG 0x0a /* CPLD Interrupt mask register */
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static void disable_se7343_irq(struct irq_data *data)
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{
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unsigned int bit = (unsigned int)irq_data_get_irq_chip_data(data);
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__raw_writew(__raw_readw(PA_CPLD_IMSK) | 1 << bit, PA_CPLD_IMSK);
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}
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static void enable_se7343_irq(struct irq_data *data)
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{
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unsigned int bit = (unsigned int)irq_data_get_irq_chip_data(data);
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__raw_writew(__raw_readw(PA_CPLD_IMSK) & ~(1 << bit), PA_CPLD_IMSK);
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}
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static struct irq_chip se7343_irq_chip __read_mostly = {
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.name = "SE7343-FPGA",
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.irq_mask = disable_se7343_irq,
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.irq_unmask = enable_se7343_irq,
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};
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static void __iomem *se7343_irq_regs;
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struct irq_domain *se7343_irq_domain;
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static void se7343_irq_demux(unsigned int irq, struct irq_desc *desc)
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{
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unsigned short intv = __raw_readw(PA_CPLD_ST);
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unsigned int ext_irq = 0;
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struct irq_data *data = irq_get_irq_data(irq);
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struct irq_chip *chip = irq_data_get_irq_chip(data);
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unsigned long mask;
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int bit;
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intv &= (1 << SE7343_FPGA_IRQ_NR) - 1;
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chip->irq_mask_ack(data);
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for (; intv; intv >>= 1, ext_irq++) {
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if (!(intv & 1))
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continue;
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mask = ioread16(se7343_irq_regs + PA_CPLD_ST_REG);
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generic_handle_irq(se7343_fpga_irq[ext_irq]);
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for_each_set_bit(bit, &mask, SE7343_FPGA_IRQ_NR)
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generic_handle_irq(irq_linear_revmap(se7343_irq_domain, bit));
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chip->irq_unmask(data);
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}
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static void __init se7343_domain_init(void)
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{
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int i;
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se7343_irq_domain = irq_domain_add_linear(NULL, SE7343_FPGA_IRQ_NR,
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&irq_domain_simple_ops, NULL);
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if (unlikely(!se7343_irq_domain)) {
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printk("Failed to get IRQ domain\n");
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return;
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}
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for (i = 0; i < SE7343_FPGA_IRQ_NR; i++) {
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int irq = irq_create_mapping(se7343_irq_domain, i);
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if (unlikely(irq == 0)) {
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printk("Failed to allocate IRQ %d\n", i);
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return;
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}
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}
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}
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static void __init se7343_gc_init(void)
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{
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struct irq_chip_generic *gc;
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struct irq_chip_type *ct;
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unsigned int irq_base;
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irq_base = irq_linear_revmap(se7343_irq_domain, 0);
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gc = irq_alloc_generic_chip(DRV_NAME, 1, irq_base, se7343_irq_regs,
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handle_level_irq);
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if (unlikely(!gc))
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return;
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ct = gc->chip_types;
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ct->chip.irq_mask = irq_gc_mask_set_bit;
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ct->chip.irq_unmask = irq_gc_mask_clr_bit;
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ct->regs.mask = PA_CPLD_IMSK_REG;
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irq_setup_generic_chip(gc, IRQ_MSK(SE7343_FPGA_IRQ_NR),
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IRQ_GC_INIT_MASK_CACHE,
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IRQ_NOREQUEST | IRQ_NOPROBE, 0);
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irq_set_chained_handler(IRQ0_IRQ, se7343_irq_demux);
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irq_set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW);
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irq_set_chained_handler(IRQ1_IRQ, se7343_irq_demux);
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irq_set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW);
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irq_set_chained_handler(IRQ4_IRQ, se7343_irq_demux);
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irq_set_irq_type(IRQ4_IRQ, IRQ_TYPE_LEVEL_LOW);
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irq_set_chained_handler(IRQ5_IRQ, se7343_irq_demux);
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irq_set_irq_type(IRQ5_IRQ, IRQ_TYPE_LEVEL_LOW);
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}
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/*
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@ -56,31 +111,19 @@ static void se7343_irq_demux(unsigned int irq, struct irq_desc *desc)
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*/
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void __init init_7343se_IRQ(void)
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{
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int i, irq;
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__raw_writew(0, PA_CPLD_IMSK); /* disable all irqs */
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__raw_writew(0x2000, 0xb03fffec); /* mrshpc irq enable */
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for (i = 0; i < SE7343_FPGA_IRQ_NR; i++) {
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irq = create_irq();
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if (irq < 0)
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return;
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se7343_fpga_irq[i] = irq;
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irq_set_chip_and_handler_name(se7343_fpga_irq[i],
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&se7343_irq_chip,
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handle_level_irq,
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"level");
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irq_set_chip_data(se7343_fpga_irq[i], (void *)i);
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se7343_irq_regs = ioremap(PA_CPLD_BASE_ADDR, SZ_16);
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if (unlikely(!se7343_irq_regs)) {
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pr_err("Failed to remap CPLD\n");
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return;
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}
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irq_set_chained_handler(IRQ0_IRQ, se7343_irq_demux);
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irq_set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW);
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irq_set_chained_handler(IRQ1_IRQ, se7343_irq_demux);
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irq_set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW);
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irq_set_chained_handler(IRQ4_IRQ, se7343_irq_demux);
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irq_set_irq_type(IRQ4_IRQ, IRQ_TYPE_LEVEL_LOW);
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irq_set_chained_handler(IRQ5_IRQ, se7343_irq_demux);
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irq_set_irq_type(IRQ5_IRQ, IRQ_TYPE_LEVEL_LOW);
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/*
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* All FPGA IRQs disabled by default
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*/
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iowrite16(0, se7343_irq_regs + PA_CPLD_IMSK_REG);
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__raw_writew(0x2000, 0xb03fffec); /* mrshpc irq enable */
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se7343_domain_init();
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se7343_gc_init();
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}
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@ -5,6 +5,7 @@
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#include <linux/serial_reg.h>
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#include <linux/usb/isp116x.h>
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#include <linux/delay.h>
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#include <linux/irqdomain.h>
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#include <asm/machvec.h>
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#include <mach-se/mach/se7343.h>
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#include <asm/heartbeat.h>
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@ -145,11 +146,12 @@ static struct platform_device *sh7343se_platform_devices[] __initdata = {
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static int __init sh7343se_devices_setup(void)
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{
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/* Wire-up dynamic vectors */
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serial_platform_data[0].irq = se7343_fpga_irq[SE7343_FPGA_IRQ_UARTA];
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serial_platform_data[1].irq = se7343_fpga_irq[SE7343_FPGA_IRQ_UARTB];
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serial_platform_data[0].irq = irq_find_mapping(se7343_irq_domain,
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SE7343_FPGA_IRQ_UARTA);
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serial_platform_data[1].irq = irq_find_mapping(se7343_irq_domain,
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SE7343_FPGA_IRQ_UARTB);
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usb_resources[2].start = usb_resources[2].end =
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se7343_fpga_irq[SE7343_FPGA_IRQ_USB];
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irq_find_mapping(se7343_irq_domain, SE7343_FPGA_IRQ_USB);
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return platform_add_devices(sh7343se_platform_devices,
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ARRAY_SIZE(sh7343se_platform_devices));
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@ -1,79 +1,96 @@
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||||
/*
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||||
* linux/arch/sh/boards/se/7722/irq.c
|
||||
* Hitachi UL SolutionEngine 7722 FPGA IRQ Support.
|
||||
*
|
||||
* Copyright (C) 2007 Nobuhiro Iwamatsu
|
||||
*
|
||||
* Hitachi UL SolutionEngine 7722 Support.
|
||||
* Copyright (C) 2012 Paul Mundt
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
#define DRV_NAME "SE7722-FPGA"
|
||||
#define pr_fmt(fmt) DRV_NAME ": " fmt
|
||||
|
||||
#define irq_reg_readl ioread16
|
||||
#define irq_reg_writel iowrite16
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/io.h>
|
||||
#include <linux/irqdomain.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/err.h>
|
||||
#include <asm/sizes.h>
|
||||
#include <mach-se/mach/se7722.h>
|
||||
|
||||
unsigned int se7722_fpga_irq[SE7722_FPGA_IRQ_NR] = { 0, };
|
||||
#define IRQ01_BASE_ADDR 0x11800000
|
||||
#define IRQ01_MODE_REG 0
|
||||
#define IRQ01_STS_REG 4
|
||||
#define IRQ01_MASK_REG 8
|
||||
|
||||
static void disable_se7722_irq(struct irq_data *data)
|
||||
{
|
||||
unsigned int bit = (unsigned int)irq_data_get_irq_chip_data(data);
|
||||
__raw_writew(__raw_readw(IRQ01_MASK) | 1 << bit, IRQ01_MASK);
|
||||
}
|
||||
|
||||
static void enable_se7722_irq(struct irq_data *data)
|
||||
{
|
||||
unsigned int bit = (unsigned int)irq_data_get_irq_chip_data(data);
|
||||
__raw_writew(__raw_readw(IRQ01_MASK) & ~(1 << bit), IRQ01_MASK);
|
||||
}
|
||||
|
||||
static struct irq_chip se7722_irq_chip __read_mostly = {
|
||||
.name = "SE7722-FPGA",
|
||||
.irq_mask = disable_se7722_irq,
|
||||
.irq_unmask = enable_se7722_irq,
|
||||
};
|
||||
static void __iomem *se7722_irq_regs;
|
||||
struct irq_domain *se7722_irq_domain;
|
||||
|
||||
static void se7722_irq_demux(unsigned int irq, struct irq_desc *desc)
|
||||
{
|
||||
unsigned short intv = __raw_readw(IRQ01_STS);
|
||||
unsigned int ext_irq = 0;
|
||||
struct irq_data *data = irq_get_irq_data(irq);
|
||||
struct irq_chip *chip = irq_data_get_irq_chip(data);
|
||||
unsigned long mask;
|
||||
int bit;
|
||||
|
||||
intv &= (1 << SE7722_FPGA_IRQ_NR) - 1;
|
||||
chip->irq_mask_ack(data);
|
||||
|
||||
for (; intv; intv >>= 1, ext_irq++) {
|
||||
if (!(intv & 1))
|
||||
continue;
|
||||
mask = ioread16(se7722_irq_regs + IRQ01_STS_REG);
|
||||
|
||||
generic_handle_irq(se7722_fpga_irq[ext_irq]);
|
||||
for_each_set_bit(bit, &mask, SE7722_FPGA_IRQ_NR)
|
||||
generic_handle_irq(irq_linear_revmap(se7722_irq_domain, bit));
|
||||
|
||||
chip->irq_unmask(data);
|
||||
}
|
||||
|
||||
static void __init se7722_domain_init(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
se7722_irq_domain = irq_domain_add_linear(NULL, SE7722_FPGA_IRQ_NR,
|
||||
&irq_domain_simple_ops, NULL);
|
||||
if (unlikely(!se7722_irq_domain)) {
|
||||
printk("Failed to get IRQ domain\n");
|
||||
return;
|
||||
}
|
||||
|
||||
for (i = 0; i < SE7722_FPGA_IRQ_NR; i++) {
|
||||
int irq = irq_create_mapping(se7722_irq_domain, i);
|
||||
|
||||
if (unlikely(irq == 0)) {
|
||||
printk("Failed to allocate IRQ %d\n", i);
|
||||
return;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Initialize IRQ setting
|
||||
*/
|
||||
void __init init_se7722_IRQ(void)
|
||||
static void __init se7722_gc_init(void)
|
||||
{
|
||||
int i, irq;
|
||||
struct irq_chip_generic *gc;
|
||||
struct irq_chip_type *ct;
|
||||
unsigned int irq_base;
|
||||
|
||||
__raw_writew(0, IRQ01_MASK); /* disable all irqs */
|
||||
__raw_writew(0x2000, 0xb03fffec); /* mrshpc irq enable */
|
||||
irq_base = irq_linear_revmap(se7722_irq_domain, 0);
|
||||
|
||||
for (i = 0; i < SE7722_FPGA_IRQ_NR; i++) {
|
||||
irq = create_irq();
|
||||
if (irq < 0)
|
||||
return;
|
||||
se7722_fpga_irq[i] = irq;
|
||||
gc = irq_alloc_generic_chip(DRV_NAME, 1, irq_base, se7722_irq_regs,
|
||||
handle_level_irq);
|
||||
if (unlikely(!gc))
|
||||
return;
|
||||
|
||||
irq_set_chip_and_handler_name(se7722_fpga_irq[i],
|
||||
&se7722_irq_chip,
|
||||
handle_level_irq,
|
||||
"level");
|
||||
ct = gc->chip_types;
|
||||
ct->chip.irq_mask = irq_gc_mask_set_bit;
|
||||
ct->chip.irq_unmask = irq_gc_mask_clr_bit;
|
||||
|
||||
irq_set_chip_data(se7722_fpga_irq[i], (void *)i);
|
||||
}
|
||||
ct->regs.mask = IRQ01_MASK_REG;
|
||||
|
||||
irq_setup_generic_chip(gc, IRQ_MSK(SE7722_FPGA_IRQ_NR),
|
||||
IRQ_GC_INIT_MASK_CACHE,
|
||||
IRQ_NOREQUEST | IRQ_NOPROBE, 0);
|
||||
|
||||
irq_set_chained_handler(IRQ0_IRQ, se7722_irq_demux);
|
||||
irq_set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW);
|
||||
@ -81,3 +98,25 @@ void __init init_se7722_IRQ(void)
|
||||
irq_set_chained_handler(IRQ1_IRQ, se7722_irq_demux);
|
||||
irq_set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW);
|
||||
}
|
||||
|
||||
/*
|
||||
* Initialize FPGA IRQs
|
||||
*/
|
||||
void __init init_se7722_IRQ(void)
|
||||
{
|
||||
se7722_irq_regs = ioremap(IRQ01_BASE_ADDR, SZ_16);
|
||||
if (unlikely(!se7722_irq_regs)) {
|
||||
printk("Failed to remap IRQ01 regs\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/*
|
||||
* All FPGA IRQs disabled by default
|
||||
*/
|
||||
iowrite16(0, se7722_irq_regs + IRQ01_MASK_REG);
|
||||
|
||||
__raw_writew(0x2000, 0xb03fffec); /* mrshpc irq enable */
|
||||
|
||||
se7722_domain_init();
|
||||
se7722_gc_init();
|
||||
}
|
||||
|
||||
@ -2,6 +2,7 @@
|
||||
* linux/arch/sh/boards/se/7722/setup.c
|
||||
*
|
||||
* Copyright (C) 2007 Nobuhiro Iwamatsu
|
||||
* Copyright (C) 2012 Paul Mundt
|
||||
*
|
||||
* Hitachi UL SolutionEngine 7722 Support.
|
||||
*
|
||||
@ -15,6 +16,7 @@
|
||||
#include <linux/ata_platform.h>
|
||||
#include <linux/input.h>
|
||||
#include <linux/input/sh_keysc.h>
|
||||
#include <linux/irqdomain.h>
|
||||
#include <linux/smc91x.h>
|
||||
#include <linux/sh_intc.h>
|
||||
#include <mach-se/mach/se7722.h>
|
||||
@ -143,10 +145,10 @@ static int __init se7722_devices_setup(void)
|
||||
|
||||
/* Wire-up dynamic vectors */
|
||||
cf_ide_resources[2].start = cf_ide_resources[2].end =
|
||||
se7722_fpga_irq[SE7722_FPGA_IRQ_MRSHPC0];
|
||||
irq_find_mapping(se7722_irq_domain, SE7722_FPGA_IRQ_MRSHPC0);
|
||||
|
||||
smc91x_eth_resources[1].start = smc91x_eth_resources[1].end =
|
||||
se7722_fpga_irq[SE7722_FPGA_IRQ_SMC];
|
||||
irq_find_mapping(se7722_irq_domain, SE7722_FPGA_IRQ_SMC);
|
||||
|
||||
return platform_add_devices(se7722_devices, ARRAY_SIZE(se7722_devices));
|
||||
}
|
||||
|
||||
@ -17,8 +17,10 @@
|
||||
#include <linux/init.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/io.h>
|
||||
#include <linux/export.h>
|
||||
#include <linux/topology.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/err.h>
|
||||
#include <mach-se/mach/se7724.h>
|
||||
|
||||
struct fpga_irq {
|
||||
@ -111,7 +113,7 @@ static void se7724_irq_demux(unsigned int irq, struct irq_desc *desc)
|
||||
*/
|
||||
void __init init_se7724_IRQ(void)
|
||||
{
|
||||
int i, nid = cpu_to_node(boot_cpu_data);
|
||||
int irq_base, i;
|
||||
|
||||
__raw_writew(0xffff, IRQ0_MR); /* mask all */
|
||||
__raw_writew(0xffff, IRQ1_MR); /* mask all */
|
||||
@ -121,29 +123,17 @@ void __init init_se7724_IRQ(void)
|
||||
__raw_writew(0x0000, IRQ2_SR); /* clear irq */
|
||||
__raw_writew(0x002a, IRQ_MODE); /* set irq type */
|
||||
|
||||
for (i = 0; i < SE7724_FPGA_IRQ_NR; i++) {
|
||||
int irq, wanted;
|
||||
|
||||
wanted = SE7724_FPGA_IRQ_BASE + i;
|
||||
|
||||
irq = create_irq_nr(wanted, nid);
|
||||
if (unlikely(irq == 0)) {
|
||||
pr_err("%s: failed hooking irq %d for FPGA\n",
|
||||
__func__, wanted);
|
||||
return;
|
||||
}
|
||||
|
||||
if (unlikely(irq != wanted)) {
|
||||
pr_err("%s: got irq %d but wanted %d, bailing.\n",
|
||||
__func__, irq, wanted);
|
||||
destroy_irq(irq);
|
||||
return;
|
||||
}
|
||||
|
||||
irq_set_chip_and_handler_name(irq, &se7724_irq_chip,
|
||||
handle_level_irq, "level");
|
||||
irq_base = irq_alloc_descs(SE7724_FPGA_IRQ_BASE, SE7724_FPGA_IRQ_BASE,
|
||||
SE7724_FPGA_IRQ_NR, numa_node_id());
|
||||
if (IS_ERR_VALUE(irq_base)) {
|
||||
pr_err("%s: failed hooking irqs for FPGA\n", __func__);
|
||||
return;
|
||||
}
|
||||
|
||||
for (i = 0; i < SE7724_FPGA_IRQ_NR; i++)
|
||||
irq_set_chip_and_handler_name(irq_base + i, &se7724_irq_chip,
|
||||
handle_level_irq, "level");
|
||||
|
||||
irq_set_chained_handler(IRQ0_IRQ, se7724_irq_demux);
|
||||
irq_set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW);
|
||||
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* Renesas SH-X3 Prototype Baseboard GPIO Support.
|
||||
*
|
||||
* Copyright (C) 2010 Paul Mundt
|
||||
* Copyright (C) 2010 - 2012 Paul Mundt
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
@ -17,6 +17,7 @@
|
||||
#include <linux/irq.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/irqdomain.h>
|
||||
#include <linux/io.h>
|
||||
#include <mach/ilsel.h>
|
||||
#include <mach/hardware.h>
|
||||
@ -26,7 +27,7 @@
|
||||
#define KEYDETR 0xb81c0004
|
||||
|
||||
static DEFINE_SPINLOCK(x3proto_gpio_lock);
|
||||
static unsigned int x3proto_gpio_irq_map[NR_BASEBOARD_GPIOS] = { 0, };
|
||||
static struct irq_domain *x3proto_irq_domain;
|
||||
|
||||
static int x3proto_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
|
||||
{
|
||||
@ -49,7 +50,14 @@ static int x3proto_gpio_get(struct gpio_chip *chip, unsigned gpio)
|
||||
|
||||
static int x3proto_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
|
||||
{
|
||||
return x3proto_gpio_irq_map[gpio];
|
||||
int virq;
|
||||
|
||||
if (gpio < chip->ngpio)
|
||||
virq = irq_create_mapping(x3proto_irq_domain, gpio);
|
||||
else
|
||||
virq = -ENXIO;
|
||||
|
||||
return virq;
|
||||
}
|
||||
|
||||
static void x3proto_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
|
||||
@ -62,9 +70,8 @@ static void x3proto_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
|
||||
chip->irq_mask_ack(data);
|
||||
|
||||
mask = __raw_readw(KEYDETR);
|
||||
|
||||
for_each_set_bit(pin, &mask, NR_BASEBOARD_GPIOS)
|
||||
generic_handle_irq(x3proto_gpio_to_irq(NULL, pin));
|
||||
generic_handle_irq(irq_linear_revmap(x3proto_irq_domain, pin));
|
||||
|
||||
chip->irq_unmask(data);
|
||||
}
|
||||
@ -78,10 +85,23 @@ struct gpio_chip x3proto_gpio_chip = {
|
||||
.ngpio = NR_BASEBOARD_GPIOS,
|
||||
};
|
||||
|
||||
static int x3proto_gpio_irq_map(struct irq_domain *domain, unsigned int virq,
|
||||
irq_hw_number_t hwirq)
|
||||
{
|
||||
irq_set_chip_and_handler_name(virq, &dummy_irq_chip, handle_simple_irq,
|
||||
"gpio");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct irq_domain_ops x3proto_gpio_irq_ops = {
|
||||
.map = x3proto_gpio_irq_map,
|
||||
.xlate = irq_domain_xlate_twocell,
|
||||
};
|
||||
|
||||
int __init x3proto_gpio_setup(void)
|
||||
{
|
||||
int ilsel;
|
||||
int ret, i;
|
||||
int ilsel, ret;
|
||||
|
||||
ilsel = ilsel_enable(ILSEL_KEY);
|
||||
if (unlikely(ilsel < 0))
|
||||
@ -91,21 +111,10 @@ int __init x3proto_gpio_setup(void)
|
||||
if (unlikely(ret))
|
||||
goto err_gpio;
|
||||
|
||||
for (i = 0; i < NR_BASEBOARD_GPIOS; i++) {
|
||||
unsigned long flags;
|
||||
int irq = create_irq();
|
||||
|
||||
if (unlikely(irq < 0)) {
|
||||
ret = -EINVAL;
|
||||
goto err_irq;
|
||||
}
|
||||
|
||||
spin_lock_irqsave(&x3proto_gpio_lock, flags);
|
||||
x3proto_gpio_irq_map[i] = irq;
|
||||
irq_set_chip_and_handler_name(irq, &dummy_irq_chip,
|
||||
handle_simple_irq, "gpio");
|
||||
spin_unlock_irqrestore(&x3proto_gpio_lock, flags);
|
||||
}
|
||||
x3proto_irq_domain = irq_domain_add_linear(NULL, NR_BASEBOARD_GPIOS,
|
||||
&x3proto_gpio_irq_ops, NULL);
|
||||
if (unlikely(!x3proto_irq_domain))
|
||||
goto err_irq;
|
||||
|
||||
pr_info("registering '%s' support, handling GPIOs %u -> %u, "
|
||||
"bound to IRQ %u\n",
|
||||
@ -119,10 +128,6 @@ int __init x3proto_gpio_setup(void)
|
||||
return 0;
|
||||
|
||||
err_irq:
|
||||
for (; i >= 0; --i)
|
||||
if (x3proto_gpio_irq_map[i])
|
||||
destroy_irq(x3proto_gpio_irq_map[i]);
|
||||
|
||||
ret = gpiochip_remove(&x3proto_gpio_chip);
|
||||
if (unlikely(ret))
|
||||
pr_err("Failed deregistering GPIO\n");
|
||||
|
||||
@ -73,10 +73,7 @@ static void hd64461_irq_demux(unsigned int irq, struct irq_desc *desc)
|
||||
|
||||
int __init setup_hd64461(void)
|
||||
{
|
||||
int i, nid = cpu_to_node(boot_cpu_data);
|
||||
|
||||
if (!MACH_HD64461)
|
||||
return 0;
|
||||
int irq_base, i;
|
||||
|
||||
printk(KERN_INFO
|
||||
"HD64461 configured at 0x%x on irq %d(mapped into %d to %d)\n",
|
||||
@ -89,28 +86,16 @@ int __init setup_hd64461(void)
|
||||
#endif
|
||||
__raw_writew(0xffff, HD64461_NIMR);
|
||||
|
||||
/* IRQ 80 -> 95 belongs to HD64461 */
|
||||
for (i = HD64461_IRQBASE; i < HD64461_IRQBASE + 16; i++) {
|
||||
unsigned int irq;
|
||||
|
||||
irq = create_irq_nr(i, nid);
|
||||
if (unlikely(irq == 0)) {
|
||||
pr_err("%s: failed hooking irq %d for HD64461\n",
|
||||
__func__, i);
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
if (unlikely(irq != i)) {
|
||||
pr_err("%s: got irq %d but wanted %d, bailing.\n",
|
||||
__func__, irq, i);
|
||||
destroy_irq(irq);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
irq_set_chip_and_handler(i, &hd64461_irq_chip,
|
||||
handle_level_irq);
|
||||
irq_base = irq_alloc_descs(HD64461_IRQBASE, HD64461_IRQBASE, 16, -1);
|
||||
if (IS_ERR_VALUE(irq_base)) {
|
||||
pr_err("%s: failed hooking irqs for HD64461\n", __func__);
|
||||
return irq_base;
|
||||
}
|
||||
|
||||
for (i = 0; i < 16; i++)
|
||||
irq_set_chip_and_handler(irq_base + i, &hd64461_irq_chip,
|
||||
handle_level_irq);
|
||||
|
||||
irq_set_chained_handler(CONFIG_HD64461_IRQ, hd64461_irq_demux);
|
||||
irq_set_irq_type(CONFIG_HD64461_IRQ, IRQ_TYPE_LEVEL_LOW);
|
||||
|
||||
|
||||
@ -50,9 +50,6 @@
|
||||
#define PA_LED 0xb0C00000 /* LED */
|
||||
#define LED_SHIFT 0
|
||||
#define PA_DIPSW 0xb0900000 /* Dip switch 31 */
|
||||
#define PA_CPLD_MODESET 0xb1400004 /* CPLD Mode set register */
|
||||
#define PA_CPLD_ST 0xb1400008 /* CPLD Interrupt status register */
|
||||
#define PA_CPLD_IMSK 0xb140000a /* CPLD Interrupt mask register */
|
||||
/* Area 5 */
|
||||
#define PA_EXT5 0x14000000
|
||||
#define PA_EXT5_SIZE 0x04000000
|
||||
@ -135,8 +132,10 @@
|
||||
|
||||
#define SE7343_FPGA_IRQ_NR 12
|
||||
|
||||
struct irq_domain;
|
||||
|
||||
/* arch/sh/boards/se/7343/irq.c */
|
||||
extern unsigned int se7343_fpga_irq[];
|
||||
extern struct irq_domain *se7343_irq_domain;
|
||||
|
||||
void init_7343se_IRQ(void);
|
||||
|
||||
|
||||
@ -81,12 +81,6 @@
|
||||
#define IRQ0_IRQ evt2irq(0x600)
|
||||
#define IRQ1_IRQ evt2irq(0x620)
|
||||
|
||||
#define IRQ01_MODE 0xb1800000
|
||||
#define IRQ01_STS 0xb1800004
|
||||
#define IRQ01_MASK 0xb1800008
|
||||
|
||||
/* Bits in IRQ01_* registers */
|
||||
|
||||
#define SE7722_FPGA_IRQ_USB 0 /* IRQ0 */
|
||||
#define SE7722_FPGA_IRQ_SMC 1 /* IRQ0 */
|
||||
#define SE7722_FPGA_IRQ_MRSHPC0 2 /* IRQ1 */
|
||||
@ -95,8 +89,10 @@
|
||||
#define SE7722_FPGA_IRQ_MRSHPC3 5 /* IRQ1 */
|
||||
#define SE7722_FPGA_IRQ_NR 6
|
||||
|
||||
struct irq_domain;
|
||||
|
||||
/* arch/sh/boards/se/7722/irq.c */
|
||||
extern unsigned int se7722_fpga_irq[];
|
||||
extern struct irq_domain *se7722_irq_domain;
|
||||
|
||||
void init_se7722_IRQ(void);
|
||||
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
obj-y := access.o chip.o core.o dynamic.o handle.o virq.o
|
||||
obj-y := access.o chip.o core.o handle.o virq.o
|
||||
|
||||
obj-$(CONFIG_INTC_BALANCING) += balancing.o
|
||||
obj-$(CONFIG_INTC_USERIMASK) += userimask.o
|
||||
|
||||
@ -1,57 +0,0 @@
|
||||
/*
|
||||
* Dynamic IRQ management
|
||||
*
|
||||
* Copyright (C) 2010 Paul Mundt
|
||||
*
|
||||
* Modelled after arch/x86/kernel/apic/io_apic.c
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
#define pr_fmt(fmt) "intc: " fmt
|
||||
|
||||
#include <linux/irq.h>
|
||||
#include <linux/bitmap.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/module.h>
|
||||
#include "internals.h" /* only for activate_irq() damage.. */
|
||||
|
||||
/*
|
||||
* The IRQ bitmap provides a global map of bound IRQ vectors for a
|
||||
* given platform. Allocation of IRQs are either static through the CPU
|
||||
* vector map, or dynamic in the case of board mux vectors or MSI.
|
||||
*
|
||||
* As this is a central point for all IRQ controllers on the system,
|
||||
* each of the available sources are mapped out here. This combined with
|
||||
* sparseirq makes it quite trivial to keep the vector map tightly packed
|
||||
* when dynamically creating IRQs, as well as tying in to otherwise
|
||||
* unused irq_desc positions in the sparse array.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Dynamic IRQ allocation and deallocation
|
||||
*/
|
||||
unsigned int create_irq_nr(unsigned int irq_want, int node)
|
||||
{
|
||||
int irq = irq_alloc_desc_at(irq_want, node);
|
||||
if (irq < 0)
|
||||
return 0;
|
||||
|
||||
activate_irq(irq);
|
||||
return irq;
|
||||
}
|
||||
|
||||
int create_irq(void)
|
||||
{
|
||||
int irq = irq_alloc_desc(numa_node_id());
|
||||
if (irq >= 0)
|
||||
activate_irq(irq);
|
||||
|
||||
return irq;
|
||||
}
|
||||
|
||||
void destroy_irq(unsigned int irq)
|
||||
{
|
||||
irq_free_desc(irq);
|
||||
}
|
||||
@ -219,12 +219,14 @@ restart:
|
||||
if (radix_tree_deref_retry(entry))
|
||||
goto restart;
|
||||
|
||||
irq = create_irq();
|
||||
irq = irq_alloc_desc(numa_node_id());
|
||||
if (unlikely(irq < 0)) {
|
||||
pr_err("no more free IRQs, bailing..\n");
|
||||
break;
|
||||
}
|
||||
|
||||
activate_irq(irq);
|
||||
|
||||
pr_info("Setting up a chained VIRQ from %d -> %d\n",
|
||||
irq, entry->pirq);
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user