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cpufreq: pxa: convert to clock API
As the clock settings have been introduced into the clock pxa drivers, which are now available to change the CPU clock by themselves, remove the clock handling from this driver, and rely on pxa clock drivers. Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
This commit is contained in:
Robert Jarzmik
Rafael J. Wysocki
parent
9bc70e6919
commit
d927807738
@ -58,56 +58,40 @@ module_param(pxa27x_maxfreq, uint, 0);
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MODULE_PARM_DESC(pxa27x_maxfreq, "Set the pxa27x maxfreq in MHz"
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"(typically 624=>pxa270, 416=>pxa271, 520=>pxa272)");
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struct pxa_cpufreq_data {
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struct clk *clk_core;
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};
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static struct pxa_cpufreq_data pxa_cpufreq_data;
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struct pxa_freqs {
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unsigned int khz;
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unsigned int membus;
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unsigned int cccr;
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unsigned int div2;
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unsigned int cclkcfg;
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int vmin;
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int vmax;
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};
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/* Define the refresh period in mSec for the SDRAM and the number of rows */
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#define SDRAM_TREF 64 /* standard 64ms SDRAM */
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static unsigned int sdram_rows;
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#define CCLKCFG_TURBO 0x1
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#define CCLKCFG_FCS 0x2
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#define CCLKCFG_HALFTURBO 0x4
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#define CCLKCFG_FASTBUS 0x8
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#define MDREFR_DB2_MASK (MDREFR_K2DB2 | MDREFR_K1DB2)
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#define MDREFR_DRI_MASK 0xFFF
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#define MDCNFG_DRAC2(mdcnfg) (((mdcnfg) >> 21) & 0x3)
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#define MDCNFG_DRAC0(mdcnfg) (((mdcnfg) >> 5) & 0x3)
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/*
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* PXA255 definitions
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*/
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/* Use the run mode frequencies for the CPUFREQ_POLICY_PERFORMANCE policy */
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#define CCLKCFG CCLKCFG_TURBO | CCLKCFG_FCS
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static const struct pxa_freqs pxa255_run_freqs[] =
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{
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/* CPU MEMBUS CCCR DIV2 CCLKCFG run turbo PXbus SDRAM */
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{ 99500, 99500, 0x121, 1, CCLKCFG, -1, -1}, /* 99, 99, 50, 50 */
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{132700, 132700, 0x123, 1, CCLKCFG, -1, -1}, /* 133, 133, 66, 66 */
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{199100, 99500, 0x141, 0, CCLKCFG, -1, -1}, /* 199, 199, 99, 99 */
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{265400, 132700, 0x143, 1, CCLKCFG, -1, -1}, /* 265, 265, 133, 66 */
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{331800, 165900, 0x145, 1, CCLKCFG, -1, -1}, /* 331, 331, 166, 83 */
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{398100, 99500, 0x161, 0, CCLKCFG, -1, -1}, /* 398, 398, 196, 99 */
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/* CPU MEMBUS run turbo PXbus SDRAM */
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{ 99500, -1, -1}, /* 99, 99, 50, 50 */
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{132700, -1, -1}, /* 133, 133, 66, 66 */
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{199100, -1, -1}, /* 199, 199, 99, 99 */
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{265400, -1, -1}, /* 265, 265, 133, 66 */
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{331800, -1, -1}, /* 331, 331, 166, 83 */
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{398100, -1, -1}, /* 398, 398, 196, 99 */
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};
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/* Use the turbo mode frequencies for the CPUFREQ_POLICY_POWERSAVE policy */
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static const struct pxa_freqs pxa255_turbo_freqs[] =
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{
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/* CPU MEMBUS CCCR DIV2 CCLKCFG run turbo PXbus SDRAM */
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{ 99500, 99500, 0x121, 1, CCLKCFG, -1, -1}, /* 99, 99, 50, 50 */
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{199100, 99500, 0x221, 0, CCLKCFG, -1, -1}, /* 99, 199, 50, 99 */
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{298500, 99500, 0x321, 0, CCLKCFG, -1, -1}, /* 99, 287, 50, 99 */
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{298600, 99500, 0x1c1, 0, CCLKCFG, -1, -1}, /* 199, 287, 99, 99 */
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{398100, 99500, 0x241, 0, CCLKCFG, -1, -1}, /* 199, 398, 99, 99 */
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/* CPU run turbo PXbus SDRAM */
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{ 99500, -1, -1}, /* 99, 99, 50, 50 */
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{199100, -1, -1}, /* 99, 199, 50, 99 */
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{298500, -1, -1}, /* 99, 287, 50, 99 */
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{298600, -1, -1}, /* 199, 287, 99, 99 */
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{398100, -1, -1}, /* 199, 398, 99, 99 */
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};
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#define NUM_PXA25x_RUN_FREQS ARRAY_SIZE(pxa255_run_freqs)
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@ -122,47 +106,14 @@ static unsigned int pxa255_turbo_table;
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module_param(pxa255_turbo_table, uint, 0);
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MODULE_PARM_DESC(pxa255_turbo_table, "Selects the frequency table (0 = run table, !0 = turbo table)");
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/*
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* PXA270 definitions
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*
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* For the PXA27x:
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* Control variables are A, L, 2N for CCCR; B, HT, T for CLKCFG.
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*
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* A = 0 => memory controller clock from table 3-7,
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* A = 1 => memory controller clock = system bus clock
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* Run mode frequency = 13 MHz * L
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* Turbo mode frequency = 13 MHz * L * N
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* System bus frequency = 13 MHz * L / (B + 1)
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*
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* In CCCR:
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* A = 1
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* L = 16 oscillator to run mode ratio
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* 2N = 6 2 * (turbo mode to run mode ratio)
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*
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* In CCLKCFG:
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* B = 1 Fast bus mode
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* HT = 0 Half-Turbo mode
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* T = 1 Turbo mode
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*
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* For now, just support some of the combinations in table 3-7 of
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* PXA27x Processor Family Developer's Manual to simplify frequency
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* change sequences.
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*/
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#define PXA27x_CCCR(A, L, N2) (A << 25 | N2 << 7 | L)
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#define CCLKCFG2(B, HT, T) \
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(CCLKCFG_FCS | \
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((B) ? CCLKCFG_FASTBUS : 0) | \
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((HT) ? CCLKCFG_HALFTURBO : 0) | \
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((T) ? CCLKCFG_TURBO : 0))
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static struct pxa_freqs pxa27x_freqs[] = {
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{104000, 104000, PXA27x_CCCR(1, 8, 2), 0, CCLKCFG2(1, 0, 1), 900000, 1705000 },
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{156000, 104000, PXA27x_CCCR(1, 8, 3), 0, CCLKCFG2(1, 0, 1), 1000000, 1705000 },
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{208000, 208000, PXA27x_CCCR(0, 16, 2), 1, CCLKCFG2(0, 0, 1), 1180000, 1705000 },
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{312000, 208000, PXA27x_CCCR(1, 16, 3), 1, CCLKCFG2(1, 0, 1), 1250000, 1705000 },
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{416000, 208000, PXA27x_CCCR(1, 16, 4), 1, CCLKCFG2(1, 0, 1), 1350000, 1705000 },
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{520000, 208000, PXA27x_CCCR(1, 16, 5), 1, CCLKCFG2(1, 0, 1), 1450000, 1705000 },
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{624000, 208000, PXA27x_CCCR(1, 16, 6), 1, CCLKCFG2(1, 0, 1), 1550000, 1705000 }
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{104000, 900000, 1705000 },
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{156000, 1000000, 1705000 },
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{208000, 1180000, 1705000 },
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{312000, 1250000, 1705000 },
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{416000, 1350000, 1705000 },
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{520000, 1450000, 1705000 },
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{624000, 1550000, 1705000 }
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};
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#define NUM_PXA27x_FREQS ARRAY_SIZE(pxa27x_freqs)
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@ -241,51 +192,29 @@ static void pxa27x_guess_max_freq(void)
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}
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}
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static void init_sdram_rows(void)
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{
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uint32_t mdcnfg = __raw_readl(MDCNFG);
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unsigned int drac2 = 0, drac0 = 0;
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if (mdcnfg & (MDCNFG_DE2 | MDCNFG_DE3))
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drac2 = MDCNFG_DRAC2(mdcnfg);
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if (mdcnfg & (MDCNFG_DE0 | MDCNFG_DE1))
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drac0 = MDCNFG_DRAC0(mdcnfg);
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sdram_rows = 1 << (11 + max(drac0, drac2));
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}
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static u32 mdrefr_dri(unsigned int freq)
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{
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u32 interval = freq * SDRAM_TREF / sdram_rows;
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return (interval - (cpu_is_pxa27x() ? 31 : 0)) / 32;
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}
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static unsigned int pxa_cpufreq_get(unsigned int cpu)
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{
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return get_clk_frequency_khz(0);
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struct pxa_cpufreq_data *data = cpufreq_get_driver_data();
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return (unsigned int) clk_get_rate(data->clk_core) / 1000;
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}
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static int pxa_set_target(struct cpufreq_policy *policy, unsigned int idx)
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{
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struct cpufreq_frequency_table *pxa_freqs_table;
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const struct pxa_freqs *pxa_freq_settings;
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unsigned long flags;
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unsigned int new_freq_cpu, new_freq_mem;
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unsigned int unused, preset_mdrefr, postset_mdrefr, cclkcfg;
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struct pxa_cpufreq_data *data = cpufreq_get_driver_data();
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unsigned int new_freq_cpu;
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int ret = 0;
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/* Get the current policy */
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find_freq_tables(&pxa_freqs_table, &pxa_freq_settings);
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new_freq_cpu = pxa_freq_settings[idx].khz;
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new_freq_mem = pxa_freq_settings[idx].membus;
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if (freq_debug)
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pr_debug("Changing CPU frequency to %d Mhz, (SDRAM %d Mhz)\n",
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new_freq_cpu / 1000, (pxa_freq_settings[idx].div2) ?
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(new_freq_mem / 2000) : (new_freq_mem / 1000));
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pr_debug("Changing CPU frequency from %d Mhz to %d Mhz\n",
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policy->cur / 1000, new_freq_cpu / 1000);
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if (vcc_core && new_freq_cpu > policy->cur) {
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ret = pxa_cpufreq_change_voltage(&pxa_freq_settings[idx]);
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@ -293,53 +222,7 @@ static int pxa_set_target(struct cpufreq_policy *policy, unsigned int idx)
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return ret;
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}
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/* Calculate the next MDREFR. If we're slowing down the SDRAM clock
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* we need to preset the smaller DRI before the change. If we're
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* speeding up we need to set the larger DRI value after the change.
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*/
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preset_mdrefr = postset_mdrefr = __raw_readl(MDREFR);
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if ((preset_mdrefr & MDREFR_DRI_MASK) > mdrefr_dri(new_freq_mem)) {
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preset_mdrefr = (preset_mdrefr & ~MDREFR_DRI_MASK);
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preset_mdrefr |= mdrefr_dri(new_freq_mem);
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}
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postset_mdrefr =
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(postset_mdrefr & ~MDREFR_DRI_MASK) | mdrefr_dri(new_freq_mem);
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/* If we're dividing the memory clock by two for the SDRAM clock, this
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* must be set prior to the change. Clearing the divide must be done
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* after the change.
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*/
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if (pxa_freq_settings[idx].div2) {
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preset_mdrefr |= MDREFR_DB2_MASK;
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postset_mdrefr |= MDREFR_DB2_MASK;
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} else {
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postset_mdrefr &= ~MDREFR_DB2_MASK;
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}
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local_irq_save(flags);
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/* Set new the CCCR and prepare CCLKCFG */
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writel(pxa_freq_settings[idx].cccr, CCCR);
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cclkcfg = pxa_freq_settings[idx].cclkcfg;
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asm volatile(" \n\
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ldr r4, [%1] /* load MDREFR */ \n\
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b 2f \n\
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.align 5 \n\
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1: \n\
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str %3, [%1] /* preset the MDREFR */ \n\
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mcr p14, 0, %2, c6, c0, 0 /* set CCLKCFG[FCS] */ \n\
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str %4, [%1] /* postset the MDREFR */ \n\
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\n\
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b 3f \n\
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2: b 1b \n\
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3: nop \n\
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"
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: "=&r" (unused)
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: "r" (MDREFR), "r" (cclkcfg),
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"r" (preset_mdrefr), "r" (postset_mdrefr)
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: "r4", "r5");
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local_irq_restore(flags);
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clk_set_rate(data->clk_core, new_freq_cpu * 1000);
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/*
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* Even if voltage setting fails, we don't report it, as the frequency
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@ -369,8 +252,6 @@ static int pxa_cpufreq_init(struct cpufreq_policy *policy)
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pxa_cpufreq_init_voltages();
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init_sdram_rows();
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/* set default policy and cpuinfo */
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policy->cpuinfo.transition_latency = 1000; /* FIXME: 1 ms, assumed */
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@ -429,11 +310,17 @@ static struct cpufreq_driver pxa_cpufreq_driver = {
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.init = pxa_cpufreq_init,
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.get = pxa_cpufreq_get,
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.name = "PXA2xx",
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.driver_data = &pxa_cpufreq_data,
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};
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static int __init pxa_cpu_init(void)
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{
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int ret = -ENODEV;
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pxa_cpufreq_data.clk_core = clk_get_sys(NULL, "core");
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if (IS_ERR(pxa_cpufreq_data.clk_core))
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return PTR_ERR(pxa_cpufreq_data.clk_core);
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if (cpu_is_pxa25x() || cpu_is_pxa27x())
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ret = cpufreq_register_driver(&pxa_cpufreq_driver);
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return ret;
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