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brcm80211: fmac: abstract chip iscoreup function
Prepare for adding backplane interconnect type support Reviewed-by: Arend van Spriel <arend@broadcom.com> Signed-off-by: Franky Lin <frankyl@broadcom.com> Signed-off-by: Arend van Spriel <arend@broadcom.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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@ -3138,7 +3138,6 @@ brcmf_sdbrcm_chip_resetcore(struct brcmf_sdio_dev *sdiodev, u32 corebase)
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static int brcmf_sdbrcm_download_state(struct brcmf_bus *bus, bool enter)
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{
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uint retries;
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u32 regdata;
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int bcmerror = 0;
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/* To enter download state, disable ARM and reset SOCRAM.
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@ -3159,11 +3158,8 @@ static int brcmf_sdbrcm_download_state(struct brcmf_bus *bus, bool enter)
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(u8 *)&zeros, 4);
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}
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} else {
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regdata = brcmf_sdcard_reg_read(bus->sdiodev,
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CORE_SB(bus->ci->ramcorebase, sbtmstatelow), 4);
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regdata &= (SBTML_RESET | SBTML_REJ_MASK |
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(SICF_CLOCK_EN << SBTML_SICF_SHIFT));
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if ((SICF_CLOCK_EN << SBTML_SICF_SHIFT) != regdata) {
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if (!brcmf_sdio_chip_iscoreup(bus->sdiodev,
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bus->ci->ramcorebase)) {
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brcmf_dbg(ERROR, "SOCRAM core is down after reset?\n");
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bcmerror = -EBADE;
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goto fail;
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@ -52,6 +52,19 @@
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#define SBIDH_VC_MASK 0xffff0000 /* vendor code */
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#define SBIDH_VC_SHIFT 16
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bool
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brcmf_sdio_chip_iscoreup(struct brcmf_sdio_dev *sdiodev,
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u32 corebase)
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{
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u32 regdata;
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regdata = brcmf_sdcard_reg_read(sdiodev,
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CORE_SB(corebase, sbtmstatelow), 4);
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regdata &= (SBTML_RESET | SBTML_REJ_MASK |
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(SICF_CLOCK_EN << SBTML_SICF_SHIFT));
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return ((SICF_CLOCK_EN << SBTML_SICF_SHIFT) == regdata);
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}
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void
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brcmf_sdio_chip_coredisable(struct brcmf_sdio_dev *sdiodev, u32 corebase)
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{
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@ -133,7 +133,8 @@ struct sbconfig {
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u32 sbidhigh; /* identification */
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};
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extern bool brcmf_sdio_chip_iscoreup(struct brcmf_sdio_dev *sdiodev,
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u32 corebase);
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extern void brcmf_sdio_chip_coredisable(struct brcmf_sdio_dev *sdiodev,
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u32 corebase);
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extern int brcmf_sdio_chip_attach(struct brcmf_sdio_dev *sdiodev,
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