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[PATCH] forcedeth: Jumbo Frame Support
This is a multi-part message in MIME format. Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
This commit is contained in:
Manfred Spraul
Jeff Garzik
parent
0e920bfb03
commit
d81c0983de
@ -85,6 +85,7 @@
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* 0.33: 16 May 2005: Support for MCP51 added.
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* 0.34: 18 Jun 2005: Add DEV_NEED_LINKTIMER to all nForce nics.
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* 0.35: 26 Jun 2005: Support for MCP55 added.
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* 0.36: 28 Jul 2005: Add jumbo frame support.
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*
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* Known bugs:
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* We suspect that on some hardware no TX done interrupts are generated.
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@ -96,7 +97,7 @@
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* DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
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* superfluous timer interrupts from the nic.
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*/
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#define FORCEDETH_VERSION "0.35"
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#define FORCEDETH_VERSION "0.36"
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#define DRV_NAME "forcedeth"
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#include <linux/module.h>
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@ -379,9 +380,13 @@ struct ring_desc {
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#define TX_LIMIT_START 62
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/* rx/tx mac addr + type + vlan + align + slack*/
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#define RX_NIC_BUFSIZE (ETH_DATA_LEN + 64)
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/* even more slack */
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#define RX_ALLOC_BUFSIZE (ETH_DATA_LEN + 128)
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#define NV_RX_HEADERS (64)
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/* even more slack. */
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#define NV_RX_ALLOC_PAD (64)
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/* maximum mtu size */
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#define NV_PKTLIMIT_1 ETH_DATA_LEN /* hard limit not known */
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#define NV_PKTLIMIT_2 9100 /* Actual limit according to NVidia: 9202 */
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#define OOM_REFILL (1+HZ/20)
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#define POLL_WAIT (1+HZ/100)
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@ -473,6 +478,7 @@ struct fe_priv {
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struct sk_buff *rx_skbuff[RX_RING];
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dma_addr_t rx_dma[RX_RING];
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unsigned int rx_buf_sz;
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unsigned int pkt_limit;
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struct timer_list oom_kick;
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struct timer_list nic_poll;
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@ -792,7 +798,7 @@ static int nv_alloc_rx(struct net_device *dev)
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nr = refill_rx % RX_RING;
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if (np->rx_skbuff[nr] == NULL) {
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skb = dev_alloc_skb(RX_ALLOC_BUFSIZE);
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skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
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if (!skb)
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break;
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@ -805,7 +811,7 @@ static int nv_alloc_rx(struct net_device *dev)
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PCI_DMA_FROMDEVICE);
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np->rx_ring[nr].PacketBuffer = cpu_to_le32(np->rx_dma[nr]);
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wmb();
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np->rx_ring[nr].FlagLen = cpu_to_le32(RX_NIC_BUFSIZE | NV_RX_AVAIL);
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np->rx_ring[nr].FlagLen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
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dprintk(KERN_DEBUG "%s: nv_alloc_rx: Packet %d marked as Available\n",
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dev->name, refill_rx);
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refill_rx++;
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@ -831,7 +837,18 @@ static void nv_do_rx_refill(unsigned long data)
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enable_irq(dev->irq);
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}
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static int nv_init_ring(struct net_device *dev)
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static void nv_init_rx(struct net_device *dev)
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{
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struct fe_priv *np = get_nvpriv(dev);
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int i;
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np->cur_rx = RX_RING;
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np->refill_rx = 0;
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for (i = 0; i < RX_RING; i++)
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np->rx_ring[i].FlagLen = 0;
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}
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static void nv_init_tx(struct net_device *dev)
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{
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struct fe_priv *np = get_nvpriv(dev);
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int i;
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@ -839,11 +856,12 @@ static int nv_init_ring(struct net_device *dev)
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np->next_tx = np->nic_tx = 0;
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for (i = 0; i < TX_RING; i++)
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np->tx_ring[i].FlagLen = 0;
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}
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np->cur_rx = RX_RING;
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np->refill_rx = 0;
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for (i = 0; i < RX_RING; i++)
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np->rx_ring[i].FlagLen = 0;
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static int nv_init_ring(struct net_device *dev)
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{
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nv_init_tx(dev);
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nv_init_rx(dev);
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return nv_alloc_rx(dev);
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}
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@ -1207,15 +1225,82 @@ next_pkt:
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}
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}
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static void set_bufsize(struct net_device *dev)
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{
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struct fe_priv *np = netdev_priv(dev);
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if (dev->mtu <= ETH_DATA_LEN)
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np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
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else
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np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
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}
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/*
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* nv_change_mtu: dev->change_mtu function
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* Called with dev_base_lock held for read.
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*/
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static int nv_change_mtu(struct net_device *dev, int new_mtu)
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{
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if (new_mtu > ETH_DATA_LEN)
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struct fe_priv *np = get_nvpriv(dev);
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int old_mtu;
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if (new_mtu < 64 || new_mtu > np->pkt_limit)
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return -EINVAL;
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old_mtu = dev->mtu;
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dev->mtu = new_mtu;
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/* return early if the buffer sizes will not change */
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if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
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return 0;
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if (old_mtu == new_mtu)
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return 0;
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/* synchronized against open : rtnl_lock() held by caller */
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if (netif_running(dev)) {
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u8 *base = get_hwbase(dev);
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/*
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* It seems that the nic preloads valid ring entries into an
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* internal buffer. The procedure for flushing everything is
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* guessed, there is probably a simpler approach.
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* Changing the MTU is a rare event, it shouldn't matter.
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*/
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disable_irq(dev->irq);
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spin_lock_bh(&dev->xmit_lock);
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spin_lock(&np->lock);
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/* stop engines */
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nv_stop_rx(dev);
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nv_stop_tx(dev);
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nv_txrx_reset(dev);
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/* drain rx queue */
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nv_drain_rx(dev);
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nv_drain_tx(dev);
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/* reinit driver view of the rx queue */
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nv_init_rx(dev);
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nv_init_tx(dev);
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/* alloc new rx buffers */
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set_bufsize(dev);
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if (nv_alloc_rx(dev)) {
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if (!np->in_shutdown)
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mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
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}
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/* reinit nic view of the rx queue */
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writel(np->rx_buf_sz, base + NvRegOffloadConfig);
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writel((u32) np->ring_addr, base + NvRegRxRingPhysAddr);
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writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
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writel( ((RX_RING-1) << NVREG_RINGSZ_RXSHIFT) + ((TX_RING-1) << NVREG_RINGSZ_TXSHIFT),
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base + NvRegRingSizes);
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pci_push(base);
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writel(NVREG_TXRXCTL_KICK|np->desc_ver, get_hwbase(dev) + NvRegTxRxControl);
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pci_push(base);
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/* restart rx engine */
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nv_start_rx(dev);
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nv_start_tx(dev);
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spin_unlock(&np->lock);
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spin_unlock_bh(&dev->xmit_lock);
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enable_irq(dev->irq);
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}
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return 0;
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}
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@ -1792,6 +1877,7 @@ static int nv_open(struct net_device *dev)
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writel(0, base + NvRegAdapterControl);
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/* 2) initialize descriptor rings */
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set_bufsize(dev);
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oom = nv_init_ring(dev);
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writel(0, base + NvRegLinkSpeed);
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@ -1837,7 +1923,7 @@ static int nv_open(struct net_device *dev)
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writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
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writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
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writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
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writel(NVREG_OFFLOAD_NORMAL, base + NvRegOffloadConfig);
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writel(np->rx_buf_sz, base + NvRegOffloadConfig);
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writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
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get_random_bytes(&i, sizeof(i));
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@ -2007,13 +2093,16 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i
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/* handle different descriptor versions */
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if (pci_dev->device == PCI_DEVICE_ID_NVIDIA_NVENET_1 ||
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pci_dev->device == PCI_DEVICE_ID_NVIDIA_NVENET_2 ||
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pci_dev->device == PCI_DEVICE_ID_NVIDIA_NVENET_3 ||
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pci_dev->device == PCI_DEVICE_ID_NVIDIA_NVENET_12 ||
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pci_dev->device == PCI_DEVICE_ID_NVIDIA_NVENET_13)
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pci_dev->device == PCI_DEVICE_ID_NVIDIA_NVENET_2 ||
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pci_dev->device == PCI_DEVICE_ID_NVIDIA_NVENET_3 ||
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pci_dev->device == PCI_DEVICE_ID_NVIDIA_NVENET_12 ||
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pci_dev->device == PCI_DEVICE_ID_NVIDIA_NVENET_13) {
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np->desc_ver = DESC_VER_1;
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else
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np->pkt_limit = NV_PKTLIMIT_1;
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} else {
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np->desc_ver = DESC_VER_2;
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np->pkt_limit = NV_PKTLIMIT_2;
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}
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err = -ENOMEM;
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np->base = ioremap(addr, NV_PCI_REGSZ);
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