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Memory controller drivers for v5.9, part 2
1. Minor cleanups and fixes of multiple memory controller drivers,
mostly around code quality and readability,
2. Add Git repository to drivers/memory entry in MAINTAINERS,
3. Allow MIPS jz4780 FUSE driver to probe by removing conflicting memory
region with jz4780_nemc.
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Merge tag 'memory-controller-drv-5.9-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into arm/drivers
Memory controller drivers for v5.9, part 2
1. Minor cleanups and fixes of multiple memory controller drivers,
mostly around code quality and readability,
2. Add Git repository to drivers/memory entry in MAINTAINERS,
3. Allow MIPS jz4780 FUSE driver to probe by removing conflicting memory
region with jz4780_nemc.
* tag 'memory-controller-drv-5.9-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl:
memory: jz4780_nemc: Only request IO memory the driver will use
MAINTAINERS: Add Git repository for memory controller drivers
memory: brcmstb_dpfe: Fix language typo
memory: samsung: exynos5422-dmc: Correct white space issues
memory: samsung: exynos-srom: Correct alignment
memory: pl172: Enclose macro argument usage in parenthesis
memory: of: Correct kerneldoc
memory: omap-gpmc: Fix language typo
memory: omap-gpmc: Correct white space issues
memory: omap-gpmc: Use 'unsigned int' for consistency
memory: omap-gpmc: Enclose macro argument usage in parenthesis
memory: omap-gpmc: Correct kerneldoc
memory: mvebu-devbus: Align with open parenthesis
memory: mvebu-devbus: Add missing braces to all arms of if statement
memory: bt1-l2-ctl: Add blank lines after declarations
Link: https://lore.kernel.org/r/20200729163008.5820-1-krzk@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
d7c6dbc02e
@ -11089,6 +11089,7 @@ MEMORY CONTROLLER DRIVERS
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M: Krzysztof Kozlowski <krzk@kernel.org>
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L: linux-kernel@vger.kernel.org
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S: Maintained
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T: git git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl.git
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F: Documentation/devicetree/bindings/memory-controllers/
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F: drivers/memory/
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@ -23,7 +23,7 @@
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* - BE kernel + LE firmware image
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* - BE kernel + BE firmware image
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*
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* The DPCU always runs in big endian mode. The firwmare image, however, can
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* The DPCU always runs in big endian mode. The firmware image, however, can
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* be in either format. Also, communication between host CPU and DCPU is
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* always in little endian.
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*/
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@ -66,6 +66,7 @@ struct l2_ctl_device_attribute {
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struct device_attribute dev_attr;
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enum l2_ctl_stall id;
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};
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#define to_l2_ctl_dev_attr(_dev_attr) \
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container_of(_dev_attr, struct l2_ctl_device_attribute, dev_attr)
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@ -242,6 +243,7 @@ static ssize_t l2_ctl_latency_store(struct device *dev,
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return count;
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}
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static L2_CTL_ATTR_RW(l2_ws_latency, l2_ctl_latency, L2_WS_STALL);
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static L2_CTL_ATTR_RW(l2_tag_latency, l2_ctl_latency, L2_TAG_STALL);
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static L2_CTL_ATTR_RW(l2_data_latency, l2_ctl_latency, L2_DATA_STALL);
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@ -8,6 +8,7 @@
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#include <linux/clk.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/math64.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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@ -22,6 +23,8 @@
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#define NEMC_SMCRn(n) (0x14 + (((n) - 1) * 4))
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#define NEMC_NFCSR 0x50
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#define NEMC_REG_LEN 0x54
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#define NEMC_SMCR_SMT BIT(0)
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#define NEMC_SMCR_BW_SHIFT 6
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#define NEMC_SMCR_BW_MASK (0x3 << NEMC_SMCR_BW_SHIFT)
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@ -288,7 +291,19 @@ static int jz4780_nemc_probe(struct platform_device *pdev)
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nemc->dev = dev;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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nemc->base = devm_ioremap_resource(dev, res);
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/*
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* The driver currently only uses the registers up to offset
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* NEMC_REG_LEN. Since the EFUSE registers are in the middle of the
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* NEMC registers, we only request the registers we will use for now;
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* that way the EFUSE driver can probe too.
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*/
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if (!devm_request_mem_region(dev, res->start, NEMC_REG_LEN, dev_name(dev))) {
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dev_err(dev, "unable to request I/O memory region\n");
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return -EBUSY;
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}
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nemc->base = devm_ioremap(dev, res->start, NEMC_REG_LEN);
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if (IS_ERR(nemc->base)) {
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dev_err(dev, "failed to get I/O memory\n");
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return PTR_ERR(nemc->base);
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@ -124,32 +124,32 @@ static int devbus_get_timing_params(struct devbus *devbus,
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* The bus width is encoded into the register as 0 for 8 bits,
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* and 1 for 16 bits, so we do the necessary conversion here.
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*/
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if (r->bus_width == 8)
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if (r->bus_width == 8) {
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r->bus_width = 0;
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else if (r->bus_width == 16)
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} else if (r->bus_width == 16) {
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r->bus_width = 1;
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else {
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} else {
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dev_err(devbus->dev, "invalid bus width %d\n", r->bus_width);
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return -EINVAL;
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}
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err = get_timing_param_ps(devbus, node, "devbus,badr-skew-ps",
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&r->badr_skew);
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&r->badr_skew);
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if (err < 0)
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return err;
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err = get_timing_param_ps(devbus, node, "devbus,turn-off-ps",
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&r->turn_off);
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&r->turn_off);
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if (err < 0)
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return err;
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err = get_timing_param_ps(devbus, node, "devbus,acc-first-ps",
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&r->acc_first);
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&r->acc_first);
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if (err < 0)
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return err;
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err = get_timing_param_ps(devbus, node, "devbus,acc-next-ps",
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&r->acc_next);
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&r->acc_next);
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if (err < 0)
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return err;
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@ -175,17 +175,17 @@ static int devbus_get_timing_params(struct devbus *devbus,
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}
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err = get_timing_param_ps(devbus, node, "devbus,ale-wr-ps",
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&w->ale_wr);
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&w->ale_wr);
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if (err < 0)
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return err;
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err = get_timing_param_ps(devbus, node, "devbus,wr-low-ps",
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&w->wr_low);
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&w->wr_low);
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if (err < 0)
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return err;
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err = get_timing_param_ps(devbus, node, "devbus,wr-high-ps",
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&w->wr_high);
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&w->wr_high);
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if (err < 0)
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return err;
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@ -18,7 +18,7 @@
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/**
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* of_get_min_tck() - extract min timing values for ddr
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* @np: pointer to ddr device tree node
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* @device: device requesting for min timing values
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* @dev: device requesting for min timing values
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*
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* Populates the lpddr2_min_tck structure by extracting data
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* from device tree node. Returns a pointer to the populated
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@ -155,7 +155,7 @@ EXPORT_SYMBOL(of_get_ddr_timings);
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/**
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* of_lpddr3_get_min_tck() - extract min timing values for lpddr3
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* @np: pointer to ddr device tree node
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* @device: device requesting for min timing values
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* @dev: device requesting for min timing values
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*
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* Populates the lpddr3_min_tck structure by extracting data
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* from device tree node. Returns a pointer to the populated
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@ -109,8 +109,8 @@
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#define ENABLE_PREFETCH (0x1 << 7)
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#define DMA_MPU_MODE 2
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#define GPMC_REVISION_MAJOR(l) ((l >> 4) & 0xf)
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#define GPMC_REVISION_MINOR(l) (l & 0xf)
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#define GPMC_REVISION_MAJOR(l) (((l) >> 4) & 0xf)
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#define GPMC_REVISION_MINOR(l) ((l) & 0xf)
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#define GPMC_HAS_WR_ACCESS 0x1
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#define GPMC_HAS_WR_DATA_MUX_BUS 0x2
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@ -141,27 +141,27 @@
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#define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28)
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#define GPMC_CONFIG1_WRITETYPE_ASYNC (0 << 27)
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#define GPMC_CONFIG1_WRITETYPE_SYNC (1 << 27)
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#define GPMC_CONFIG1_CLKACTIVATIONTIME(val) ((val & 3) << 25)
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#define GPMC_CONFIG1_CLKACTIVATIONTIME(val) (((val) & 3) << 25)
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/** CLKACTIVATIONTIME Max Ticks */
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#define GPMC_CONFIG1_CLKACTIVATIONTIME_MAX 2
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#define GPMC_CONFIG1_PAGE_LEN(val) ((val & 3) << 23)
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#define GPMC_CONFIG1_PAGE_LEN(val) (((val) & 3) << 23)
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/** ATTACHEDDEVICEPAGELENGTH Max Value */
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#define GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX 2
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#define GPMC_CONFIG1_WAIT_READ_MON (1 << 22)
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#define GPMC_CONFIG1_WAIT_WRITE_MON (1 << 21)
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#define GPMC_CONFIG1_WAIT_MON_TIME(val) ((val & 3) << 18)
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#define GPMC_CONFIG1_WAIT_MON_TIME(val) (((val) & 3) << 18)
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/** WAITMONITORINGTIME Max Ticks */
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#define GPMC_CONFIG1_WAITMONITORINGTIME_MAX 2
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#define GPMC_CONFIG1_WAIT_PIN_SEL(val) ((val & 3) << 16)
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#define GPMC_CONFIG1_DEVICESIZE(val) ((val & 3) << 12)
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#define GPMC_CONFIG1_WAIT_PIN_SEL(val) (((val) & 3) << 16)
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#define GPMC_CONFIG1_DEVICESIZE(val) (((val) & 3) << 12)
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#define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1)
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/** DEVICESIZE Max Value */
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#define GPMC_CONFIG1_DEVICESIZE_MAX 1
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#define GPMC_CONFIG1_DEVICETYPE(val) ((val & 3) << 10)
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#define GPMC_CONFIG1_DEVICETYPE(val) (((val) & 3) << 10)
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#define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0)
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#define GPMC_CONFIG1_MUXTYPE(val) ((val & 3) << 8)
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#define GPMC_CONFIG1_MUXTYPE(val) (((val) & 3) << 8)
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#define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4)
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#define GPMC_CONFIG1_FCLK_DIV(val) (val & 3)
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#define GPMC_CONFIG1_FCLK_DIV(val) ((val) & 3)
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#define GPMC_CONFIG1_FCLK_DIV2 (GPMC_CONFIG1_FCLK_DIV(1))
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#define GPMC_CONFIG1_FCLK_DIV3 (GPMC_CONFIG1_FCLK_DIV(2))
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#define GPMC_CONFIG1_FCLK_DIV4 (GPMC_CONFIG1_FCLK_DIV(3))
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@ -246,7 +246,7 @@ static DEFINE_SPINLOCK(gpmc_mem_lock);
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static unsigned int gpmc_cs_num = GPMC_CS_NUM;
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static unsigned int gpmc_nr_waitpins;
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static resource_size_t phys_base, mem_size;
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static unsigned gpmc_capability;
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static unsigned int gpmc_capability;
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static void __iomem *gpmc_base;
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static struct clk *gpmc_l3_clk;
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@ -292,15 +292,14 @@ static unsigned long gpmc_get_fclk_period(void)
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/**
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* gpmc_get_clk_period - get period of selected clock domain in ps
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* @cs Chip Select Region.
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* @cd Clock Domain.
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* @cs: Chip Select Region.
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* @cd: Clock Domain.
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*
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* GPMC_CS_CONFIG1 GPMCFCLKDIVIDER for cs has to be setup
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* prior to calling this function with GPMC_CD_CLK.
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*/
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static unsigned long gpmc_get_clk_period(int cs, enum gpmc_clk_domain cd)
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{
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unsigned long tick_ps = gpmc_get_fclk_period();
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u32 l;
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int div;
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@ -320,7 +319,6 @@ static unsigned long gpmc_get_clk_period(int cs, enum gpmc_clk_domain cd)
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}
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return tick_ps;
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}
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static unsigned int gpmc_ns_to_clk_ticks(unsigned int time_ns, int cs,
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@ -412,7 +410,7 @@ static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p)
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* @reg: GPMC_CS_CONFIGn register offset.
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* @st_bit: Start Bit
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* @end_bit: End Bit. Must be >= @st_bit.
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* @ma:x Maximum parameter value (before optional @shift).
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* @max: Maximum parameter value (before optional @shift).
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* If 0, maximum is as high as @st_bit and @end_bit allow.
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* @name: DTS node name, w/o "gpmc,"
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* @cd: Clock Domain of timing parameter.
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@ -512,7 +510,7 @@ static void gpmc_cs_show_timings(int cs, const char *desc)
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GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 4, 4, "time-para-granularity");
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GPMC_GET_RAW(GPMC_CS_CONFIG1, 8, 9, "mux-add-data");
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GPMC_GET_RAW_SHIFT_MAX(GPMC_CS_CONFIG1, 12, 13, 1,
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GPMC_CONFIG1_DEVICESIZE_MAX, "device-width");
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GPMC_CONFIG1_DEVICESIZE_MAX, "device-width");
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GPMC_GET_RAW(GPMC_CS_CONFIG1, 16, 17, "wait-pin");
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GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 21, 21, "wait-on-write");
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GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 22, 22, "wait-on-read");
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@ -626,9 +624,8 @@ static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, int max
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l = gpmc_cs_read_reg(cs, reg);
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#ifdef CONFIG_OMAP_GPMC_DEBUG
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pr_info(
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"GPMC CS%d: %-17s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
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cs, name, ticks, gpmc_get_clk_period(cs, cd) * ticks / 1000,
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pr_info("GPMC CS%d: %-17s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
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cs, name, ticks, gpmc_get_clk_period(cs, cd) * ticks / 1000,
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(l >> st_bit) & mask, time);
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#endif
|
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l &= ~(mask << st_bit);
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@ -663,7 +660,6 @@ static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, int max
|
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*/
|
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static int gpmc_calc_waitmonitoring_divider(unsigned int wait_monitoring)
|
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{
|
||||
|
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int div = gpmc_ns_to_ticks(wait_monitoring);
|
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|
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div += GPMC_CONFIG1_WAITMONITORINGTIME_MAX - 1;
|
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@ -675,7 +671,6 @@ static int gpmc_calc_waitmonitoring_divider(unsigned int wait_monitoring)
|
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div = 1;
|
||||
|
||||
return div;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
@ -729,7 +724,6 @@ int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t,
|
||||
if (!s->sync_read && !s->sync_write &&
|
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(s->wait_on_read || s->wait_on_write)
|
||||
) {
|
||||
|
||||
div = gpmc_calc_waitmonitoring_divider(t->wait_monitoring);
|
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if (div < 0) {
|
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pr_err("%s: waitmonitoringtime %3d ns too large for greatest gpmcfclkdivider.\n",
|
||||
@ -1088,7 +1082,7 @@ static struct gpmc_nand_ops nand_ops = {
|
||||
|
||||
/**
|
||||
* gpmc_omap_get_nand_ops - Get the GPMC NAND interface
|
||||
* @regs: the GPMC NAND register map exclusive for NAND use.
|
||||
* @reg: the GPMC NAND register map exclusive for NAND use.
|
||||
* @cs: GPMC chip select number on which the NAND sits. The
|
||||
* register map returned will be specific to this chip select.
|
||||
*
|
||||
@ -1243,7 +1237,7 @@ int gpmc_omap_onenand_set_timings(struct device *dev, int cs, int freq,
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(gpmc_omap_onenand_set_timings);
|
||||
|
||||
int gpmc_get_client_irq(unsigned irq_config)
|
||||
int gpmc_get_client_irq(unsigned int irq_config)
|
||||
{
|
||||
if (!gpmc_irq_domain) {
|
||||
pr_warn("%s called before GPMC IRQ domain available\n",
|
||||
@ -1466,7 +1460,6 @@ static void gpmc_mem_exit(void)
|
||||
continue;
|
||||
gpmc_cs_delete_mem(cs);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
static void gpmc_mem_init(void)
|
||||
@ -1635,17 +1628,14 @@ static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t,
|
||||
/* oe_on */
|
||||
temp = dev_t->t_oeasu;
|
||||
if (mux)
|
||||
temp = max_t(u32, temp,
|
||||
gpmc_t->adv_rd_off + dev_t->t_aavdh);
|
||||
temp = max_t(u32, temp, gpmc_t->adv_rd_off + dev_t->t_aavdh);
|
||||
gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
|
||||
|
||||
/* access */
|
||||
temp = max_t(u32, dev_t->t_iaa, /* XXX: remove t_iaa in async ? */
|
||||
gpmc_t->oe_on + dev_t->t_oe);
|
||||
temp = max_t(u32, temp,
|
||||
gpmc_t->cs_on + dev_t->t_ce);
|
||||
temp = max_t(u32, temp,
|
||||
gpmc_t->adv_on + dev_t->t_aa);
|
||||
gpmc_t->oe_on + dev_t->t_oe);
|
||||
temp = max_t(u32, temp, gpmc_t->cs_on + dev_t->t_ce);
|
||||
temp = max_t(u32, temp, gpmc_t->adv_on + dev_t->t_aa);
|
||||
gpmc_t->access = gpmc_round_ps_to_ticks(temp);
|
||||
|
||||
gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
|
||||
@ -2091,7 +2081,7 @@ static int gpmc_probe_generic_child(struct platform_device *pdev,
|
||||
gpmc_cs_disable_mem(cs);
|
||||
|
||||
/*
|
||||
* FIXME: gpmc_cs_request() will map the CS to an arbitary
|
||||
* FIXME: gpmc_cs_request() will map the CS to an arbitrary
|
||||
* location in the gpmc address space. When booting with
|
||||
* device-tree we want the NOR flash to be mapped to the
|
||||
* location specified in the device-tree blob. So remap the
|
||||
|
||||
@ -21,7 +21,7 @@
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/time.h>
|
||||
|
||||
#define MPMC_STATIC_CFG(n) (0x200 + 0x20 * n)
|
||||
#define MPMC_STATIC_CFG(n) (0x200 + 0x20 * (n))
|
||||
#define MPMC_STATIC_CFG_MW_8BIT 0x0
|
||||
#define MPMC_STATIC_CFG_MW_16BIT 0x1
|
||||
#define MPMC_STATIC_CFG_MW_32BIT 0x2
|
||||
@ -31,17 +31,17 @@
|
||||
#define MPMC_STATIC_CFG_EW BIT(8)
|
||||
#define MPMC_STATIC_CFG_B BIT(19)
|
||||
#define MPMC_STATIC_CFG_P BIT(20)
|
||||
#define MPMC_STATIC_WAIT_WEN(n) (0x204 + 0x20 * n)
|
||||
#define MPMC_STATIC_WAIT_WEN(n) (0x204 + 0x20 * (n))
|
||||
#define MPMC_STATIC_WAIT_WEN_MAX 0x0f
|
||||
#define MPMC_STATIC_WAIT_OEN(n) (0x208 + 0x20 * n)
|
||||
#define MPMC_STATIC_WAIT_OEN(n) (0x208 + 0x20 * (n))
|
||||
#define MPMC_STATIC_WAIT_OEN_MAX 0x0f
|
||||
#define MPMC_STATIC_WAIT_RD(n) (0x20c + 0x20 * n)
|
||||
#define MPMC_STATIC_WAIT_RD(n) (0x20c + 0x20 * (n))
|
||||
#define MPMC_STATIC_WAIT_RD_MAX 0x1f
|
||||
#define MPMC_STATIC_WAIT_PAGE(n) (0x210 + 0x20 * n)
|
||||
#define MPMC_STATIC_WAIT_PAGE(n) (0x210 + 0x20 * (n))
|
||||
#define MPMC_STATIC_WAIT_PAGE_MAX 0x1f
|
||||
#define MPMC_STATIC_WAIT_WR(n) (0x214 + 0x20 * n)
|
||||
#define MPMC_STATIC_WAIT_WR(n) (0x214 + 0x20 * (n))
|
||||
#define MPMC_STATIC_WAIT_WR_MAX 0x1f
|
||||
#define MPMC_STATIC_WAIT_TURN(n) (0x218 + 0x20 * n)
|
||||
#define MPMC_STATIC_WAIT_TURN(n) (0x218 + 0x20 * (n))
|
||||
#define MPMC_STATIC_WAIT_TURN_MAX 0x0f
|
||||
|
||||
/* Maximum number of static chip selects */
|
||||
|
||||
@ -47,9 +47,9 @@ struct exynos_srom {
|
||||
struct exynos_srom_reg_dump *reg_offset;
|
||||
};
|
||||
|
||||
static struct exynos_srom_reg_dump *exynos_srom_alloc_reg_dump(
|
||||
const unsigned long *rdump,
|
||||
unsigned long nr_rdump)
|
||||
static struct exynos_srom_reg_dump *
|
||||
exynos_srom_alloc_reg_dump(const unsigned long *rdump,
|
||||
unsigned long nr_rdump)
|
||||
{
|
||||
struct exynos_srom_reg_dump *rd;
|
||||
unsigned int i;
|
||||
@ -116,7 +116,7 @@ static int exynos_srom_probe(struct platform_device *pdev)
|
||||
}
|
||||
|
||||
srom = devm_kzalloc(&pdev->dev,
|
||||
sizeof(struct exynos_srom), GFP_KERNEL);
|
||||
sizeof(struct exynos_srom), GFP_KERNEL);
|
||||
if (!srom)
|
||||
return -ENOMEM;
|
||||
|
||||
@ -130,7 +130,7 @@ static int exynos_srom_probe(struct platform_device *pdev)
|
||||
platform_set_drvdata(pdev, srom);
|
||||
|
||||
srom->reg_offset = exynos_srom_alloc_reg_dump(exynos_srom_offsets,
|
||||
ARRAY_SIZE(exynos_srom_offsets));
|
||||
ARRAY_SIZE(exynos_srom_offsets));
|
||||
if (!srom->reg_offset) {
|
||||
iounmap(srom->reg_base);
|
||||
return -ENOMEM;
|
||||
@ -157,16 +157,16 @@ static int exynos_srom_probe(struct platform_device *pdev)
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static void exynos_srom_save(void __iomem *base,
|
||||
struct exynos_srom_reg_dump *rd,
|
||||
unsigned int num_regs)
|
||||
struct exynos_srom_reg_dump *rd,
|
||||
unsigned int num_regs)
|
||||
{
|
||||
for (; num_regs > 0; --num_regs, ++rd)
|
||||
rd->value = readl(base + rd->offset);
|
||||
}
|
||||
|
||||
static void exynos_srom_restore(void __iomem *base,
|
||||
const struct exynos_srom_reg_dump *rd,
|
||||
unsigned int num_regs)
|
||||
const struct exynos_srom_reg_dump *rd,
|
||||
unsigned int num_regs)
|
||||
{
|
||||
for (; num_regs > 0; --num_regs, ++rd)
|
||||
writel(rd->value, base + rd->offset);
|
||||
@ -177,7 +177,7 @@ static int exynos_srom_suspend(struct device *dev)
|
||||
struct exynos_srom *srom = dev_get_drvdata(dev);
|
||||
|
||||
exynos_srom_save(srom->reg_base, srom->reg_offset,
|
||||
ARRAY_SIZE(exynos_srom_offsets));
|
||||
ARRAY_SIZE(exynos_srom_offsets));
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -186,7 +186,7 @@ static int exynos_srom_resume(struct device *dev)
|
||||
struct exynos_srom *srom = dev_get_drvdata(dev);
|
||||
|
||||
exynos_srom_restore(srom->reg_base, srom->reg_offset,
|
||||
ARRAY_SIZE(exynos_srom_offsets));
|
||||
ARRAY_SIZE(exynos_srom_offsets));
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -1398,7 +1398,7 @@ static int exynos5_dmc_probe(struct platform_device *pdev)
|
||||
return PTR_ERR(dmc->base_drexi1);
|
||||
|
||||
dmc->clk_regmap = syscon_regmap_lookup_by_phandle(np,
|
||||
"samsung,syscon-clk");
|
||||
"samsung,syscon-clk");
|
||||
if (IS_ERR(dmc->clk_regmap))
|
||||
return PTR_ERR(dmc->clk_regmap);
|
||||
|
||||
@ -1477,7 +1477,6 @@ static int exynos5_dmc_probe(struct platform_device *pdev)
|
||||
exynos5_dmc_df_profile.polling_ms = 500;
|
||||
}
|
||||
|
||||
|
||||
dmc->df = devm_devfreq_add_device(dev, &exynos5_dmc_df_profile,
|
||||
DEVFREQ_GOV_SIMPLE_ONDEMAND,
|
||||
&dmc->gov_data);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user