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drm/mode: add the CVT algorithm in kernel space
Add the CVT algorithm in kernel space. And this function can be called to generate the required modeline. I copied it from the file of xserver/hw/xfree86/modes/xf86cvt.c. What I have done is to translate it by using integer calculation. This is to avoid the float-point calculation in kernel space. [airlied:- cleaned up some bits] Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by: Dave Airlie <airlied@linux.ie>
This commit is contained in:
Zhao Yakui
Dave Airlie
parent
e9e961c9a8
commit
d782c3f95c
@ -8,6 +8,7 @@
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* Copyright © 2007 Dave Airlie
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* Copyright © 2007-2008 Intel Corporation
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* Jesse Barnes <jesse.barnes@intel.com>
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* Copyright 2005-2006 Luc Verhaegen
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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@ -61,6 +62,224 @@ void drm_mode_debug_printmodeline(struct drm_display_mode *mode)
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}
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EXPORT_SYMBOL(drm_mode_debug_printmodeline);
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/**
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* drm_cvt_mode -create a modeline based on CVT algorithm
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* @dev: DRM device
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* @hdisplay: hdisplay size
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* @vdisplay: vdisplay size
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* @vrefresh : vrefresh rate
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* @reduced : Whether the GTF calculation is simplified
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* @interlaced:Whether the interlace is supported
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*
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* LOCKING:
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* none.
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*
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* return the modeline based on CVT algorithm
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*
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* This function is called to generate the modeline based on CVT algorithm
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* according to the hdisplay, vdisplay, vrefresh.
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* It is based from the VESA(TM) Coordinated Video Timing Generator by
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* Graham Loveridge April 9, 2003 available at
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* http://www.vesa.org/public/CVT/CVTd6r1.xls
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*
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* And it is copied from xf86CVTmode in xserver/hw/xfree86/modes/xf86cvt.c.
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* What I have done is to translate it by using integer calculation.
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*/
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#define HV_FACTOR 1000
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struct drm_display_mode *drm_cvt_mode(struct drm_device *dev, int hdisplay,
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int vdisplay, int vrefresh,
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bool reduced, bool interlaced)
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{
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/* 1) top/bottom margin size (% of height) - default: 1.8, */
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#define CVT_MARGIN_PERCENTAGE 18
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/* 2) character cell horizontal granularity (pixels) - default 8 */
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#define CVT_H_GRANULARITY 8
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/* 3) Minimum vertical porch (lines) - default 3 */
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#define CVT_MIN_V_PORCH 3
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/* 4) Minimum number of vertical back porch lines - default 6 */
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#define CVT_MIN_V_BPORCH 6
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/* Pixel Clock step (kHz) */
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#define CVT_CLOCK_STEP 250
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struct drm_display_mode *drm_mode;
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bool margins = false;
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unsigned int vfieldrate, hperiod;
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int hdisplay_rnd, hmargin, vdisplay_rnd, vmargin, vsync;
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int interlace;
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/* allocate the drm_display_mode structure. If failure, we will
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* return directly
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*/
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drm_mode = drm_mode_create(dev);
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if (!drm_mode)
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return NULL;
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/* the CVT default refresh rate is 60Hz */
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if (!vrefresh)
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vrefresh = 60;
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/* the required field fresh rate */
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if (interlaced)
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vfieldrate = vrefresh * 2;
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else
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vfieldrate = vrefresh;
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/* horizontal pixels */
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hdisplay_rnd = hdisplay - (hdisplay % CVT_H_GRANULARITY);
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/* determine the left&right borders */
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hmargin = 0;
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if (margins) {
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hmargin = hdisplay_rnd * CVT_MARGIN_PERCENTAGE / 1000;
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hmargin -= hmargin % CVT_H_GRANULARITY;
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}
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/* find the total active pixels */
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drm_mode->hdisplay = hdisplay_rnd + 2 * hmargin;
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/* find the number of lines per field */
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if (interlaced)
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vdisplay_rnd = vdisplay / 2;
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else
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vdisplay_rnd = vdisplay;
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/* find the top & bottom borders */
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vmargin = 0;
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if (margins)
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vmargin = vdisplay_rnd * CVT_MARGIN_PERCENTAGE / 1000;
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drm_mode->vdisplay = vdisplay_rnd + 2 * vmargin;
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/* Interlaced */
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if (interlaced)
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interlace = 1;
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else
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interlace = 0;
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/* Determine VSync Width from aspect ratio */
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if (!(vdisplay % 3) && ((vdisplay * 4 / 3) == hdisplay))
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vsync = 4;
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else if (!(vdisplay % 9) && ((vdisplay * 16 / 9) == hdisplay))
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vsync = 5;
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else if (!(vdisplay % 10) && ((vdisplay * 16 / 10) == hdisplay))
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vsync = 6;
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else if (!(vdisplay % 4) && ((vdisplay * 5 / 4) == hdisplay))
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vsync = 7;
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else if (!(vdisplay % 9) && ((vdisplay * 15 / 9) == hdisplay))
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vsync = 7;
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else /* custom */
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vsync = 10;
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if (!reduced) {
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/* simplify the GTF calculation */
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/* 4) Minimum time of vertical sync + back porch interval (µs)
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* default 550.0
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*/
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int tmp1, tmp2;
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#define CVT_MIN_VSYNC_BP 550
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/* 3) Nominal HSync width (% of line period) - default 8 */
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#define CVT_HSYNC_PERCENTAGE 8
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unsigned int hblank_percentage;
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int vsyncandback_porch, vback_porch, hblank;
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/* estimated the horizontal period */
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tmp1 = HV_FACTOR * 1000000 -
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CVT_MIN_VSYNC_BP * HV_FACTOR * vfieldrate;
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tmp2 = (vdisplay_rnd + 2 * vmargin + CVT_MIN_V_PORCH) * 2 +
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interlace;
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hperiod = tmp1 * 2 / (tmp2 * vfieldrate);
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tmp1 = CVT_MIN_VSYNC_BP * HV_FACTOR / hperiod + 1;
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/* 9. Find number of lines in sync + backporch */
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if (tmp1 < (vsync + CVT_MIN_V_PORCH))
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vsyncandback_porch = vsync + CVT_MIN_V_PORCH;
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else
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vsyncandback_porch = tmp1;
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/* 10. Find number of lines in back porch */
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vback_porch = vsyncandback_porch - vsync;
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drm_mode->vtotal = vdisplay_rnd + 2 * vmargin +
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vsyncandback_porch + CVT_MIN_V_PORCH;
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/* 5) Definition of Horizontal blanking time limitation */
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/* Gradient (%/kHz) - default 600 */
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#define CVT_M_FACTOR 600
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/* Offset (%) - default 40 */
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#define CVT_C_FACTOR 40
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/* Blanking time scaling factor - default 128 */
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#define CVT_K_FACTOR 128
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/* Scaling factor weighting - default 20 */
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#define CVT_J_FACTOR 20
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#define CVT_M_PRIME (CVT_M_FACTOR * CVT_K_FACTOR / 256)
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#define CVT_C_PRIME ((CVT_C_FACTOR - CVT_J_FACTOR) * CVT_K_FACTOR / 256 + \
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CVT_J_FACTOR)
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/* 12. Find ideal blanking duty cycle from formula */
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hblank_percentage = CVT_C_PRIME * HV_FACTOR - CVT_M_PRIME *
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hperiod / 1000;
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/* 13. Blanking time */
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if (hblank_percentage < 20 * HV_FACTOR)
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hblank_percentage = 20 * HV_FACTOR;
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hblank = drm_mode->hdisplay * hblank_percentage /
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(100 * HV_FACTOR - hblank_percentage);
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hblank -= hblank % (2 * CVT_H_GRANULARITY);
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/* 14. find the total pixes per line */
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drm_mode->htotal = drm_mode->hdisplay + hblank;
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drm_mode->hsync_end = drm_mode->hdisplay + hblank / 2;
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drm_mode->hsync_start = drm_mode->hsync_end -
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(drm_mode->htotal * CVT_HSYNC_PERCENTAGE) / 100;
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drm_mode->hsync_start += CVT_H_GRANULARITY -
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drm_mode->hsync_start % CVT_H_GRANULARITY;
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/* fill the Vsync values */
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drm_mode->vsync_start = drm_mode->vdisplay + CVT_MIN_V_PORCH;
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drm_mode->vsync_end = drm_mode->vsync_start + vsync;
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} else {
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/* Reduced blanking */
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/* Minimum vertical blanking interval time (µs)- default 460 */
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#define CVT_RB_MIN_VBLANK 460
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/* Fixed number of clocks for horizontal sync */
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#define CVT_RB_H_SYNC 32
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/* Fixed number of clocks for horizontal blanking */
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#define CVT_RB_H_BLANK 160
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/* Fixed number of lines for vertical front porch - default 3*/
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#define CVT_RB_VFPORCH 3
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int vbilines;
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int tmp1, tmp2;
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/* 8. Estimate Horizontal period. */
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tmp1 = HV_FACTOR * 1000000 -
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CVT_RB_MIN_VBLANK * HV_FACTOR * vfieldrate;
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tmp2 = vdisplay_rnd + 2 * vmargin;
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hperiod = tmp1 / (tmp2 * vfieldrate);
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/* 9. Find number of lines in vertical blanking */
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vbilines = CVT_RB_MIN_VBLANK * HV_FACTOR / hperiod + 1;
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/* 10. Check if vertical blanking is sufficient */
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if (vbilines < (CVT_RB_VFPORCH + vsync + CVT_MIN_V_BPORCH))
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vbilines = CVT_RB_VFPORCH + vsync + CVT_MIN_V_BPORCH;
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/* 11. Find total number of lines in vertical field */
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drm_mode->vtotal = vdisplay_rnd + 2 * vmargin + vbilines;
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/* 12. Find total number of pixels in a line */
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drm_mode->htotal = drm_mode->hdisplay + CVT_RB_H_BLANK;
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/* Fill in HSync values */
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drm_mode->hsync_end = drm_mode->hdisplay + CVT_RB_H_BLANK / 2;
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drm_mode->hsync_start = drm_mode->hsync_end = CVT_RB_H_SYNC;
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}
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/* 15/13. Find pixel clock frequency (kHz for xf86) */
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drm_mode->clock = drm_mode->htotal * HV_FACTOR * 1000 / hperiod;
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drm_mode->clock -= drm_mode->clock % CVT_CLOCK_STEP;
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/* 18/16. Find actual vertical frame frequency */
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/* ignore - just set the mode flag for interlaced */
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if (interlaced)
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drm_mode->vtotal *= 2;
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/* Fill the mode line name */
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drm_mode_set_name(drm_mode);
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if (reduced)
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drm_mode->flags |= (DRM_MODE_FLAG_PHSYNC |
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DRM_MODE_FLAG_NVSYNC);
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else
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drm_mode->flags |= (DRM_MODE_FLAG_PVSYNC |
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DRM_MODE_FLAG_NHSYNC);
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if (interlaced)
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drm_mode->flags |= DRM_MODE_FLAG_INTERLACE;
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return drm_mode;
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}
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EXPORT_SYMBOL(drm_cvt_mode);
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/**
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* drm_mode_set_name - set the name on a mode
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* @mode: name will be set in this mode
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@ -736,4 +736,7 @@ extern int drm_mode_gamma_get_ioctl(struct drm_device *dev,
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extern int drm_mode_gamma_set_ioctl(struct drm_device *dev,
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void *data, struct drm_file *file_priv);
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extern bool drm_detect_hdmi_monitor(struct edid *edid);
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extern struct drm_display_mode *drm_cvt_mode(struct drm_device *dev,
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int hdisplay, int vdisplay, int vrefresh,
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bool reduced, bool interlaced);
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#endif /* __DRM_CRTC_H__ */
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