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ahci: Implement SATA AHCI FIS-based switching support
Tested on AMD internal reference board. Signed-off-by: Shane Huang <shane.huang@amd.com> Acked-by: Tejun Heo <tj@kernel.org> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
This commit is contained in:
Shane Huang
Jeff Garzik
parent
d817898c2f
commit
d6ef31539d
@ -93,6 +93,9 @@ enum {
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AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
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AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
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AHCI_RX_FIS_SZ,
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AHCI_PORT_PRIV_FBS_DMA_SZ = AHCI_CMD_SLOT_SZ +
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AHCI_CMD_TBL_AR_SZ +
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(AHCI_RX_FIS_SZ * 16),
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AHCI_IRQ_ON_SG = (1 << 31),
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AHCI_CMD_ATAPI = (1 << 5),
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AHCI_CMD_WRITE = (1 << 6),
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@ -170,6 +173,7 @@ enum {
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PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
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PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
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PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */
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PORT_FBS = 0x40, /* FIS-based Switching */
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/* PORT_IRQ_{STAT,MASK} bits */
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PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
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@ -208,6 +212,7 @@ enum {
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PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */
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PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */
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PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
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PORT_CMD_FBSCP = (1 << 22), /* FBS Capable Port */
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PORT_CMD_PMP = (1 << 17), /* PMP attached */
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PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
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PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
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@ -222,6 +227,14 @@ enum {
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PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
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PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
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PORT_FBS_DWE_OFFSET = 16, /* FBS device with error offset */
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PORT_FBS_ADO_OFFSET = 12, /* FBS active dev optimization offset */
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PORT_FBS_DEV_OFFSET = 8, /* FBS device to issue offset */
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PORT_FBS_DEV_MASK = (0xf << PORT_FBS_DEV_OFFSET), /* FBS.DEV */
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PORT_FBS_SDE = (1 << 2), /* FBS single device error */
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PORT_FBS_DEC = (1 << 1), /* FBS device error clear */
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PORT_FBS_EN = (1 << 0), /* Enable FBS */
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/* hpriv->flags bits */
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AHCI_HFLAG_NO_NCQ = (1 << 0),
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AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */
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@ -304,6 +317,9 @@ struct ahci_port_priv {
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unsigned int ncq_saw_dmas:1;
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unsigned int ncq_saw_sdb:1;
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u32 intr_mask; /* interrupts to enable */
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bool fbs_supported; /* set iff FBS is supported */
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bool fbs_enabled; /* set iff FBS is enabled */
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int fbs_last_dev; /* save FBS.DEV of last FIS */
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/* enclosure management info per PM slot */
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struct ahci_em_priv em_priv[EM_MAX_SLOTS];
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};
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@ -315,9 +331,12 @@ static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
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static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
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static int ahci_port_start(struct ata_port *ap);
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static void ahci_port_stop(struct ata_port *ap);
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static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc);
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static void ahci_qc_prep(struct ata_queued_cmd *qc);
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static void ahci_freeze(struct ata_port *ap);
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static void ahci_thaw(struct ata_port *ap);
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static void ahci_enable_fbs(struct ata_port *ap);
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static void ahci_disable_fbs(struct ata_port *ap);
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static void ahci_pmp_attach(struct ata_port *ap);
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static void ahci_pmp_detach(struct ata_port *ap);
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static int ahci_softreset(struct ata_link *link, unsigned int *class,
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@ -390,7 +409,7 @@ static struct scsi_host_template ahci_sht = {
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static struct ata_port_operations ahci_ops = {
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.inherits = &sata_pmp_port_ops,
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.qc_defer = sata_pmp_qc_defer_cmd_switch,
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.qc_defer = ahci_pmp_qc_defer,
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.qc_prep = ahci_qc_prep,
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.qc_issue = ahci_qc_issue,
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.qc_fill_rtf = ahci_qc_fill_rtf,
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@ -2045,6 +2064,17 @@ static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
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return si;
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}
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static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc)
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{
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struct ata_port *ap = qc->ap;
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struct ahci_port_priv *pp = ap->private_data;
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if (!sata_pmp_attached(ap) || pp->fbs_enabled)
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return ata_std_qc_defer(qc);
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else
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return sata_pmp_qc_defer_cmd_switch(qc);
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}
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static void ahci_qc_prep(struct ata_queued_cmd *qc)
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{
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struct ata_port *ap = qc->ap;
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@ -2083,6 +2113,31 @@ static void ahci_qc_prep(struct ata_queued_cmd *qc)
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ahci_fill_cmd_slot(pp, qc->tag, opts);
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}
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static void ahci_fbs_dec_intr(struct ata_port *ap)
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{
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struct ahci_port_priv *pp = ap->private_data;
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void __iomem *port_mmio = ahci_port_base(ap);
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u32 fbs = readl(port_mmio + PORT_FBS);
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int retries = 3;
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DPRINTK("ENTER\n");
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BUG_ON(!pp->fbs_enabled);
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/* time to wait for DEC is not specified by AHCI spec,
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* add a retry loop for safety.
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*/
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writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS);
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fbs = readl(port_mmio + PORT_FBS);
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while ((fbs & PORT_FBS_DEC) && retries--) {
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udelay(1);
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fbs = readl(port_mmio + PORT_FBS);
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}
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if (fbs & PORT_FBS_DEC)
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dev_printk(KERN_ERR, ap->host->dev,
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"failed to clear device error\n");
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}
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static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
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{
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struct ahci_host_priv *hpriv = ap->host->private_data;
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@ -2091,12 +2146,26 @@ static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
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struct ata_link *link = NULL;
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struct ata_queued_cmd *active_qc;
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struct ata_eh_info *active_ehi;
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bool fbs_need_dec = false;
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u32 serror;
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/* determine active link */
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ata_for_each_link(link, ap, EDGE)
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if (ata_link_active(link))
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break;
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/* determine active link with error */
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if (pp->fbs_enabled) {
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void __iomem *port_mmio = ahci_port_base(ap);
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u32 fbs = readl(port_mmio + PORT_FBS);
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int pmp = fbs >> PORT_FBS_DWE_OFFSET;
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if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links) &&
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ata_link_online(&ap->pmp_link[pmp])) {
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link = &ap->pmp_link[pmp];
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fbs_need_dec = true;
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}
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} else
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ata_for_each_link(link, ap, EDGE)
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if (ata_link_active(link))
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break;
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if (!link)
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link = &ap->link;
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@ -2153,8 +2222,13 @@ static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
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}
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if (irq_stat & PORT_IRQ_IF_ERR) {
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host_ehi->err_mask |= AC_ERR_ATA_BUS;
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host_ehi->action |= ATA_EH_RESET;
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if (fbs_need_dec)
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active_ehi->err_mask |= AC_ERR_DEV;
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else {
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host_ehi->err_mask |= AC_ERR_ATA_BUS;
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host_ehi->action |= ATA_EH_RESET;
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}
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ata_ehi_push_desc(host_ehi, "interface fatal error");
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}
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@ -2169,7 +2243,10 @@ static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
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if (irq_stat & PORT_IRQ_FREEZE)
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ata_port_freeze(ap);
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else
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else if (fbs_need_dec) {
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ata_link_abort(link);
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ahci_fbs_dec_intr(ap);
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} else
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ata_port_abort(ap);
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}
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@ -2222,12 +2299,19 @@ static void ahci_port_intr(struct ata_port *ap)
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/* If the 'N' bit in word 0 of the FIS is set,
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* we just received asynchronous notification.
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* Tell libata about it.
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*
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* Lack of SNotification should not appear in
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* ahci 1.2, so the workaround is unnecessary
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* when FBS is enabled.
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*/
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const __le32 *f = pp->rx_fis + RX_FIS_SDB;
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u32 f0 = le32_to_cpu(f[0]);
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if (f0 & (1 << 15))
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sata_async_notification(ap);
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if (pp->fbs_enabled)
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WARN_ON_ONCE(1);
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else {
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const __le32 *f = pp->rx_fis + RX_FIS_SDB;
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u32 f0 = le32_to_cpu(f[0]);
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if (f0 & (1 << 15))
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sata_async_notification(ap);
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}
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}
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}
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@ -2321,6 +2405,15 @@ static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
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if (qc->tf.protocol == ATA_PROT_NCQ)
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writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
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if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) {
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u32 fbs = readl(port_mmio + PORT_FBS);
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fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
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fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET;
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writel(fbs, port_mmio + PORT_FBS);
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pp->fbs_last_dev = qc->dev->link->pmp;
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}
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writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
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ahci_sw_activity(qc->dev->link);
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@ -2333,6 +2426,9 @@ static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
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struct ahci_port_priv *pp = qc->ap->private_data;
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u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
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if (pp->fbs_enabled)
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d2h_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ;
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ata_tf_from_fis(d2h_fis, &qc->result_tf);
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return true;
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}
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@ -2381,6 +2477,71 @@ static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
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ahci_kick_engine(ap);
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}
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static void ahci_enable_fbs(struct ata_port *ap)
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{
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struct ahci_port_priv *pp = ap->private_data;
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void __iomem *port_mmio = ahci_port_base(ap);
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u32 fbs;
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int rc;
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if (!pp->fbs_supported)
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return;
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fbs = readl(port_mmio + PORT_FBS);
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if (fbs & PORT_FBS_EN) {
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pp->fbs_enabled = true;
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pp->fbs_last_dev = -1; /* initialization */
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return;
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}
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rc = ahci_stop_engine(ap);
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if (rc)
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return;
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writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS);
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fbs = readl(port_mmio + PORT_FBS);
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if (fbs & PORT_FBS_EN) {
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dev_printk(KERN_INFO, ap->host->dev, "FBS is enabled.\n");
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pp->fbs_enabled = true;
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pp->fbs_last_dev = -1; /* initialization */
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} else
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dev_printk(KERN_ERR, ap->host->dev, "Failed to enable FBS\n");
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ahci_start_engine(ap);
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}
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static void ahci_disable_fbs(struct ata_port *ap)
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{
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struct ahci_port_priv *pp = ap->private_data;
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void __iomem *port_mmio = ahci_port_base(ap);
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u32 fbs;
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int rc;
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if (!pp->fbs_supported)
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return;
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fbs = readl(port_mmio + PORT_FBS);
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if ((fbs & PORT_FBS_EN) == 0) {
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pp->fbs_enabled = false;
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return;
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}
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rc = ahci_stop_engine(ap);
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if (rc)
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return;
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writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS);
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fbs = readl(port_mmio + PORT_FBS);
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if (fbs & PORT_FBS_EN)
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dev_printk(KERN_ERR, ap->host->dev, "Failed to disable FBS\n");
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else {
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dev_printk(KERN_INFO, ap->host->dev, "FBS is disabled.\n");
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pp->fbs_enabled = false;
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}
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ahci_start_engine(ap);
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}
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static void ahci_pmp_attach(struct ata_port *ap)
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{
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void __iomem *port_mmio = ahci_port_base(ap);
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@ -2391,6 +2552,8 @@ static void ahci_pmp_attach(struct ata_port *ap)
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cmd |= PORT_CMD_PMP;
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writel(cmd, port_mmio + PORT_CMD);
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ahci_enable_fbs(ap);
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pp->intr_mask |= PORT_IRQ_BAD_PMP;
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writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
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}
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@ -2401,6 +2564,8 @@ static void ahci_pmp_detach(struct ata_port *ap)
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struct ahci_port_priv *pp = ap->private_data;
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u32 cmd;
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ahci_disable_fbs(ap);
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cmd = readl(port_mmio + PORT_CMD);
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cmd &= ~PORT_CMD_PMP;
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writel(cmd, port_mmio + PORT_CMD);
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@ -2492,20 +2657,40 @@ static int ahci_pci_device_resume(struct pci_dev *pdev)
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static int ahci_port_start(struct ata_port *ap)
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{
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struct ahci_host_priv *hpriv = ap->host->private_data;
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struct device *dev = ap->host->dev;
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struct ahci_port_priv *pp;
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void *mem;
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dma_addr_t mem_dma;
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size_t dma_sz, rx_fis_sz;
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pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
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if (!pp)
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return -ENOMEM;
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mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma,
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GFP_KERNEL);
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/* check FBS capability */
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if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) {
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void __iomem *port_mmio = ahci_port_base(ap);
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u32 cmd = readl(port_mmio + PORT_CMD);
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if (cmd & PORT_CMD_FBSCP)
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pp->fbs_supported = true;
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else
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dev_printk(KERN_WARNING, dev,
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"The port is not capable of FBS\n");
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}
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if (pp->fbs_supported) {
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dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ;
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rx_fis_sz = AHCI_RX_FIS_SZ * 16;
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} else {
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dma_sz = AHCI_PORT_PRIV_DMA_SZ;
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rx_fis_sz = AHCI_RX_FIS_SZ;
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}
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mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL);
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if (!mem)
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return -ENOMEM;
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memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
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memset(mem, 0, dma_sz);
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/*
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* First item in chunk of DMA memory: 32-slot command table,
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@ -2523,8 +2708,8 @@ static int ahci_port_start(struct ata_port *ap)
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pp->rx_fis = mem;
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pp->rx_fis_dma = mem_dma;
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mem += AHCI_RX_FIS_SZ;
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mem_dma += AHCI_RX_FIS_SZ;
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mem += rx_fis_sz;
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mem_dma += rx_fis_sz;
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/*
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* Third item: data area for storing a single command
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