Minki/linux
1
0
Fork 1
mirror of https://github.com/torvalds/linux.git synced 2024-11-16 00:52:01 +00:00
Code Issues Packages Projects Releases Wiki Activity

i2c: sirf: tune the divider to make i2c bus freq more accurate

Browse Source 
In prima2 and atlas7, due to some hardware design issue. we
need to adjust the divider ratio a little according to i2c
bus frequency ranges.
Since i2c is open drain interface that allows the slave to
stall the transaction by holding the SCL line at '0', the RTL
implementation is waiting for SCL feedback from the pin after
setting it to High-Z ('1'). This wait adds to the high-time
interval counter few cycles of the input synchronization
(depending on the SCL_FILTER_REG field), and also the time it
takes for the board pull-up resistor to rise the SCL line.
For slow SCL settings these additions are negligible, but they
start to affect the speed when clock is set to faster frequencies.
This patch is based on the actual tests, and it makes SCL more
accurate.

Signed-off-by: Guoying Zhang <Guoying.Zhang@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
This commit is contained in:
Guoying Zhang 2015-09-09 10:30:32 +00:00 committed by Wolfram Sang
parent 4c0657ae43
commit d64d45cb95
1 changed files with 22 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

26
drivers/i2c/busses/i2c-sirf.c
View File

@ -358,11 +358,29 @@ static int i2c_sirfsoc_probe(struct platform_device *pdev)
if (err < 0)
bitrate = SIRFSOC_I2C_DEFAULT_SPEED;
if (bitrate < 100000)
regval =
(2 * ctrl_speed) / (bitrate * 11);
else
/*
* Due to some hardware design issues, we need to tune the formula.
* Since i2c is open drain interface that allows the slave to
* stall the transaction by holding the SCL line at '0', the RTL
* implementation is waiting for SCL feedback from the pin after
* setting it to High-Z ('1'). This wait adds to the high-time
* interval counter few cycles of the input synchronization
* (depending on the SCL_FILTER_REG field), and also the time it
* takes for the board pull-up resistor to rise the SCL line.
* For slow SCL settings these additions are negligible,
* but they start to affect the speed when clock is set to faster
* frequencies.
* Through the actual tests, use the different user_div value(which
* in the divider formular 'Fio / (Fi2c * user_div)') to adapt
* the different ranges of i2c bus clock frequency, to make the SCL
* more accurate.
*/
if (bitrate <= 30000)
regval = ctrl_speed / (bitrate * 5);
else if (bitrate > 30000 && bitrate <= 280000)
regval = (2 * ctrl_speed) / (bitrate * 11);
else
regval = ctrl_speed / (bitrate * 6);
writel(regval, siic->base + SIRFSOC_I2C_CLK_CTRL);
if (regval > 0xFF)