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gpio: mvebu: clear irq in edge cause register before unmask edge irq

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When input GPIO set from 0 to 1, the interrupt bit asserted in the GPIO
Interrupt Cause Register (ICR) even if the corresponding interrupt
masked in the GPIO Interrupt Mask Register.

Because interrupt mask register only affects assertion of the interrupt
bits in Main Interrupt Cause Register and it does not affect the
setting of bits in the GPIO ICR.

So, there is problem, when we unmask interrupt with already
asserted bit in the GPIO ICR, then false interrupt immediately occurs
even if GPIO don't change their value since last unmask.

Signed-off-by: Maxim Kiselev <bigunclemax@gmail.com>
Link: https://lore.kernel.org/r/20200115073811.24438-1-bigunclemax@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Maxim Kiselev 2020-01-15 10:38:11 +03:00 committed by Linus Walleij
parent 366950eeb6
commit d5331ec2cc
1 changed files with 1 additions and 0 deletions
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drivers/gpio/gpio-mvebu.c
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@ -431,6 +431,7 @@ static void mvebu_gpio_edge_irq_unmask(struct irq_data *d)
u32 mask = d->mask; u32 mask = d->mask;
irq_gc_lock(gc); irq_gc_lock(gc);
mvebu_gpio_write_edge_cause(mvchip, ~mask);
ct->mask_cache_priv |= mask; ct->mask_cache_priv |= mask;
mvebu_gpio_write_edge_mask(mvchip, ct->mask_cache_priv); mvebu_gpio_write_edge_mask(mvchip, ct->mask_cache_priv);
irq_gc_unlock(gc); irq_gc_unlock(gc);